JP2000091923A - Information processing unit and information processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an analog signal with high quality by eliminating a noise component from the analog signal. SOLUTION: A low-order bit round-off circuit 4 receives digital data resulting from an A/D converter 2 that converts an analog signal fed via input terminal 1. The low-order bit round-off circuit 4 applies round-off processing to prescribed low-order bits of the digital data on which a noise component is superimposed and gives the processed data to a data recovery circuit 6. The data recovery circuit 6 recovers the digital data in an original bit number (or digital data in a bit number more than the original bit number) based on remaining high- order bits by the round-off processing to eliminate the noise component from the digital data. Then a D/A converter 7 converts the digital data whose noise component is eliminated into an analog signal and provides an output of it. Thus, the analog signal with high quality can be obtained by eliminating the noise component superimposed on the original analog signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and an information processing method suitable for, for example, a signal processing system of an analog cassette tape recorder, a television receiver or an analog video tape recorder, and more particularly to an analog audio. Analog information such as information and analog video information,
The present invention relates to an information processing apparatus and an information processing method for removing noise components for reproduction.

[0002]

2. Description of the Related Art Conventionally, there are many devices that handle audio information or video information in an analog manner, such as an analog cassette tape recorder, a television receiver, and an analog video tape recorder. For example, in the case of an analog cassette tape recorder device, audio information longitudinally recorded on a cassette tape is traced by a magnetic head and reproduced, and supplied to a speaker unit via an amplifier, a low-pass filter or the like to obtain an audio output. It has become. In the case of a television receiver, an image is obtained by driving, for example, an electron gun and performing interlaced scanning of a cathode ray tube based on image information selected by a tuner section.

[0003]

However, when audio information, video information, and the like are handled in an analog manner, noise tends to be superimposed on the information, and the quality of the information may be impaired. For this reason, at present, devices that handle information digitally, including noise countermeasures, are increasing, but even when audio information or video information is handled digitally, to obtain an audio output through a speaker device, It is necessary to convert digital audio information into analog audio information, and to obtain a display image via a monitor device, it is necessary to convert digital video information into analog video information. Finally, it is necessary to handle information in an analog manner as described above, which causes the problem of noise.

The present invention has been made in view of the above-described problems, and has as its object to provide an information processing apparatus and an information processing method capable of obtaining high-quality analog information in a form from which noise components have been removed. I do.

[0005]

According to the present invention, there is provided an information processing apparatus comprising: an analog / digital converter for converting analog information into digital information for solving the above-mentioned problems; and a digital signal from the analog / digital converter. A lower bit truncation unit that truncates predetermined lower bits of information and outputs the digital information, based on the digital information whose lower bits are truncated from the lower bit truncation unit, based on the digital information of the original number of bits including the truncated lower bits. Information reproducing means for reproducing information or digital information having a larger number of bits than the original digital information, and digital / analog converting means for converting the digital information reproduced by the information reproducing means into analog information and outputting the analog information And

Further, in order to solve the above-mentioned problems, the information processing method according to the present invention comprises the steps of: converting analog information into digital information; and discarding predetermined lower bits of the digital information formed in the step. Reproducing digital information of the original number of bits including the truncated lower bits, or digital information of a larger number of bits than the digital information of the original bits, based on the digital information with the lower bits truncated in the step. And converting the digital information reproduced in the step into analog information and outputting the analog information.

In such an information processing apparatus and information processing method, lower bits containing a large amount of noise components are discarded, and digital information having the original number of bits is reproduced based on the remaining upper bits, or is larger than the original number of bits. The digital information of the number of bits is reproduced, and this is converted into an analog signal and output. This makes it possible to obtain high-quality analog information from which noise components have been removed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] (Configuration of First Embodiment) An information processing apparatus according to a first embodiment of the present invention is, for example, an analog tape recorder as shown in FIG. An input terminal 1 to which an analog signal such as an analog audio signal from a device or an analog video signal received by a television receiver is supplied, and an A / D converter for converting the analog signal into digital data of a predetermined number of bits 2
A noise component removing circuit 3 for removing a noise component from the digital data; a noise detecting unit 5 for detecting a noise level superimposed on the digital data from which the noise component has been removed; A lower bit truncation circuit 4 for truncating (or rounding) predetermined lower bits according to the noise level.

Further, the information processing apparatus according to the first embodiment forms digital data of the total number of bits including the truncated lower bits based on the digital data whose predetermined lower bits have been truncated. By that
A data reproduction circuit 6 for reproducing digital data in a form in which noise components have been removed, and an output terminal 8 for converting digital data reproduced by the data reproduction circuit 6 into an analog signal and outputting the analog signal via an output terminal 8 Have.

(Operation of the First Embodiment) In such an information processing apparatus, when an analog signal is supplied through an input terminal 1, the analog signal is converted into N bits (N is For example, the data is converted into digital data of a predetermined natural number (16 bits or the like) and supplied to the noise component removing circuit 3.

(Operation of Noise Component Removal Circuit 3) The noise component removal circuit 3 includes a high-pass filter (HPF) 11 and an operation unit 12, as shown in FIG. H
The PF 11 removes a DC component (offset component) of the digital data supplied from the A / D converter 2 and supplies the same to the arithmetic unit 12. The arithmetic unit 12 outputs the output S ′ of “SX” when the digital data S supplied from the HPF 11 is (1) S> X, and outputs “2” when −Y ≦ S ≦ X. An output S ′ of “0” is output, and (3) an output S ′ of “S + Y” is output when S <−Y. Thereby, the offset generated in the A / D converter 2 can be removed by the HPF 11, and the HPF 11
Is digital data S that swings to the + and-sides around the zero level.

The arithmetic unit 12 shifts the input signal of S ≧ 0 to the zero level side by X, shifts the input signal of S <0 to the zero level side by Y, as shown in FIG. S
An input signal of ≤X is output as a zero-level output signal S '.

More specifically, the arithmetic section 12 is composed of adders 15 and 16, a selector (SEL) 17, and a determination section 18, as shown in FIG. The adders 15 and 16
The digital data supplied from the HPF 11 and −X, Y are added, and the added output is supplied to the SEL 17, and the sign bits signA, signB of the added output are supplied to the determination unit 18. SEL17 has all "0"
Is also supplied. The determination unit 18 is
A selection signal corresponding to the values of A and signB is supplied to SEL17. The SEL 17 selects one of the three inputs according to the selection signal and outputs it as an output signal S ′.
Note that the values of X and Y are set to values that have little effect on the audibility due to noise measurement during silence, actual listening, and the like. This X
And the value of Y may be fixed values, or the listener may be arbitrarily settable.

Thus, when S> X, signA =
0, signA = 1 when S ≦ X, si when S ≧ −Y
Since signB = 1 when gnB = 0 and S <−Y, when signA = 0 and signB = 0,
The output of the adder 15 is selected, and signA = 1, sig
When nB = 0, all “0” is selected and s
When signA = 1 and signB = 1, the output of the adder 16 is selected, and the output signal S ′ after the above-described level conversion can be obtained.

The output signal S 'is supplied to the noise component removing circuit 3 when digital data having a waveform having a large amplitude as shown by a dotted line in FIG.
As a result of the processing of the arithmetic unit 11 and the arithmetic unit 12, a signal waveform is obtained in which the amplitude of the digital data is shifted to the zero level side as shown by the solid line in FIG. In this case, the waveform of the output signal S ′ is the original waveform (the waveform shown by the dotted line in FIG. 5A).
Is slightly distorted with respect to, but since there is no sudden change in level, there is almost no problem in terms of audibility. In addition, by providing a filter at a stage subsequent to the noise component removing circuit 3, the waveform of the output signal S 'can be made closer to the original waveform.

In the case where digital data having a waveform having a small amplitude as shown by a dotted line in FIG. 5B is supplied to the noise component removing circuit 3 as the output signal S ′, FIG. At a zero level as shown by the solid line. For this reason,
Noise can be effectively removed even when there is no sound or when the level of input digital data is low.

As described above, the noise component removing circuit 3
After removing the DC component of the input digital data, the output is shifted to the zero level by a predetermined value, and the output smaller than the predetermined value is output as the zero level, so that the silent It is possible to effectively remove noise even when digital data of a low level is input, and the S / N of digital data to be output is reduced.
The ratio can be good.

(Operation of Lower Bit Truncation Circuit 4) Next, the digital data from which the noise component has been removed by the noise component removal circuit 3 is supplied to the lower bit truncation circuit 4 and the noise detection circuit 5. The noise detection circuit 5 detects the level of the noise component superimposed on the digital data supplied from the noise component removal circuit 3 (the level of the noise component that cannot be completely removed by the noise component removal circuit 3), and detects this noise. The output is supplied to the lower bit truncation circuit 4.

The lower bit truncation circuit 4 truncates the lower bits of the digital data according to the noise detection output from the noise detection circuit 5 and supplies it to the data reproduction circuit 6. Specifically, the lower bit truncation circuit 4
Suppose that the digital data supplied to the digital signal is, for example, 16 bits, the lower bit truncation circuit 4 truncates the lower 2 bits of the digital data and converts the 14-bit digital data into a data reproduction circuit 6 according to the noise detection output. Or 12-bit digital data is supplied to the data reproducing circuit 6 by discarding the lower 4 bits of the digital data. The number of lower bits to be discarded is appropriately varied according to the noise detection output from the noise detection circuit 5.

(Operation of Data Reproduction Circuit 6) Next, the data reproduction circuit 6 has the configuration shown in FIG. 6A or FIG. 6B. N of the sampling period Ts in which
The bit digital data is repeatedly supplied to the data generator 22 via the input terminal 21. The data reproducing circuit 6 up-samples, for example, N-bit digital data into M-bit digital data (N <M). In this sense, in FIG. Is shown. Note that the data reproducing circuit 6 performs N
What outputs bit digital data as N-bit digital data may be provided.

(Operation of Repetition Data Generation Unit 22) The repetition data generation unit 22 performs the sampling cycle T based on the digital data of the sampling cycle Ts as shown in FIG.
The digital data of s / K is formed (K is a natural number of 2 or more: when K = 2, the sampling period is Ts / 2). In the following, the description will be made on the assumption that K is 2 in order to facilitate understanding.

More specifically, the repetitive data generator 22
Has the configuration shown in FIG.
The bit digital data is supplied to the serial / parallel converter 27 via the input terminal 22a. FIG. 8B shows N-bit digital data D1, D2,... Supplied as serial data for each sampling period Ts. The serial-to-parallel converter 7 is supplied with a bit clock BCLK1 as shown in FIG. 8C via the input terminal 27a.
Based on the bit clock BCLK1, the serial / parallel converter 7 outputs digital data D1,
., Are converted into parallel data D1, D2,... As shown in FIG.

A latch clock LTCLK having the same period as the sampling period Ts as shown in FIG. 8E is supplied to the latch memory 28.
CLK, the parallel data D1, D2,.
Is latched as shown in FIG.
9 respectively. The parallel-to-serial converter 29 includes FIG.
As shown in (g), a load clock LDCLK having a cycle of Ts / 2 having a cycle of 1/2 of the sampling cycle Ts is supplied through an input terminal 29b, and data is outputted based on the load clock LDCLK. By performing the load operation, the parallel data D1 and D2 are output at Ts / 2 cycle.
Load….

As a result, the parallel data D1, D1, D2,..., D1, D1, D2, D2,...
2, D2... Are loaded. The parallel-to-serial converter 29 converts the parallel data D1, D1, D2, D2,... Loaded in the Ts / 2 cycle based on the bit clock BCLK2 having the cycle of Ts / 2 supplied through the input terminal 29a. And read them out as serial data, and read out the serial data D1, D1, D2, D2
.. Are output via the output terminal 22b. Thereby, as shown in FIG. 8 (i), it is possible to generate repetitive data (the serial data D1, D1, D2, D2...) Having a cycle of Ts / 2. The repetition data is supplied to the resolution improving signal processing unit 23 shown in FIG.

(Effect of Repetitive Data Generating Unit 22) FIG. 9A shows how the digital value of digital data (digital data of the sampling period Ts) changes when such a repetitive data generating unit 22 is not used. Repetitive data generator 2
2 using digital data (sampling period Ts / 2
FIG. 9 shows how the digital value of the digital data changes).
(B) shows each. As can be seen by comparing FIGS. 9 (a) and 9 (b), the changing mode of the digital values sequentially arranged on the time axis shown in FIG. 9 (a) is a → b → d → f → h → i →
k → m → n, which is the same as the change mode of the digital values sequentially arranged on the time axis shown in FIG. 9B, but the sampling period of digital data is set to Ts / By setting it to 2, each digital value to A, B, C, D, and E can be inserted between the digital values of a to n in FIG. The number of data can be twice as large as that in the case described above. Therefore, the interpolation processing performed by the resolution improving signal processing unit 23 described below can be improved.

(Operation of Signal Processing Unit 23 for Improving Resolution) The signal processing unit 23 for improving resolution has the configuration shown in FIG. 10, and has a sampling period of Ts / 2 by the repetitive data generating unit 22. Repetitive data (digital data)
Is supplied to the delay unit 30 via the input terminal 23a, and is also supplied to the change pattern determination unit 32.

(Operation of the Change Pattern Judgment Unit 32) The change pattern judgment unit 32 is supplied with a pulse Pfs having a sampling period Ts / 2 via an input terminal 38, and supplies the pulse Pfs based on the pulse Pfs. The stored digital data is stored, the data change pattern of the stored digital data is determined, and the determination output is supplied to the (MN) bit signal generator 33.

Specifically, FIG. 12A is a diagram showing a waveform of N-bit digital data at each of the times t1, t2, t3,... Of the sampling period Ts / 2. This figure 1
2 (a), the digital value of the N-bit digital data holds the same digital value from time t1 to time t2, but the digital value changes to a large value at time t3. ing. Also, from time t25 to time t
Although the same digital value is held until immediately before 31, the digital value changes to a small value at time t31. Such a changing point includes a changing point A to a changing point 図 in FIG. The digital value changes between two adjacent change points, such as between the change point A and the change point B, between the change point B and the change point C, among the change points A to ヲ. There is no.

Of the change points a to ヲ, the change point a at time t3, the change point b at time t7, the change point c at time t13, the change point d at time t25, and the change point d at time t51. At each change point such as a change point nu at time t55 and a change point ル at time t59, the change patterns are such that the digital value increases. In FIG. 12B, a change pattern in which the digital value increases is indicated by an upward arrow with a letter D (Down). Further, of each of the change points A to ヲ, a change point E at time t31;
At each change point such as a change point at time t37, a change point at time t41, a change point at time t47, and a change point at time t63, the change pattern is such that the digital value decreases. I have. In FIG. 12B, a change pattern in which the digital value decreases is represented by a letter U (Up).
Are indicated by downward arrows.

FIG. 12 (c) shows one step (1/1) for each of the change points i to d, reel, etc., each change point showing a change pattern of increase, irrespective of the amount of increase in the digital value at each change point. ^2N resolution = resolution of 1 LSB of N bits), and the digital value at each change point is reduced at each change point, such as ホ, 変 化, etc., where each change point indicates a change pattern of decrease. FIG. 11 is a waveform diagram formed by reducing the data level by one step (1/2 ^N resolution = N-bit 1 LSB resolution) regardless of the amount.

Here, the solid line S connecting the points a to n of the digital waveform shown in FIG. 13 in order is a resolution of 1 / Nth power of the analog signal at every sampling period Ts, that is,
It shows a state of change of digital data sampled and formed at a resolution of 1 LSB of N bits. The original analog signal corresponding to the digital waveform indicated by the solid line S in FIG. 13 exists in a region indicated by oblique lines in FIG. Therefore, between the original analog signal and the analog signal reproduced based on the N-bit digital data, 1/2 ^N
An error within ± 0.5 LSB occurs for 1 LSB of the resolution of (1). For this reason, the resolution improving signal processing unit 23 performs the following data processing based on the N-bit digital data to form M-bit digital data in which the error is minimized (M
> N).

That is, as shown in FIG. 12A, for example, assuming that transition points A to ヲ occur sequentially in N-bit digital data, four consecutive transition points of digital values are set as one set of transition points. When viewed as a point group, the change patterns of the digital values of the four change points a to d in the first change point group are “1”, “1”, and “1” as shown in FIG.
It becomes "1". Similarly, the change patterns of the digital values of the four change points b to e of the next change point group are "1", "1", "1", and "0" as shown in FIG. The change patterns of the digital values of the four change points c to f of the change point group are “1”, “1”, and “0” as shown in FIG.
It becomes "0". The change pattern of the digital value of each change point of each change point group based on such a concept is 00
00,0001,0010,0011,0100,01
01,0110,0111,100O, 1001,10
10, 1011, 1100, 1101, 1110, 11
There are a total of eleven 16 types of change patterns.

As shown in FIG. 14, the change pattern determining section 32 includes a signal waveform change information generating section 32A, a signal waveform change mode information generating section 32B, an address generating section 32C, and a change pattern determining circuit 32D. Have been.

The input terminal 32a of the signal waveform change information generating section 32A is supplied with N-bit digital data to be processed for the information signal, and the input terminal 38 is supplied with a clock signal pulse Pfs. . As the clock signal pulse Pfs, a pulse having the same repetition frequency as the sampling frequency fs which is twice the sampling frequency used when forming N-bit digital data is used. N supplied to the signal waveform change information generation unit 32A
The bit digital data is D flip-flop 40,
It is supplied to the magnitude comparator 41 and the comparator 42, respectively.

The D flip-flop 40 has an input terminal 3
8, a clock signal Pfs is supplied. At the rising edge of the clock signal Pfs, for example, N-bit digital data is latched and supplied to the magnitude comparator 41 and the comparator 42. The clock signal Pfs is also supplied to the address counter 45, and the address counter 45 counts the number of clocks of the supplied clock signal Pfs, and uses this count value as address data for the first address of the address generator 32C. Data input terminal (D) of the D flip-flop 47a of the stage
To supply.

The magnitude comparator 41 includes N-bit digital data (digital data A) supplied directly through the input terminal 32a and N-bit digital data (digital data B) latched by the D flip-flop 40. Compare the size of The magnitude comparator 41 has A> B output terminals 41a, A
= B output terminal 41b and A <B output terminal 41c. When digital data A is larger than digital data B (A> B), A> B output terminal 41a. Is set to a high level (H) state, and the other output terminals 41b and 41c are set to a low level (L) state. When both the digital data A and B are equal, only the A = B output terminal 41b is set to the high level, and both the other output terminals 41a and 41c are set to the low level.
When the digital data B is larger than the digital data A, only the A <B output terminal 41c is set to the high level, and both the other output terminals 41a and 41b are set to the low level.

The comparator 20 compares the digital data A with the digital data B. If the digital data A is larger than the digital data B, that is, as shown in FIG.
(A) and (b), each of the change points a to d, r to r, etc.
When the change mode of the digital value at each change point is in the increasing state, the comparison output of the logical value “1” is generated regardless of the increase amount. When the digital data B is larger than the digital data A, that is, in FIG.
As shown in (b), when the changing mode of the digital value at each change point is in a decreasing state as in each of the changing points H to H, .DELTA. Occurs.
The comparison output of the logical value "1" or the logical value "0" is supplied to the data input terminal (D) of the first-stage D flip-flop 42a of the signal waveform change mode information generating unit 32B.

3 from the magnitude comparator 41
The OR circuit 43 to which the two outputs are supplied supplies the high-level output to the AND circuit 44 when the output from the A> B output terminal 41a or the output from the A <B output terminal becomes high level, In other cases, the low-level output is set to AN
It is supplied to the D circuit 44.

A gate pulse having a phase difference of 180 degrees is supplied to the AND circuit 44 through an input terminal 48 by inverting the clock signal pulse Pfs. Each time the value of the N-bit digital data changes, the AND circuit 44 forms a clock signal (CLK) at the timing of the gate pulse, and outputs the clock signal (CLK) to each of the D flip-flops 42a to 42d of the signal waveform change mode information generating unit 32B. The clock is supplied to the clock input terminal (CK) and the clock input terminal (CK) of each of the D flip-flops 47a to 47d of the address generating section 32C.

The address generator 32C reads the address data from the address counter 45 based on the clock signal CLK supplied from the AND circuit 44 by each of the D flip flops 47a to 47d, and supplies the read address data to the change pattern determining circuit 32D. I do. As a result, the change pattern determination circuit 32D is supplied with the address data at each of the change points A to 示 す shown in FIG. 12A at the time when the slope of the N-bit digital data changes.

The signal waveform change mode information generating section 32B
Reads the logical values "1" and "0" from the comparator 42 based on the clock signal CLK by the D flip flops 46a to 46d, and supplies them to the change pattern determining circuit 32D. As a result, the change pattern determination circuit 32D provides the logical value “1”,
"0" will be supplied.

The change pattern determination circuit 32D has the configuration shown in FIG.
To 16 types of change patterns (binary display,
Alternatively, the data pattern composed of four logical values supplied from the signal waveform variation mode information generating unit 32B is compared with each of the 16 types of variation patterns, and a matching variation pattern is determined. I do. Then, for example, the information signal indicating the type of the change pattern such as a numerical value set in the match circuit from which the match output was obtained, and the address data of each change point from the address generating unit 32C corresponding to the information signal are changed Output terminal 32b
To the (MN) bit signal generator 33 via the

(Operation of (MN) Bit Signal Generation Unit 33) The (MN) bit signal generation unit 33 mainly includes a random access memory (RAM), a read only memory (ROM), and a microprocessor. It comprises a control circuit and an arithmetic circuit. The form of each linear interpolation corresponding to each change pattern is stored in the ROM in advance. When the information signal indicating the type of the change pattern determined from the 16 types of change patterns by the change pattern determining unit 32 is supplied to the (MN) bit signal generation unit 33, the type of the change pattern is determined. The corresponding data in the form of linear interpolation is read from the ROM table, and based on the read data, the data between the change point of the first digital value and the change point of the second digital value of the corresponding change point group is read. As shown in FIGS. 15 to 22, the relationship between the second digital value change point and the third digital value change point of each change point group is related to the already applied linear interpolation mode. 1
A predetermined operation is performed to perform linear interpolation at a resolution of / 2 ^M (M> N).
Stored in AM sequentially.

More specifically, FIGS. 15 to 22 show the relationship between the second digital value change point and the third digital value change point corresponding to the digital value change mode of each change point group. It is a figure showing the mode of the linear interpolation performed. The display of # 1, # 2, # 3, and # 4 in the column of the change point in each figure indicates the first change point (# 1) and the second change point in four continuous change points on the time axis, respectively. A change point (# 2), a third change point (# 3), and a fourth change point (# 4) are shown, and the arrangement of numbers in the column of the change mode is four of the change point group. The change mode of the digital value at the change point is indicated by logical values “1” and “0” (“1” indicates an increase,
“0” decreases).

Also, the column of the interpolation form between # 1 and # 2,
And the convex and concave indications in the column of the interpolation mode between # 2 and # 3 indicate that the interpolation mode during each corresponding period is convex and concave, and the column of the interpolation mode between # 1 and # 2. , And the number in the column of the interpolation form between # 2 and # 3 (for example, a number such as 1-2 or 2.5-3)
Indicates a section in which linear interpolation is performed.
When "-" is displayed in the column of the interpolation mode between # 2 and # 3, it indicates that no interpolation is performed between # 2 and # 3. Further, when interpolation is performed for a period including the period between # 2 and # 3, the state of the interpolation is illustrated by a dotted line, and when interpolation is performed for a period including the period between # 1 and # 2, the interpolation is performed. The state is indicated by a solid line.

FIGS. 15 to 22 show the change patterns 1111, 1110, 1101, 1100, and 101 as the change patterns including four change points # 1, # 2, # 3, and # 4.
Although only eight kinds of change patterns of 1, 1010, 1000, and 1001 are shown, the above-mentioned sixteen kinds of change patterns include the eight kinds of change patterns and the logical values forming the eight kinds of change patterns. 15 is a combination of eight types of change patterns consisting of a number sequence obtained by reversing the numbers “1” and “0” in the number sequence shown in FIG.
22. Only by providing the data of the eight kinds of change patterns shown in FIG. 22, it is possible to perform the linear interpolation processing corresponding to all the 16 kinds of change patterns.

The linear interpolation pattern to be performed between the second digital value change point and the third digital value change point of each change point group, which is determined based on each change pattern, is determined as follows. Is performed as follows. That is, FIGS. 23A to 23D show four typical change patterns. FIG. 23A shows a change pattern in which the digital values of the four change points monotonically increase, and FIG. 23B shows the change pattern after the digital values of the four change points monotonically increase. FIG. 4C shows a change pattern which has turned to decrease, and FIG. 6C shows a change pattern which turns to decrease and then shows a mountain shape after the digital values of the four change points have increased, and FIG. This is a change pattern in which a digital value of one change point increases, then keeps a constant value, then turns to decrease and shows a mountain shape.

First, the linear interpolation performed by the inclined straight line e → f between the second change point # 2 and the third change point # 3 in FIG. middle point e between a and a and c at the third change point # 3
and a midpoint f between the points a and d at the second change point # 2 and a midpoint f between the cds at the third change point # 3. The difference is 1 LSB with a resolution of 1/2 ^N. The gradient of the interpolation line e → f used for the linear interpolation performed between the second change point # 2 and the third change point # 3 is the second change point # 2 and the third change point The distance bc to # 3, the middle point e between a and b at the second change point # 2, and the third change point #
3 and 1LSB having a resolution of 1/2 ^N indicated as a difference in height from the midpoint f between the cds, and is calculated by the following arithmetic expression.

[(1 LSB of 1/2 ^N resolution) ÷ (2
Distance b between the third change point # 2 and the third change point # 3
c)] Note that the distance bc between the second change point # 2 and the third change point # 3 is the difference between the address value of the second change point # 2 and the address value of the third change point # 3. Since the calculation is performed based on the difference, the calculation using this calculation expression can be easily performed.

Next, the linear interpolation performed by the inclined straight line e → g between the second change point # 2 and the third change point # 3 in FIG. At the middle point e between a and b at the third change point # 3
This is performed by a part of the straight line connecting the midpoint f between d and d.
As described above, the difference in height between the middle point e between a and b at the second change point # 2 and the middle point f between cd at the third change point # 3 is 1LSB with a resolution of 1 / ^2N. Because
An interpolation straight line e used for linear interpolation performed at a part between the second change point # 2 and the third change point # 3 →
The gradient of g is the second change point # 2 and the third change point # 3
, A middle point e between a and b at a second change point # 2, and a middle point f between cd and at a third change point # 3
1LS with 1/2 ^N resolution indicated as height difference from
It is obtained by performing an operation using the following expression using B and the following expression.

[(1 LSB of 1/2 ^N resolution) ÷ (2
Distance b between the third change point # 2 and the third change point # 3
c)] Next, in the case of the change pattern shown in FIG.
→ b → c → h, hypotenuse i → m passing through the midpoint k of this rectangular side a → b and hypotenuse m → J passing through the midpoint l of the rectangular side c → h
Since the areas of the triangles i → m → J having the same length are equal, if the length of the side a → b (or the length of the side c → h) of this rectangle is Hc, Hc performs an operation according to the following equation. It is required by

Hc = 2 × (rectangular side a−h) ÷ ｛(i →
a) + (a → h) + (h → j)｝ Note that i → a in this equation is a change point # 1 and a change point #
2 is 1/2 of the interval n → a, and h → j in this equation is 1/2 of the interval h → o between the change point # 3 and the change point # 4. For this reason, the change pattern determination unit 32
And the information indicating the change pattern, and # 1 to # 4 of each change point supplied to the (MN) bit signal generation unit 33.
, The value of i → a is １ ／ of the difference between the address value of the first change point # 1 and the address value of the second change point # 2, and h → J Is 3
It can be easily calculated as の of the difference between the address value of the fourth change point # 3 and the address value of the fourth change point # 4.

Here, there are three possible values of Hc: Hc is equal to 1, Hc is smaller than 1, and Hc is larger than 1.

First, when Hc is equal to 1 and when Hc is smaller than 1, the straight line i → shown in FIG.
The gradient of m and the gradient of the straight line m → j are respectively obtained by the following arithmetic expressions.

The gradient of the straight line i → m = Hc ÷ (the number of sampling periods Ts between a → r) The gradient of the straight line m → j = Hc ÷ (the sampling period Ts of r → h
The point r is a middle point of a → h, and is determined by the vertex m of the triangle i → m → J.

In each equation, (the number of sampling periods Ts between a → r) and (the number of sampling periods Ts between r → h)
Is determined by the following equation.

(Number of sampling periods Ts between a → r) = (a
→ number of sampling periods Ts between h) × (number of sampling periods Ts between n → a) ａ (number of sampling periods Ts between n → a) +
(Number of sampling periods Ts between h → o)｝ (number of sampling periods Ts between r → h) = (number of sampling periods Ts between a → h) − (sampling between a → r) (Number of periods Ts) (Number of sampling periods Ts between i → r) = (Number of sampling periods Ts between n → a ÷ 2) + (Number of sampling periods Ts between a → r) (r → the number of sampling periods Ts between J) = (the number of sampling periods Ts between h → o ÷ 2) + (the number of sampling periods Ts between r → h) Next, Hc is larger than 1. In this case, the gradient of the straight line (i → p) and the gradient of the straight line (q → j) in FIG. In this case, p
→ The gradient between q becomes zero.

The gradient of the straight line (i → p) = 1 ÷ (the number of sampling periods Ts between i → u) The gradient of the straight line (q → j) = 1 ÷ (the sampling period T between v → j)
(the number of s) Note that the points u and v in this arithmetic expression are i → a = a, respectively.
→ u, v → h = h → j are determined by the points p and q.

Further, (the number of sampling periods Ts between i → u) and (the number of sampling periods Ts between v → j) in this arithmetic expression are obtained by the following expressions.

(Number of sampling periods Ts between i → u) = 2 ×
(Number of sampling periods Ts between n → a / 2) = (number of sampling periods Ts between n → a) (number of sampling periods Ts between v → j) = 2 × (h → o The number of sampling periods Ts ÷ 2) = (the sampling period T between h → o)
(number of sampling periods Ts between u → v) = (number of sampling periods Ts between a → h) − ｛(number of sampling periods Ts between na) /
2) + (the number of sampling periods Ts of h → o {2)} There are 16 types of change patterns of each change point group as described above, and the linear interpolation patterns are shown in FIGS.
As shown in FIG. 2, there are four types of each change pattern. Therefore, in this embodiment, there are a total of 64 types of linear interpolation patterns (16 types × 4 types = 64) as the linear interpolation patterns.
type).

In the RAM, the points a, c, e, g, i, k, m, and m on the straight line ar shown in FIG. Point p,
A digital value corresponding to each point such as the point r, sampling position data indicating a sampling position on the time axis, gradient data indicating a gradient of the straight line ar, and the like are stored. The (MN) bit signal generator 33 sequentially reads out the M-bit linear interpolation data stored in the RAM, and forms M-N bit digital data from the most significant bit (MSB) of the linear interpolation data. .

More specifically, the linear interpolation data sequentially read out from the RAM is D1, D2, D3, D
4, D5, D6, D7 ... (M-N)
For example, the bit signal generation unit 33 sets the linear interpolation data D2 to (D1 + D2 + D3) / 3, the linear interpolation data D3 to (D2 + D3 + D4) / 3, the linear interpolation data D4 to (D3 + D4 + D5) / 3, and the linear interpolation data D5 to (D3 + D4 + D5) / 3. D4 + D5 + D6) / 3, for example, by calculating the average value of each linear interpolation data D1, D2, D3,... Over a period of three sampling periods,
The linear interpolation data D1, D2, D3,... Are rounded to form (MN) bits of digital data. Note that the period of the sampling cycle for calculating the average value is not limited to such three sampling cycles, but may be any plural number such as two sampling cycles, four sampling cycles, or the like. The period of the sampling cycle may be used.

FIG. 24 shows an example of an interpolation state in which averaging and rounding processes are performed on the linear interpolation data during four sampling periods. As can be seen from FIG. 24, by executing the averaging and rounding processing, the solid line L in FIG.
The linear interpolation state indicated by c can be changed to a curve interpolation state indicated by a dotted line Sc in FIG.

When performing the rounding process, for example, when the gradient of the interpolation line is small, the number of sampling periods used for averaging is increased, and when the gradient of the interpolation line is small, the number of sampling periods used for averaging is increased. When the direction of the gradient of the interpolation line is changed (convex or concave portion), the number of sampling periods used for averaging is changed, such as increasing the number of sampling periods used for averaging. This makes it possible to perform a favorable interpolation state changing process.

However, when the number of sampling periods used for averaging is changed in accordance with the magnitude of the gradient of the interpolation line, portions where the direction of the gradient of the interpolation line is changed (convex and concave portions).
, The area surrounded by the interpolation curve is N 2
There may be a problem that the area is smaller than the rectangular area of the convex and concave portions surrounded by a straight line having a resolution of 1LS3, which is 1 / the power. In this case, linear interpolation is performed in a state where the value of Hc described with reference to FIGS. 23C and 23D is increased in advance, and the interpolation straight line is rounded. The inconvenience can be prevented by making the area of the rectangular portion equal to the rectangular area of the convex and concave portions surrounded by a straight line having a resolution of 1 LSB of 1 / N. it can.

The digital data of (MN) bits thus formed are supplied to the adder 35 and the selected terminal 37a of the changeover switch 37, respectively. The M-bit digital data in a linearly interpolated state used when forming (M-N) bits of digital data and predetermined information described below are supplied to the offset generator 34.

(Operation of Offset Value Generating Unit 34) 1/2
The linear interpolation data of ^M resolution is stored.
-N) In the RAM of the bit signal generation unit 33, FIG.
Digital values corresponding to points a, c, e, g, i, k, m, p, r, etc. on the straight line ar in (a) to (c), time axis Data on the sequential sampling positions above, data on the gradient of the straight line ar, and the like are stored. The offset value generating section 34 shown in FIG. 10 is a digital data (for example, points a, c, and e on the straight line ar) stored in the memory supplied from the RAM of the (MN) bit signal generating section 33. , Point g, point i, point k, point m, point p, point r
Step-like waveforms as shown in FIGS. 25 (a) to 25 (c), for example, using digital values corresponding to each point, etc.), data on sequential sampling positions on the time axis, data on the gradient of the straight line ar, and the like. Is shifted on the time axis by の of the sampling period, and generates an offset value having a staircase waveform as shown in FIGS.

The straight line ar shown in FIGS.
It corresponds to the straight line ar shown in FIGS.
The intersections of the straight lines ar shown in FIGS. 26A to 26C and the vertical lines shown at the respective sampling positions are shown in FIGS. 25A to 25C.
Correspond to points a, c, e, g, i, k, m, and p. 26A to 26C, in order to simplify the description of the drawings, FIG.
26 (a), only alphabets a, b, c (symbols without dashes) are shown in FIG. 26 (a). It is stopped in. 26 (a) to 26 (c), a ', c', e ', g', i ', k', m ',
The digital value indicated by the position of each point such as p ′ is shown in FIG.
A, c, e, g, i, shown in (a) to (c),
It is shown that a digital value indicated by the position of each of k, m, and p is obtained by giving a predetermined offset value (for example, a → a ′, c → c ′...).

The offset values, for example, a → a ′, c → c ′, etc., generated by the offset value generator 34 are sampling positions sequentially arranged on the time axis at time intervals of the sampling period Ts. And the height of the intersection of the perpendicular set at a position intermediate between two adjacent sampling positions and the straight line ar (the straight line ar in FIG. 26 corresponding to the straight line ar shown in FIG. 25); It is of a size indicated as the difference between the vertical line set at the sampling position immediately before the time position of the intersection on the time axis and the height of the intersection with the straight line ar.

In FIG. 26C, at times t1, t2,
t3... indicate sampling positions sequentially arranged on the time axis, and the interval T between the two successive sampling positions described above.
1, T2 and the like are sampling periods (Ts). D1 is a digital value at the sampling position at time t1, D2 is a digital value at the sampling position at time t2, and D3 is time t3.
, And the digital values D1, D2, D3, etc., are as described above (M−
N) Sequential sampling stored in a memory that stores linear interpolation data having a resolution of 1 / Mth power (where M> N) calculated by the bit signal generator 13 The digital value at the position (eg FIG.
Digital values corresponding to points a, c, e, g, i, k, m, p, r, etc. on the straight line ar described with reference to FIG. ).

In FIG. 26 (c), D1, D
Lines L connecting the points 2 and D3 are shown in FIGS. 25 (a) to 25 (c).
And a straight line shown as corresponding to the straight line ar shown in FIGS. FIG. 26 (c)
At a time position [t1 intermediate between time t1 and time t2.
+ (T1 / 2)], and a vertical dotted line at a time position [t2 + (T2 / 2)] between the time t2 and the time t3 for simplification of description. The digital value D at the sampling position at time t1 shown in FIG.
1 ′, digital value D2 ′ at the sampling position at time t2
Are the digital values D at the sampling position at the time t1.
1. The digital value D2 at the sampling position at time t2 is:
This is a new digital value obtained by adding a predetermined offset value d.

The offset value generating section 34 is configured as shown in FIG.
A predetermined offset value d as shown as “d” is generated in the inside, and this offset value d is obtained from the gradient of a straight line L indicated by digital data having a resolution of 1/2 ^M in a linearly interpolated state. Required angle θ,
Using a numerical value of 2/1 (T1 / 2, T2 / 2: generally represented as 1/2 of Ts / 2) of the sampling period, an offset value d is set as d = (Ts / 4) cotθ. Generate.

That is, the offset value generating section 34 calculates the difference between the digital values of two adjacent digital data of the digital data having the resolution of 1/2 ^M in the linearly interpolated state in the linear section having the same gradient. / 2 (for example, d = (D2−D1) / 2) is set as a predetermined offset value d. Further, for digital data having a resolution of 1/2 ^M in a linear section having the same gradient and linearly interpolated, the section length is n times the sampling period Ts (n
Is a natural number, for example, d = (N-bit 1
LSB) / 2n, 1LSB resolution of 1/2 ^N
Is set as a predetermined offset value d. The offset value d formed by the offset value generating section 34 is supplied to the adder 35 shown in FIG.

(Operation of Adder 35) The adder 35
-N) By adding the MN bits of digital data supplied from the bit signal generation unit 33 and the offset value supplied from the offset value generation unit 34, the sampling period Ts / 2 on the time axis M-bit digital data shifted (offset) by の is supplied to the selected terminal 37 b of the changeover switch 37 and the overflow detector 36.

(Operation of Overflow Detection Unit 36) When the digital data supplied from the adder 35 does not exceed 1 LSB of N bits, the overflow detection unit 36 selects the selected terminal 37b by the selection terminal 37c. The switching of the changeover switch 37 is controlled. As a result, the digital data supplied from the adder 35 becomes N-bit 1L.
If it does not exceed SB, the digital data formed by the adder 35 (digital data to which the offset value d has been added) is supplied to the adder 31 via the changeover switch 37. Also, the overflow detection unit 3
6 is a selection terminal 37c when the digital data supplied from the adder 35 exceeds 1 LSB of N bits.
Switch 37 so that the selected terminal 37a is selected with
Is switched. Thereby, when the digital data supplied from the adder 35 exceeds 1 LSB of N bits, the MN having the resolution of 1/2 ^M formed by the (MN) bit signal generation unit 33 is used. The digital data for the bits is supplied to the adder 31 via the changeover switch 37.

(Operation of Delay Unit 30) The delay unit 30 repeats the delay of the time required for each digital data to be supplied to the addition unit 31 via the changeover switch 37 from the repetition data generation unit 22 to the input terminal 23a. It is applied to the N-bit digital data supplied through the interface and supplied to the adder 31.

(Operation of Addition Unit 31) The addition unit 31 converts the MN-bit digital data supplied through the changeover switch 37 into the least significant bit of the N-bit code information supplied from the delay unit 30. By performing addition processing so as to be continuous, for example, digital data of M pits as shown in FIG. 26A is formed, and this is output via the output terminal 23b to FIG. 6A or FIG. Is supplied to the low-pass filter 24 shown in FIG.

Digital data of M pits formed by the information processing apparatus of the embodiment shown in FIG. 26A and M bit data formed by the conventional information processing apparatus shown in FIG. As shown in FIG. 26B, the polygon a → a ′ →
b ′ → c ′ → d ′ → e ′ → f ′ → g ′ → h ′ → u and polygon r → v → i ′ → j ′ → k ′ → 1 ′ → m ′ → n ′ →
FIG. 25 shows a comparison result between the areas of two polygons p ′ → q ′.
(C) polygon b → c → d → e → f → g → h → u,
And the polygon r → v → i → j → k → l → m → n → p → q, as can be seen from the comparison result of the area of the two polygons. It can be seen that the data processing described above can obtain digital data with extremely good signal quality.

(Operation of Low-pass Filter 24) The low-pass filter 24 uses a Nyquist frequency of fs / 4 corresponding to digital data having a sampling frequency fs / 2 corresponding to the sampling period Ts / 2 as a cutoff frequency. The data reproducing circuit 6 shown in FIG.
In this case, the low-pass filter 24 removes the frequency components higher than the cut-off frequency, so that M-bit digital data of the sampling period Ts / 2 from which the high-frequency noise has been removed is output from the output terminal 26 via the output terminal 26 as shown in FIG. / A converter 7.

The data reproducing circuit 6 shown in FIG.
In this case, the M-bit digital data of the sampling period Ts / 2 from which the high-frequency noise has been removed by removing the frequency components equal to or higher than the cutoff frequency by the low-pass filter 24 can be used, for example, using an FIR digital filter or a switching circuit Decimation processing (decimation) is performed by the decimation section 25, which is a formed decimation filter, to obtain M-bit digital data with a sampling period Ts.
The signal is supplied to the D / A converter 7 shown in FIG.

The D / A converter 7 has a low-pass filter 24
From the digital data (or the digital data supplied through the low-pass filter 24 and the thinning unit 25) supplied from the
For example, the power is supplied to an external device such as a speaker device or a television receiver. As a result, a sound output and a video output without noise can be obtained.

(Effects of First Embodiment) As is clear from the above description, the information processing apparatus of the first embodiment forms digital data by digitizing an externally supplied analog signal. Then, predetermined lower bits of the digital data are truncated by a lower bit truncation circuit 4,
Based on the remaining high-order digital data, the data reproducing circuit forms digital data of the original number of bits including the truncated low-order bits, or digital data of a larger number of bits than the original number of bits. By outputting the analog signal, it is possible to obtain a high-quality analog signal from which noise components have been removed.

The resolution improving signal processor 23 supplies the MN bit digital data formed by the (MN) bit signal generator 33 directly to the adder 31 as shown in FIG. It is good also as a structure which performs. With this configuration, the offset value generation unit 34, the adder 35, the overflow detection unit 36, and the changeover switch 37 can be omitted, and the configuration of the resolution improving signal processing unit 23 can be simplified. Further, the delay time of the delay unit 30 can be reduced, and the data processing time in the resolution improving signal processing unit 23 can be reduced.

[Second Embodiment] The information processing apparatus according to the first embodiment determines the number of lower bits to be rounded down by the lower bit rounddown circuit 4 according to the amount of noise detected by the noise detection circuit 5. However, in the information processing apparatus according to the second embodiment, the lower bit of the number of bits designated by the user is truncated by the lower bit truncation circuit 4 for data processing. In addition,
The information processing apparatus according to the first embodiment is different from the information processing apparatus according to the second embodiment only in this point. Therefore, only the differences will be described below, and redundant description will be omitted.

(Configuration of Second Embodiment) That is, the information processing apparatus according to the second embodiment of the present invention has a configuration as shown in FIG. 28 instead of the noise detection circuit 5 as shown in FIG. Has an operation unit 50 for designating lower bits to be rounded down by the lower bit round-down circuit 4. The lower bit truncation circuit 4 includes a gate processing unit 51 to a coefficient generation unit 58. A signal specifying a truncation bit specified by a user operating the operation unit 50 is supplied to a threshold value generation unit 55 and a coefficient generation unit 55. The data is supplied to the data reproducing circuit 6 shown in FIG. The gate processing unit 51 has an input terminal 59
, N-bit digital data from the noise component removing circuit 3 shown in FIG. 27 is supplied.
In the gate processing section 51, a gate waveform G (t) formed by a gate waveform generation section 56 described later.
By multiplying by a coefficient (gain of 0 to 1) corresponding to
The lower bits specified by the user are discarded from the N-bit digital data and supplied to the data reproducing circuit 6 via the output terminal 60. The data reproducing circuit 6 forms a high-quality analog signal from which noise components have been removed in the same manner as in the first embodiment, based on the signal specifying the truncation bit supplied from the operation unit 50.

(Operation of the Second Embodiment) First, FIG.
, N-bit digital data from the noise component removal circuit 3 shown in FIG. 27 is supplied to the gate processing unit 51 via the input terminal 59, and the envelope extraction unit 5
2 is supplied. The envelope extraction unit 52 is configured as shown in FIG.
An envelope waveform of the N-bit digital data as shown in FIG. 3A is extracted, and the extracted envelope waveform is supplied to an open / close signal generator 53, a threshold value generator 55, and a coefficient generator 58.

The opening / closing signal generator 53 compares the threshold value held in the threshold value memory 54 with the magnitude of the envelope waveform extracted by the envelope extracting section 52, and based on the comparison result, FIG. An opening / closing instruction signal for issuing a gate opening / closing instruction as shown in (b) is formed, and this signal is generated by the gate waveform generator 56 and the coefficient generator 5
8 The opening / closing instruction signal includes a threshold value>
A gate close signal of “0” is output when the envelope waveform is used, and a gate open signal of “1” is output when the threshold value ≦ envelope waveform.

The gate opening / closing operation is performed when the envelope waveform rises and falls. In the case of the second embodiment, for example, the threshold value Tho for opening gate and the threshold value Thc for closing gate at the time of comparison in the open / close signal generator 53 are different values, and each value is the threshold value. It is held in the memory 54. The threshold values Tho and Thc stored in the threshold value memory 54 are updated by the threshold value generation unit 55 at the timing when the user operates the operation unit 59 to specify the lower bits to be discarded. I have.

The gate waveform generator 56 generates a gate waveform which rises in response to the gate open signal "1" and falls in response to the gate close signal "0" as shown in FIG. The rise characteristic and the fall characteristic of this gate waveform are determined by the rise coefficient Kup and the fall coefficient Kdn held in the coefficient memory 57. The coefficients Kup and Kdn of the coefficient memory 57 are updated by the coefficient generation unit 58 in accordance with the cut-off lower-order bits specified by the user via the operation unit 50 or in response to an open / close instruction signal from the open / close signal generator 53. It has become so.

The operation will be described in detail. For example, when digital data having no data component is supplied to the lower bit truncation circuit 4 (when only noise is supplied), the threshold value generation unit 55 The envelope extraction unit 52 supplies a noise envelope waveform. In this state, when the user operates the operation unit 50 to give an instruction to set a truncation bit, the threshold value generation unit 55 sets the threshold value generation unit 55 in the period in which the setting instruction is being issued (the period from the setting start instruction to the setting end instruction). A maximum value Nmax of a noise envelope amplitude value is detected, and a threshold value Th of an appropriate level exceeding the maximum value Nmax is detected.
o and Thc are calculated and stored in a threshold value memory 54.
Set to.

Thus, for example, when digital data having a data component as shown in FIG. 29A is supplied, the open / close signal generator 53 causes the rising edge of the digital data as shown in FIG. 29B. At the time when the amplitude level exceeds the open threshold value Tho, the open / close instruction signal is set to the open signal "1".
The output of "1" is continued until the amplitude level falls below the closing threshold value Thc, and when the amplitude level falls below the closing threshold value Thc, the closing signal is set to "0".

As described above, when the start of threshold value setting is instructed by the repetition section 50, a threshold value suitable for the amplitude level is newly obtained from the amplitude level of the noise waveform measured during the setting period. When the termination is instructed, the value held in the threshold value memory 54 is
Update with the newly obtained threshold value. As a result, the setting of the threshold value can be recognized as an appropriate value by a simple operation.

The gate waveform generator 56 is a switching signal generator 5
Upon receipt of the opening / closing instruction signal shown in FIG. 29 (b) from FIG. 3, a gate waveform as shown in FIG. 29 (c) having a smooth rise and fall is generated based on this opening / closing instruction signal. The rise and fall characteristics of this gate waveform are determined by the rise coefficient Kup and the fall coefficient Kdn held in the coefficient memory 57. The gate waveform is supplied to the gate processing unit 51, and the gate processing unit 51 performs a gate process of multiplying the N-bit digital data by the gate waveform to smoothly open and close the gate.

Next, the rise and fall characteristics of the gate waveform according to the digital data are adjusted as follows.
That is, before inputting digital data having a data component, the user operates the operation unit 50 to give a truncation bit setting instruction. Thus, when the digital data is supplied, the coefficient generation unit 58 calculates a rising coefficient Kup corresponding to the slope of the envelope waveform of the digital data near the open threshold value Tho at the rising portion, and similarly, the rising coefficient is calculated. The falling coefficient Kdn corresponding to the slope of the envelope waveform of the input signal near the closed threshold value Thc is calculated in the falling part, and the value held in the coefficient memory 57 is updated with these coefficients Kup and Kdn.

As described above, when the operation section 50 is operated to instruct the start of the setting of the truncation bit, the rising and falling characteristics of the gate waveform corresponding to the envelope waveform are determined from the envelope waveform extracted during the setting period. When a coefficient to be set is newly obtained and the setting end is instructed, the value held in the coefficient memory 57 is updated with the newly obtained coefficient. This makes it possible to appropriately set the gate waveform at the time of opening and closing the gate by a simple operation.

Next, when the characteristics of the digital data change, the rising and falling characteristics of the gate waveform are corrected in accordance with the changes as follows. Here, it is assumed that digital data having different characteristics are discretely input.
Each time digital data is input, an open / close signal generator 53 outputs an open / close instruction signal, which is supplied to a coefficient generator 58. Each time a new opening / closing instruction signal is input, the coefficient generator 8 calculates more appropriate rise coefficient Kup and fall coefficient Kdn based on the envelope waveform of the digital data at that time, and stores the coefficient memory in the coefficient memory using the calculated coefficients. 57
Update the coefficient stored in. This makes it possible to set the rising and falling characteristics of the gate waveform to be optimal in real time, following changes in the state of digital data.

Next, the detailed operation of the main circuit portion of the lower bit truncation circuit 4 will be described.

First, the gate waveform generator 56 has a functional block configuration shown in FIG. Switch 6
Reference numeral 1 denotes a switch for selecting a constant Ku or a constant “0”. The selected coefficient is input to one input terminal of the adder 63. The constant Ku connected to the one-side contact of the switch 61 is a constant that determines a predetermined rising characteristic, and the constant “0” connected to the zero-side contact is a constant that determines the falling characteristic. The target value is where the waveform converges.

The switch 62 is a switch for selecting the rise coefficient Kup or the fall coefficient Kdn of the coefficient memory 57. The switch 62 has the rise coefficient Kup at the one-side contact (the contact indicated by "1"), and The falling coefficient Kdn is input to the zero-side contact (the contact indicated as “0”). The selected coefficient is input to the multiplier 66 as a multiplication coefficient. The rise coefficient Kup and the fall coefficient Kdn
Is a condition such as Kup ≧ 1 1> Kdn ≧ 0.

The switching of these switches 61 and 62 is controlled by an open / close instruction signal from the open / close signal generator 3.
That is, when the open / close instruction signal is the open signal “1”, the switch is switched to the 1-side contact, and when the close signal is “0”, the switch is switched to the 0-side contact.

The addition result of the adder 63 is input to the limiter 64, and the output signal of the limiter 64 is output to the gate processing unit 51 as a gate waveform and is also supplied to the delay unit 65 which delays by one sample time. The limiter 64 limits the value of the addition result of the adder 63 to “1” when the value is larger than “1”, and outputs “0” when the value becomes equal to or less than a predetermined value. The output signal of the delay unit 65 is input to the other input terminal of the adder 63 after being multiplied by the coefficient by the multiplier 66.

In such a gate waveform generator 56, in the initial state, the open / close instruction signal from the open / close signal generator 53 is a close signal “0”, and the output gate waveform is “0”. When the open / close instruction signal becomes the open signal “1”, the switches 61 and 6
2 are connected to the 1-side contact, respectively, and perform the following calculation for each sampling period to generate a gate waveform G rising with a curve as shown in FIG.

G (t) = Ku + G (t−1) × Kup where G (t) is the value at the current sampling time, and G (t)
-1) means the value at the previous sampling time. In addition,
When the gate waveform G (t) as a result of this calculation becomes larger than "1", the gate waveform G (t) is limited to "1" by the limiter 64 and "1" is continuously output.

Next, when the opening / closing instruction signal from the opening / closing signal generator 53 becomes the closing signal “0”, the switches 61 and 62 are respectively connected to the 0-side contacts, and the following calculation is performed for each sampling cycle. A gate waveform falling with a curve as shown in FIG. 29 (c) is generated. This calculation is theoretically forever close to “0” and becomes an asymptote. Therefore, the limiter 64 is set to “0” when the value becomes a predetermined value or less.

G (t) = G (t-1) × Kdn It should be noted that digital processing is performed such that a value less than a predetermined value is automatically cut off to “0” due to the number of bits used in the operation. You may. In this case, the configuration can be simplified by eliminating the need for a limiter for setting to “0”.

Next, the threshold value generator 55 will be described. When the operator operates the threshold value setting operation element of the operation section 59, the threshold value generation section 55 operates during the operation period (or during a predetermined time after the operation).
The threshold value is formed from the digital data inputted to the threshold value memory 54 and set in the threshold value memory 54.

FIG. 31 shows the threshold value generator 55.
31. As shown in FIG. 31, the envelope waveform from the envelope extracting unit 52 is supplied to one input terminal of a comparator 71.
1 is output to the comparator 7 via the one-sample delay 72.
1 as well as being supplied to the maximum value register 73. An output signal from the maximum value register 73 is supplied to a multiplier 7 for multiplying by a coefficient Ko.
4. The signals are supplied to multipliers 75 for multiplying by the coefficient Kc, and the output signals of the multipliers 74 and 75 are supplied to the threshold value memory 54.

Next, the operation of the threshold value generator 54 will be described below. In the threshold value generation unit 54,
The process is started by a threshold value setting start instruction from the operation unit 50 to generate a threshold value, and when a setting repeat operation end instruction is received from the operation unit, the content of the threshold value memory 54 is updated with the generated threshold value. finish.

When a threshold value setting start instruction is received from the operation unit 50, first, the delay unit 72 which is delayed by one sample time is reset, and the envelope waveform output from the envelope extraction unit 52 and one sample before from the delay unit 72 are output. Are compared by the comparator 71 and the larger one is output. The process of comparing the output of the envelope extraction unit 52 with the signal of the delay unit 72 and selecting the larger one is continued until a setting end instruction is received from the operation unit 50, and this process ends with the setting end instruction. The comparator 7 when the setting end instruction is given
Since the output of 1 becomes the maximum value during the setting operation period,
The value is stored in the maximum value register 73 that holds the maximum value.

Note that both the start and end operations are performed by the operation unit 5
Although the setting is performed at 0, this may be performed by giving only a start instruction and automatically giving a setting end instruction after a predetermined time has elapsed.

The maximum value of the maximum value register 73 is multiplied by a coefficient Ko and a coefficient Kc by multipliers 74 and 75, respectively, so that an open threshold value Tho, (rising threshold value), and a closed threshold value Thc (falling threshold value) are obtained. Is calculated, and the threshold value memory 54 is updated with the calculated value.

The formulas for calculating the open threshold value and the closed threshold value are shown below. That is, the maximum value of the amplitude level of the envelope waveform is Nmax, and the open threshold value is Tmax.
Assuming that ho and the closed threshold value are Thc, an operation of Th = Nmax X Ko Thc = Nmax X Kc (1.0 ≦ Kc ≦ Ko) is performed, and the calculated value is stored in the threshold value memory 54.

Further, in order to obtain the timing to be used in the coefficient correction processing described later, a value Tho 'which is a predetermined multiple of the open threshold value Tho and a value Thc' which is a predetermined multiple of the close threshold value Thc are calculated and held. are doing.

For example, when the threshold value is increased by 6 dB with respect to the amplitude measurement value such as noise, the coefficient K
The values of c and Ko are 2.0. Further, different values may be used. The example of FIG. 29A shows a case where the falling threshold value is set lower. In addition,
The values of the coefficient Kc and the coefficient Ko may be appropriately set in advance by experiments, or may be arbitrarily set by the user himself / herself.

Next, the coefficient generator 58 will be described.
The coefficient generation unit 58 detects a rise coefficient Kup and a fall coefficient Kdn from an envelope state near a threshold value of digital data input during operation of the operation unit 50 (or during a predetermined time after operation). Set.

The coefficient generation unit 58 sets the coefficient when the coefficient is set by the truncation bit setting operation from the operation unit 50,
The function differs when the coefficient is corrected in real time thereafter. FIG. 32 shows a functional block of the coefficient generating unit 58 when the coefficient is set, and FIG. 33 shows a functional block of the coefficient generating unit 58 when the coefficient is corrected.

The coefficient generation unit 58 has the configuration shown in FIG. 32 in response to a cut-off bit setting start instruction from the operation unit 50 and starts the coefficient setting process. The rise and fall coefficients are updated to end the coefficient setting process.
After that, the coefficient correction process is performed.

First, the configuration of the coefficient generation unit 58 when setting the coefficients shown in FIG. 32 will be described. When the start of coefficient setting is instructed by the truncation bit setting operation of the operation unit 50, the coefficient generation unit 58 has the configuration shown in FIG. 32, and is in a state where the coefficient can be set. In FIG. 32, when an envelope waveform is input from an envelope extraction unit 52, this envelope waveform is input to a divider 82 as input data A and a delay unit 81 that delays by one sample.
And the output data of the delay unit 81 is
2 is input as input data B. Thereby, the envelope value E at the current sampling time is used as the input data A.
(T) is the input data B as the previous sampling time (t
The envelope value E (t-1) of -1) is input to the divider 82.

The divider 82 performs an operation of A ÷ B on the input data A and B, and outputs the operation result as a ratio R (t) (hereinafter, referred to as an envelope value) between the current sampling time and the previous sampling time. , A change ratio).

R (t) = E (t) / E (t-1) The change ratio R (t) output from the divider 82 is input to shift registers 83 and 84, respectively. The shift register 83 has the number of stages (the number of samplings) corresponding to the time difference from to to 'in FIG. 29A, and the shift register 84 has the number of stages corresponding to the time difference from tc' to tc in FIG. Have.

The signals output from each stage of the shift register 83 are added by an adder 85, multiplied by a coefficient Ku by a multiplier 87, and held in a register 91 as a rising coefficient Ro. On the other hand, the signals output from the respective stages of the shift register 84 are added by an adder 86, multiplied by a coefficient Kd by a multiplier 88, and held in a register 92 as a falling coefficient Rc.

The operation performed by these circuits is an operation for averaging a predetermined number of change ratios R (t) to obtain a rising coefficient Ro and a falling coefficient Rc as shown in the following equation. Where to and tc are the times of the rising and falling portions of the opening / closing instruction signal obtained by the preset threshold value, to 'is the time after a predetermined time after to, and tc' is tc This is the time after the previous predetermined time, and the constant Ku is Ku = 1 / (to'-to
+1), and (to'-to + 1) is from to 'to t
The sampling number and the constant Kd up to o are given by Kd = 1 / (t
c−tc ′ + 1), where (tc−tc ′ + 1) is
The sampling number is from tc to tc '. The holding of the coefficients in the registers 91 and 92 is performed by generating the timings of to ′ and tc by the timing generation unit 89.

Ro = ｛R (to) + R (to + 1) + ·
R (to ') @ xKu Rc = @ R (tc') + R (tc '+ 1) + .. R (t
c)｝ xKd In the coefficient generating unit 58 having such a configuration, when an envelope waveform of digital data having a data component as shown in FIG.
The rising coefficient Ro is calculated from the change ratio of the portion of the envelope waveform near the threshold value Tho (section from time to to to '), and the portion near the threshold value Thc (time t).
The falling coefficient Rc is obtained from the change ratio of the section (c ′ to tc). The rising coefficient Ro is held in the register 91 and the falling coefficient Rc is held in the register 92, respectively. And
When the end of the coefficient setting is instructed by the truncation bit setting operation of the operation unit 50, the coefficient Ro held in the register 91 is set as the rising coefficient Kup, and the coefficient Rc held in the register 92 is set as the falling coefficient Kdn. Set in the coefficient memory 57.

Instead of giving an end instruction in the working unit 50, the operation unit 50 gives only a start instruction for coefficient setting.
The coefficient memory 57 may be updated after a lapse of a predetermined time or when new coefficient data is obtained, and the operation may be terminated.

In the above description, since the change of the change ratio R (t) at the rising and falling portions of the envelope waveform is large, the average is calculated using the shift register, the adder, and the multiplier. If the change in the calculated change ratio is not so large, or if the large change is removed in the process of the divider, the result of the divider 82 (A８２B) is calculated without calculating the average. Multiplied by a predetermined coefficient,
Rise coefficient and fall coefficient can also be used.

Next, the coefficient generator 58 at the time of coefficient correction shown in FIG. 33 will be described. After the end of the coefficient setting is instructed by the operation unit 50, the rise coefficient Kup and the fall coefficient Kdn set in the previous coefficient setting processing are corrected according to the envelope of the newly input signal, and the gate waveform generator 56 Then, a gate waveform having rising and falling characteristics corresponding to the corrected rising coefficient Kup and falling coefficient Kdn is generated, and the gate processing unit 51 is controlled.

First, the basic concept of the coefficient correction will be described. When the input signal is gated, the rising edge of the gate waveform should be as steep as possible in order to prevent the rising portion of the envelope waveform from being lost, but the gate waveform is too steep although the rising edge of the gated input signal is gentle. When the information processing apparatus is applied to, for example, an electronic musical instrument or the like, a sudden change in volume at the rising edge is felt, which gives an unnatural feeling. Therefore, the rise coefficient Kup is set to a value most suitable for the rise of the input signal at that time when the coefficient is set. However, when an input signal having a steeper rise is input, the input signal becomes steeper. , The rise coefficient is sequentially corrected. On the other hand, as for the falling coefficient Kdn, the falling coefficient Kdn is successively modified so as to conform to the falling characteristic of the currently input signal.

When the end of the coefficient setting is instructed, the coefficient generator 58 has the configuration shown in FIG. In this configuration, a process is performed in which the opening / closing instruction signal from the opening / closing signal generator 53 operates in the section of the open signal “1” to correct the coefficient. That is, when a significant input signal is input, each timing signal t is generated by the timing generation unit 114 based on the open / close instruction signal generated by the open / close signal generator 53 in accordance with the input signal.
o, tc ', and to-tc are generated. Timing signal t
o-tc corresponds to the opening / closing instruction signal shown in FIG. 29B, and during the period of the open signal “1”, the coefficient generation unit 8 having this configuration is used.
Performs processing.

The delay unit 101 and the divider 102 are the same as those described above.
The change ratio R (t) of the envelope waveform from 2 is calculated,
The change ratio R (t) is input to one input terminal of the comparator 104 and is input to one input terminal of the adder 109.

The timing signal to generated by the timing generation section 114 is a signal which becomes "1" only at the rising edge of the open / close instruction signal shown in FIG.
03 is input as a control signal. As a result, the switch 103 operates at the rising edge of the open / close
7 is supplied to the other input terminal of the comparator 104, and the switching signal is controlled to supply the output signal of the one-sample delay unit 105 to the other input terminal after the rising portion.

The comparator 104 compares the amplitude levels of the input signals, selects the higher one, and selects the output signal Ro.
(T) '. This comparator 104
Supplies the output signal Ro (t) ′ to the limiter 106 and also to the delay unit 105. The limiter 816 limits the minimum value of the input signal Ro 'according to the following equation and outputs the resultant signal.

Ro (t) = Max [Ro (t) ′, Rmin] (where Rmin is the minimum value of a preset rise coefficient) This expression indicates that the input signal Ro (t) ′ is smaller than the minimum value Rmin. If it is larger, it means that the signal is passed as it is, and if it is less than the minimum value Rmin, it means that the minimum value Rmin is output instead of the input signal Ro (t) '. The reason why such a limit process is performed is that it is not necessary to make the rise of the gate waveform very slow.

On the other hand, the timing signal tc 'of the timing generator 114 is a signal which becomes "1" only at the time tc' (see FIG. 29A) which is a predetermined time before the fall of the opening / closing instruction signal, and 115 is input as a control signal. As a result, the switch 115 sets the register 1
13, the falling coefficient Kdn is set to the inverter 108.
The signal is supplied to the other input terminal of the adder 109 and to one input terminal of the adder 109, and is switched to supply the output signal of the one-sample delay unit 112 during the subsequent period. The output signal of the adder 109 is input to the other input terminal of the adder 111 via the multiplier 110 for multiplying the coefficient C, and the output signal of the adder 111 is input to the delay unit 112.

Therefore, the lower adder 109, coefficient multiplier 110, adder 111, delay unit 112, and inverter 10
8. The configuration of the switch 115 is based on the falling coefficient R held in the register 113 from the time of the timing signal tc '.
A value obtained by performing the following operation with c as an initial value is supplied to the coefficient memory 57 as a falling coefficient Kdn.

Rc (t) = CX ｛R (t) −Rc (t−
1)｝ + Rc (t−1) (where c is 0 ≦ c ≦ 1) Next, the operation of the coefficient generation unit 58 at the time of coefficient correction will be described. When the open / close instruction signal generated by the open / close signal generator 53 becomes the open signal “1”, the comparator 104, the delay unit 105,
In the configuration including the switch 103, the comparator 104 compares the sequentially input R (t) with the value of the delay unit 105 using the rising coefficient Ro held in the register 107 as an initial value, and An operation of selecting and outputting an input signal is performed. As a result, the maximum value is held in the delay device 105. The output value Ro of the comparator 104
(T) ′ is sequentially stored in the coefficient memory 57 via the limiter 106 as the rising coefficient Kup. This allows
The rise coefficient Kup changes with time, and the rise coefficient Kup set by the above-described coefficient setting operation is sequentially corrected.

On the other hand, the lower adder 109 and the coefficient multiplier 1
10, the adder 111, the delay unit 112, the inverter 108, and the switch 115, the following operation described above is performed using the falling coefficient Rc held in the register 113 from the time of the timing signal tc 'as an initial value. I do.

Rc (t) = CX ｛R (t) −Rc (t−
1)｝ + Rc (t-1) The processing by this arithmetic expression is to calculate the falling coefficient Rc (t) by:
From the value of the initial value Rc (t-1) held in the register 113, the value R sequentially input as time passes.
(T), and when the coefficient C is “0”, the falling coefficient Re (t) is held unchanged without changing the initial value Rc (t−1), and the coefficient C becomes “1”. Means that the falling coefficient Rc (t) is immediately replaced by the input value R (t), and the falling coefficient Rc (t) increases as the coefficient C approaches "1". The time to approach R (t) is reduced.

When the open / close instruction signal falls from the open signal "1" to the close signal "0", the processing of the coefficient generating section 58 is completed, and the gate waveform is obtained according to the falling coefficient Kdn of the coefficient memory 57 stored at that time. Falls.

The gate processing section 51 shown in FIG. 28 multiplies the gate waveform G (t) thus formed by a coefficient (gain of 0 to 1) corresponding to the lower bit designated by the user. From the N-bit digital data, and supplies this to the data reproducing circuit 6 via the output terminal 60. The data reproducing circuit 6 is configured to output the data based on the signal specifying the truncation bit supplied from the operation unit 50.
As in the first embodiment, a high-quality analog signal from which noise components have been removed is formed. Thus, the same effect as the information processing apparatus according to the first embodiment can be obtained in the information processing apparatus according to the second embodiment.

Finally, the present invention is not limited to the above-described embodiment which has been described as an example, and various changes may be made according to the design and the like within a range not departing from the technical idea of the present invention. Of course, it is possible.

[0141]

According to the information processing apparatus according to the first aspect of the present invention and the information processing method according to the fifth aspect of the present invention, it is possible to obtain high-quality analog information from which noise components have been removed.

In the information processing apparatus according to the present invention, the number of bits to be discarded is changed according to the noise level detected by the noise detecting means. Noise removal processing can be performed.

In the information processing apparatus according to the third aspect of the present invention, the lower bits designated by the truncation bit designating means are truncated, so that the user can obtain analog information having desired characteristics. It can be.

In the information processing apparatus according to the present invention, the noise component superimposed on the digital information from the analog / digital conversion means is largely removed in advance by the noise component removal means. Can be easily processed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a noise component removing circuit provided in the information processing apparatus according to the first embodiment.

FIG. 3 is a diagram for explaining an operation of a calculation unit provided in the noise component removal circuit.

FIG. 4 is a block diagram of the calculation unit.

FIG. 5 is a diagram showing an output waveform of the arithmetic unit.

FIG. 6 is a block diagram of a data reproducing circuit provided in the information processing apparatus according to the first embodiment.

FIG. 7 is a block diagram of a repeated data generator provided in the data reproducing circuit.

FIG. 8 is a diagram for explaining the operation of the repetitive data generation unit.

FIG. 9 is a diagram used to explain a difference between a case where the repetitive data generation unit is not used and a case where the unit is used.

FIG. 10 is a block diagram of a resolution improving signal processing unit provided in the data reproducing circuit.

FIG. 11 is a block diagram showing another configuration of the resolution improving signal processing unit.

FIG. 12 is a waveform chart used to explain matters related to the manner of change in the digital value of N-bit code information.

FIG. 13 shows N-bit code information (digital data);
FIG. 3 is a diagram for explaining a relationship with an original analog signal.

FIG. 14 is a block diagram of a change pattern determining unit provided in the resolution improving signal processing unit.

FIG. 15 is a diagram exemplifying a relationship between a change mode of digital values of four continuous change points on a time axis and a mode of linear interpolation to be performed according to the change mode of the digital value.

FIG. 16 is a diagram exemplifying a relationship between a change mode of digital values of four continuous change points on a time axis and a mode of linear interpolation to be performed according to the change mode of the digital value;

FIG. 17 is a diagram exemplifying a relation between a change mode of digital values of four continuous change points on a time axis and a mode of linear interpolation to be performed according to the change mode of the digital value;

FIG. 18 is a diagram exemplifying a relationship between a change mode of digital values of four continuous change points on a time axis and a linear interpolation mode to be performed according to the change mode of the digital value.

FIG. 19 is a diagram illustrating an example of a relationship between a change mode of digital values of four continuous change points on a time axis and a mode of linear interpolation to be performed according to the change mode of the digital value.

FIG. 20 is a diagram exemplifying a relationship between a change mode of digital values of four continuous change points on a time axis and a mode of linear interpolation to be performed in accordance with the change mode of the digital value;

FIG. 21 is a diagram exemplifying a relationship between a change mode of digital values of four continuous change points on a time axis and a mode of linear interpolation to be performed in accordance with the change mode of the digital value.

FIG. 22 is a diagram illustrating an example of a relationship between digital value change modes at four continuous change points on a time axis and a linear interpolation mode to be performed according to the digital value change mode;

FIG. 23 is a graph showing the relationship between the second digital value change point and the third digital value change point in a set of four digital value change points sequentially appearing on the time axis; FIG. 7 is a diagram for explaining how an interpolation straight line to be applied to a section is determined.

FIG. 24 is a diagram for explaining an interpolation state in which linear interpolation is changed to curve interpolation;

FIG. 25 is a diagram used to describe the state of digital data obtained by a conventional information processing device.

FIG. 26 is a diagram used to explain the state of digital data obtained by the resolution improving signal processing unit.

FIG. 27 is a block diagram illustrating an information processing apparatus according to a second embodiment of this invention.

FIG. 28 is a block diagram of an operation unit and a lower bit truncation circuit provided in the information processing apparatus according to the second embodiment.

FIG. 29 is a diagram showing a data waveform of each part of the lower bit truncation circuit.

FIG. 30 is a functional block diagram of a gate waveform generator 56 provided in the lower bit truncation circuit.

FIG. 31 is a functional block diagram of a threshold value generation unit 55 provided in the lower bit truncation circuit.

FIG. 32 is a functional block diagram of a coefficient generation unit 58 provided in the lower bit truncation circuit when setting a coefficient.

FIG. 33 is a functional block diagram of a coefficient generation unit 58 provided in the lower bit truncation circuit at the time of coefficient correction.

[Explanation of symbols]

1 ... input terminal for analog signal, 2 ... A / D converter, 3 ...
Noise component removal circuit, 4 ... lower bit truncation circuit, 5
... Noise detection circuit, 6 ... Data reproduction circuit, 7 ... D / A converter, 8 ... Output terminal of analog signal, 9 ... Sampling rate variable section, 50 ... Operation section

Claims (5)

[Claims] 1. An analog / digital converter for converting analog information into digital information, a lower bit truncation unit for truncating and outputting a predetermined lower bit of digital information from the analog / digital converter, and the lower bit truncation. Reproducing the digital information of the original number of bits including the truncated lower bits, or the digital information of the larger number of bits than the digital information of the original bit number, based on the digital information whose lower bits are truncated from the means; An information processing apparatus comprising: an information reproducing unit; and a digital / analog converting unit that converts digital information reproduced by the information reproducing unit into analog information and outputs the analog information. 2. The apparatus according to claim 1, further comprising a noise detection unit configured to detect a level of a noise component superimposed on the digital information from the analog / digital conversion unit, wherein the low-order bit truncation unit detects the noise component detected by the noise detection unit. 2. The information processing apparatus according to claim 1, wherein the number of lower bits to be discarded is changed and controlled according to the level of the noise component. 3. The system according to claim 1, further comprising: a truncation bit designating unit for designating the number of lower bits to be truncated by the lower bit truncation unit; 2. The information processing apparatus according to claim 1, wherein bits are truncated from digital information from the analog / digital converter and output. 4. The apparatus according to claim 1, further comprising a noise component removing unit that removes a noise component superimposed on the digital information from the analog / digital converting unit and outputs the noise component. The information processing apparatus according to claim 1. 5. A step of converting analog information into digital information, a step of discarding predetermined lower bits of the digital information formed in the step, and a step of: Reproducing digital information of the original number of bits including the truncated lower bits, or digital information of a larger number of bits than the digital information of the original number of bits; converting the digital information reproduced in the step to analog information And outputting the information.