JPH0632018B2 - Pitch converter - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention, when the tape recorder rotates fast and slow, returns the pitch to restore the timbre change, or changes the pitch of the music signal to change the pitch. The present invention relates to a pitch conversion device used when performing pitch matching with a musical instrument or voice.

[Technical Background of the Invention and Problems Thereof] As a method of changing the pitch of an acoustic signal, a method of reproducing an acoustic signal recorded on a tape recorder or the like at a speed different from that at the time of recording is known.

However, this method cannot change the pitch of the sound in real time because the time length changes and the tempo also changes.

For this reason, recently, a pitch conversion device which uses a memory element and is capable of performing pitch conversion in real time has been developed.

FIG. 1 is a circuit block diagram of such a conventional pitch conversion device.

The pitch conversion device includes an A / D converter 1 for converting an analog signal as an input signal into a digital signal, a memory 2 for storing data, an address switcher 3 for switching an address of the memory 2, and an address switcher 3. Write address counter 4 for sending a write address to and a read address counter 5 for instructing a read address to the address switcher 3.
And a memory controller 6 for switching addresses, switching between write mode and read mode, and supplying clocks to the A / D converter 1 and the write address counter 4
A write clock generator 7 for supplying a write request to the memory and a memory controller 6 for supplying a clock to the read address counter 5.
A read clock generator 8 for supplying a read request to the block, a block counter 9 for resetting the read address counter 5 when the write address counter 4 counts a fixed block length, a data latch 10 for latching read data, and a data It comprises a D / A converter 11 for converting the read data supplied from the latch 10 into an analog signal.

In such a conventional pitch converter, the input signal is A /
It is converted into a digital signal by the D converter 1 and written in the memory 2. At this time, the sample clock is supplied from the write clock generator 7 to the A / D converter 1, the clock is supplied to the write address counter 4, and the address switching unit 3 addresses according to the address signal of the write address counter 4. Switch.

Reading from the memory 2 is performed at a frequency different from the write clock, and the read data is once latched by the data latch 10 and then returned to an analog signal through the D / A converter 11 and output.

When reading data, a clock is supplied from the read clock generator 8 to the read address counter 5, and a latch pulse is supplied to the data latch 10. The read address counter 5 is reset by the block counter 9 for each fixed block length preset.

The switching control of writing and reading to and from the memory 2 is performed by writing requests from the writing clock generator 7 and the reading clock generator 8 and switching of addresses by the memory controller 6 that has received the reading request, writing mode, and reading mode. Is performed by switching.

2 and 3 are timing charts for explaining the operation of this pitch conversion device.

FIG. 2 shows the case where the frequency of the read clock is lower than the write clock, that is, the case where the pitch is lowered, and FIG. 3 shows the case where the frequency of the read clock is higher than the write clock, that is, the case where the pitch is raised. ing.

In these figures, (a) shows an input data string and (b) shows an output data string.

Here, a block length of several 100 ms is required for the sense of hearing, and an input signal having a period longer than the block length is not pitch-converted. From this point, the longer the block length, the better.

However, if the block length is long, the memory capacity of the memory 2 increases, and the length of the lost data that is lost when the predetermined pitch conversion is performed becomes long, so that the aurally perceived lost sound is recognized. Therefore, the block length is usually about several hundred ms.

When lowering the pitch using this pitch converter,
As shown in FIG. ₂ , data of D ₁ + D ₂ is written in the memory at the frequency of the write clock. On the other hand, when this data is read, the frequency of the read clock becomes lower than the frequency of the write clock, so the data output by the end of the block is the portion (D ₁ ) and the portion (D ₂ ). The data cannot be read because the read address counter is reset every fixed block length.

That is, the data D _{2 of} this portion is lost for each block. Therefore, in this case, the pitch is reduced as in the case where the tape recorder is delayed, and the read data catches up with the write data in each block, so that the entire time is not extended and the pitch conversion is performed in real time. Done.

On the contrary, when the pitch shown in FIG. 3 is increased, the frequency of the read clock is increased, so that the read address is reset in the middle of the block. That is, the reading is performed from the D ₃ portion of the previous data, and the (D ₃ ) and (D ₄ ) portions are read by the time of resetting in the next block. That is, the portion (D ₃ ) is read redundantly before and after the reset. Therefore, the pitch rises and conversion is performed in real time in the same manner as the fast rotation of the tape recorder in the block.

By the way, in such a conventional pitch conversion device,
As shown in the figure, a discontinuous portion X is generated in the audio signal S at the data joint.

That is, since the read address counter 5 is reset regardless of the contents of the signal, the continuity of the signal is rarely obtained stochastically, so that this discontinuous portion X occurs in the cycle of the block. There are drawbacks that the contents are very annoying, making it difficult to hear the contents, and often giving an acoustic discomfort.

[Object of the Invention] The present invention has been made in order to eliminate such a conventional drawback, and provides a pitch conversion device which eliminates noise caused by discontinuity of sound in each block and obtains a natural sound. To aim.

[Outline of the Invention] That is, as shown in FIG. 5, the pitch conversion device of the present invention includes a conversion means (A) for converting an analog signal into digital signal data and a storage means (B) for storing the data. Writing means (C) for writing the data obtained by the converting means (A) into the storage means (B) at a predetermined frequency, and writing the data stored in the storage means (B) at a frequency different from the writing frequency. Two read means (D) (D) for reading in parallel while alternately resetting the read addresses for each fixed block length, and the read means provided corresponding to these read means (D) (D), respectively. (D) (D)
Two data holding means (E) (E) for holding the data read by the above, and these two data holding means (E)
The switching means (F) for alternately switching the data held in (E) and joining them into one data, and the potential level as an analog value of each data held in each data holding means (E) (E). When the detecting means (G) for detecting and after resetting the read address, the detecting means (G) detects that the potential level of one data not selected by the switching means (F) has reached a predetermined value. , When the data reading of the reading means (D) corresponding to one of the data holding means (E) holding the data is stopped and then it is detected that the potential level of the other data reaches a predetermined value, And a control means (H) for switching the switching means (F) and for restarting the data reading by the stopped reading means (D).

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 is a circuit block diagram of an embodiment of the present invention. In FIG. 6, the same parts as those in FIG. 1 are designated by the same reference numerals.

The pitch conversion apparatus of this embodiment includes an A / D converter 1 for converting an analog signal which is an input signal into a digital signal,
A memory 2 for storing data, an address switch 3 for switching the address of the memory 2, a write address counter 4 for sending a write address to the address switch 3, and a read address counter for instructing the read address to the address switch 3. 5a and 5b, clocks are supplied to the memory controller 6 for switching addresses, switching between the write mode and the read mode, the A / D converter 1 and the write address counter 4, and write requests are sent to the memory controller 6. A write clock generator 7 for supplying and a read clock generator 8 for supplying clocks to the read address counters 5a and 5b and supplying read requests A and B to the memory controller 6 and a write address counter 4 for writing. When the difference between the address and the read address does not exceed the capacity of the memory, the read address is counted when counting a predetermined block length. A block counter 9 for resetting the response counter 5, data latches 10a, 10b for latching read data, and a D / A converter 11 for converting the read data supplied from the data latch into an analog signal are provided. The structure is similar to that of the conventional pitch converter shown in FIG.

Therefore, the pitch conversion apparatus of this embodiment is provided with two systems of the read address counter and the data latch, as indicated by reference numerals 5a, 5b, 10a and 10b in the figure.
In addition, the data latches 10a, 10
Data switch 12 for selecting and outputting any one of b
In response to the A / B switching request from the block counter 9, a point where the data read by the two reading means coincide is detected, and the data is switched to the data switching unit 12 at the timing of the clock of the read clock generator 8. And a level discriminator 13 for transmitting a switching signal.

Next, the operation of each part of this embodiment will be described.

In this pitch converter, the analog input signal is A / D
It is converted into digital data by the converter 1, and the memory 2
To be remembered.

The read data from the memory 2 has A and B systems, and the read data are once latched in the data latches 10a and 10b, respectively. The data of the A and B2 systems are supplied to the level discriminator 13, one of them is selected by the data switcher 12, and the D / A converter 11 converts the data into an analog signal for output.

The write clock generator 7 supplies a sample clock to the A / D converter 1, a clock to the write address counter 4, and a write request signal to the memory controller 6.

The read clock generator 8 includes a read address counter 5a,
The clock is supplied to 5b, and the data latches 10a and 10b are supplied.
Latch pulses A and B are supplied to the memory, a clock is supplied to the level discriminator 13, and read requests A and B are supplied to the memory controller 6.

The memory controller 6 receives the write request and the read requests A and B, supplies an address switch signal to the address switch 3 at a timing, and selects the write mode and read mode for the memory 2. R / W signal for

The address switch 3 receives the address switch signal, selects either the write address signal or the read address signal A or B, and supplies it to the memory 2 as address data.

The level discriminator 13 detects a point where the data read by the two reading means coincide with each other within a preset range and supplies an AB switching signal to the data switcher 12.

The block counter 9 receives the signal from the write address counter 4 and supplies resets A and B to the read address counters 5a and 5b for each fixed block length.

Next, the configuration and operation of the level discriminator 13 will be described.

FIG. 7 is a circuit diagram of the level discriminator 13, and FIG. 8 is a timing chart showing its operation.

The level discriminator 13 may determine whether or not the levels match, by matching or mismatching all the bits of the data, but normally, in order to increase the matching frequency, it is determined by matching or mismatching the upper digits.

The level discriminator 13 of this embodiment is provided with an AB coincidence circuit 13
a and a flip-flop circuit 13b.

A logical product of the coincidence detection signal of the coincidence detection circuit and the inverted signal of the A / B switching request is added to the R terminal of the flip-flop circuit 13b, and the coincidence detection signal of the coincidence detection circuit and A / B switching are applied to the S terminal. The AND of the requests is added.

In the level discriminator 13, when the A / B switching request is "0" level, the A / B switching signal is not output even if the coincidence detection signal of the coincidence detection circuit becomes "1" level.

Only when the A, B switching request is at "1" level and the match detection signal of the match detection circuit becomes "1" level, A, B
The switching signal is output at "1" level.

When the match detection signal of the match detection circuit when the A / B switching request is “0” level becomes “1” level, the A / B switching signal becomes “0” level.

Next, the operation of this embodiment will be described with reference to FIGS. 9 to 12.

The input signal is sampled at a constant cycle, converted into a digital signal by the A / D converter 1, and then sequentially written in the memory 2 according to the write address counter 4.

In response to the write request and the read request A and B, the memory controller 6 controls the memory recording mode, the read mode switching, and the address data switching so as not to overlap in time.

Reading from the memory 2 is performed at a frequency different from the writing frequency by the two read address counters 5a and 5b.
This is performed for each of the systems A and B, and is performed while alternately resetting the read address for each fixed block length.

FIG. 9 (a) shows an input signal sequence,
(B ₁ ) and (b ₂ ) show two output signal sequences when the read cycle is longer than the write cycle. The two read address counters 5a and 5b are alternately reset for each fixed block length (indicated by ▲ in FIG. 9).
If the read systems of (b ₁ ) and (b ₂ ) are switched and read at a constant cycle as shown in (c), the signal becomes exactly the same as that of the conventional example, and the signal discontinuity shown in FIG. 4 occurs. .

Further, when the read systems of (b ₁ ) and (b ₂ ) are switched and output, if switching is performed at the time when the signal levels of the two match, a signal having a different length between the switching times as shown in (d). A series is obtained.

The timing of this switching is determined as follows.

As shown in FIG. 10, when the signals of (a) and (b) are joined together, there is little discomfort and it sounds natural.
Indicate by dots. It is the time when the signal levels match. This level can be set arbitrarily, but if the set level is too high or too low, it will take time until the signal levels of (a) and (b) match, and it is necessary to increase the memory capacity. 0V which has the highest frequency of occurrence
It is desirable to use the electric potential as the reference level. The signal connected at such points can be heard as a natural voice without the discontinuity of the signal level as shown in FIG.

The level discriminator 13 in this embodiment is thus 2
In order to connect the seed signals at the points where the levels match, the output data is switched when the signal level becomes 0 V for the first time after the read address of one of the address counters 5a and 5b is reset.

FIG. 11 is a block diagram showing the main part of another embodiment of the present invention.

The pitch conversion apparatus of this embodiment includes level detectors 14a and 14b for detecting that the signal level of the data of each system has reached a preset level, instead of the level discriminator 13 of the above-described embodiment. , A / B switching request from the block counter 9 and level detectors 14a, 1
The embodiment shown in FIG. 6 except that it is provided with a level controller 16 which receives the level detection signal from 4b and supplies a gate signal to the gates 15a and 15b at the timing of the clock of the read clock generator 8. It has the same configuration as the example.

Next, the operation of this embodiment will be described with reference to FIG.

In this embodiment, in order to connect the two kinds of data, A and B, at the point where the potential levels corresponding to the analog values coincide with each other, one of the data has a potential level at a preset level, for example, 0V. Hold at and shift in time.

12A and 12B are signals in the data A series and the data B series in the circuit block diagram of FIG. 11, respectively.

Assuming that the signal is a sine wave for simplicity, the level detector 14a of the series of the data A has the potential level of the data A set to the set level (zero V in this embodiment) only at the time of X, that is, after the read address is reset. ) Is detected. Upon receiving the detection signal of this level, the level controller 1
6 inputs the gate signal as shown in FIG. Then, the supply of the clock A to the read address counter 5a is stopped [Fig. 12 (i)], and the read address counter 5a is stopped. Therefore, the read signal is maintained at a constant value [Fig. 12a].

After that, when the level detector 14b detects that the potential level of the data B has reached the set level at the time of Y, the gate signal A returns to the original [FIG. 12 (g)],
The read address counter A starts operating again [Fig. 12 (i)]. Therefore, at the time of Y, the signals of the A series and the B series are in a state where the potential levels are matched with each other. At the time of Y, a data switching signal is given [Fig. 12 (l)],
The output analog data is switched at the same potential level point [Fig. 12 (n)].

The level detection is performed for the data string of the system that is not currently output as shown in FIGS. 12 (e) and 12 (f). When it is detected that the detection level has reached the set level, the address counters 5a and 5b of the currently non-outputting series are stopped, and then the level detection is performed for the currently outputting data string. To start.

By repeating the above operation, a continuous signal sequence as shown in FIG. 12 (n) can be obtained, and noise or abnormal sound due to discontinuity at the joint of signals can be eliminated.

In the above embodiments, the case where the read cycle is longer than the write cycle has been described, but the same applies when the read cycle is shorter than the write cycle, whereby the pitch can be increased without causing signal discontinuity. .

It should be noted that in the above embodiment, an example in which a digital memory is used as the memory 2 has been described, but the present invention should not be limited to this embodiment, and a BBD, CCD
It is also possible to use an analog memory like device. In this case, the A / D converter and the D / A converter can be omitted.

[Effects of the Invention] As described above, according to the present invention, when performing pitch conversion of an acoustic signal in real time, it is possible to remove noise and unpleasant sound due to discontinuity of sound and perform pitch conversion of natural sound. .

Further, since the pitch conversion device of the present invention can be realized by a digital logic circuit, it can be easily integrated into an integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a conventional pitch conversion device, and FIG.
FIGS. 5 and 6 are timing charts for explaining the operation of the conventional pitch converter, FIG. 4 is a diagram showing a discontinuous portion of a voice signal generated when pitch conversion is performed by the conventional pitch converter, and FIG. FIG. 7 is a block diagram schematically showing the configuration of the pitch conversion device of the present invention, FIG. 6 is a circuit block diagram of an embodiment of the present invention, FIG. 7 is a circuit diagram of a level detector, and FIG. Timing chart showing the operation,
FIG. 9 is a timing chart showing the state of blocks when switching between A and B systems, FIG. 10 is a diagram showing a state in which signals are continuous according to the present invention, and FIG. 11 is a main part of another embodiment of the present invention. The block diagram shown in FIG. 12, and FIG. 12 are timing charts for explaining the operation of this embodiment. 1 ... A / D converter 2 ... Memory 3 ... Address switcher 4 ... Write address counter 5, 5a, 5b ... Read address counter 6 ... Memory controller 7 ... Write clock generator 8 ... Read clock generator 9 ... Block counter 10, 10a, 10b ... Data latch 11 ... D / A converter 12 ... Data switcher 13 ... Data discriminator 14a, 14b ... Level detector 16 ... … Level controller

Claims (1)

[Claims] 1. A conversion means for converting an analog signal into digital signal data, a storage means for storing the data, and a writing means for writing the data obtained by the conversion means in the storage means at a predetermined frequency. , Two read means for reading the data stored in the storage means in parallel at a frequency different from the write frequency while alternately resetting the read addresses for each fixed block length, and respectively corresponding to these read means. Two data holding means which are provided and hold the data read by the corresponding reading means, and a switching means which alternately switches the data held in these two data holding means to join them into one data, Detection means for detecting a potential level as an analog value of each data held in each data holding means; After the reset of, by the detection means,
When it is detected by the switching means that the potential level of one data not selected has reached a predetermined value, the data reading of the reading means corresponding to the one data holding means holding the data is stopped. , Then, when it is detected that the potential level of the other data reaches the specified value,
And a control unit for switching the switching unit and restarting the data reading by the stopped reading unit.