JPS60150865U

JPS60150865U - Frequency and frequency deviation adjustment circuit

Info

Publication number: JPS60150865U
Application number: JP3913984U
Authority: JP
Inventors: 雄一市川
Original assignee: 三洋電機株式会社
Priority date: 1984-03-19
Filing date: 1984-03-19
Publication date: 1985-10-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案の周波数及び周波数偏移調整回路を用い
た磁気録画再生装置の記録系を示す略ブロック図、第２
図は本考案の周波数及び周波数偏移調整回路を示す回路
図である。４・・・エンファシス回路、ｌ・・・周波数及び周波数
偏移調整回路、６・・−ＦＭ変調回路、１１・・・電源
ライン、１２・・・第１のトランジスタ、１３・・・定
電流源、１４・・・第１の可変抵抗器、１５・・・第２
の可変抵抗器、１６・・・第２のトランジスタ、１８・
・・第３のトランジスタ、１９・・・第４のトランジス
タ。FIG. 1 is a schematic block diagram showing a recording system of a magnetic recording and reproducing apparatus using the frequency and frequency shift adjustment circuit of the present invention, and FIG.
The figure is a circuit diagram showing the frequency and frequency shift adjustment circuit of the present invention. 4... Emphasis circuit, l... Frequency and frequency deviation adjustment circuit, 6... -FM modulation circuit, 11... Power supply line, 12... First transistor, 13... Constant current source , 14...first variable resistor, 15...second
variable resistor, 16... second transistor, 18...
...Third transistor, 19...Fourth transistor.

Claims

[Scope of utility model registration request]

In a recording system of a magnetic recording/reproducing device, a first adjusting means for adjusting a frequency shift of a first means for FM modulating a luminance signal extracted from a video signal; a transistor, a constant current source, and a second adjusting means for adjusting the sync chip carrier frequency of the first means, and a base of the first transistor,
A second component that secures the S/N ratio in the high frequency range of the luminance signal.
The collector of the first transistor and one end of the second adjusting means are connected to a power supply line, and one end of the constant current source and one end of the first adjusting means are connected to the output terminal of the first adjusting means. the other end of the constant current source is grounded, and the other end of the second adjusting means and the emitter of the second transistor are connected to the other end of the first adjusting means. , the base of the second transistor is fixed at a potential such that the emitters of the first and second transistors are at the same potential, and the collector of the second transistor is fixed to the base of the third transistor, the collector and the fourth transistor. , the emitters of the third and fourth transistors are DC grounded, and the collector of the fourth transistor is connected to the input end of the first means. and frequency deviation adjustment circuit.