JPS5885854U - blanking circuit - Google Patents
blanking circuitInfo
- Publication number
- JPS5885854U JPS5885854U JP18106581U JP18106581U JPS5885854U JP S5885854 U JPS5885854 U JP S5885854U JP 18106581 U JP18106581 U JP 18106581U JP 18106581 U JP18106581 U JP 18106581U JP S5885854 U JPS5885854 U JP S5885854U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- blanking circuit
- blanking
- transistor
- input side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Picture Signal Circuits (AREA)
- Details Of Television Scanning (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はブランキング回路の一例を示す回路図、第２図
は第１図のブランキング回路の動作を説明するための説
明図、第３図は本発明によるブランキング回路の一実施
例を示す回路図である。FIG. 1 is a circuit diagram showing an example of a blanking circuit, FIG. 2 is an explanatory diagram for explaining the operation of the blanking circuit of FIG. 1, and FIG. 3 is an example of a blanking circuit according to the present invention. FIG.
Claims (1)
２のトランジスタと、一定レベルの電流がエミッタ端子
から共通に供給される第３．第４のトランジスタとの夫
々のベースにブランキング−パルスを供給することによ
り、前記夫々のトランジスタをオン・オフ制御し、前記
一定レベルの電流により、所定レベルに設定されたブラ
ンキング期間を有する映像信号を得ることができるよう
にしたブランキング回路において、前記夫々のトランジ
スタのベース端子の入力側を高インピーダンスにするた
めの手段を設け、前記各トランジスタのベース・エミッ
タ間の静電容量に起因する雑音を減衰可能に構成したこ
とを特徴とするブランキング回路。The first one to which the video signal is commonly supplied from the emitter terminal. a second transistor and a third transistor to which a constant level of current is commonly supplied from the emitter terminal. By supplying a blanking pulse to the base of each of the fourth transistors, the respective transistors are controlled on and off, and the constant level current causes an image having a blanking period set to a predetermined level. In the blanking circuit that enables the signal to be obtained, means is provided for making the input side of the base terminal of each of the transistors high impedance, and the blanking circuit is configured to provide a means for making the input side of the base terminal of each of the transistors high impedance. A blanking circuit characterized by being configured to be able to attenuate noise.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18106581U JPS5885854U (en) | 1981-12-07 | 1981-12-07 | blanking circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18106581U JPS5885854U (en) | 1981-12-07 | 1981-12-07 | blanking circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5885854U true JPS5885854U (en) | 1983-06-10 |
| JPS6238375Y2 JPS6238375Y2 (en) | 1987-09-30 |
Family
ID=29978211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18106581U Granted JPS5885854U (en) | 1981-12-07 | 1981-12-07 | blanking circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5885854U (en) |
-
1981
- 1981-12-07 JP JP18106581U patent/JPS5885854U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6238375Y2 (en) | 1987-09-30 |
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