JPS60124167U - Video signal processing circuit - Google Patents
Video signal processing circuitInfo
- Publication number
- JPS60124167U JPS60124167U JP1143184U JP1143184U JPS60124167U JP S60124167 U JPS60124167 U JP S60124167U JP 1143184 U JP1143184 U JP 1143184U JP 1143184 U JP1143184 U JP 1143184U JP S60124167 U JPS60124167 U JP S60124167U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- processing circuit
- circuit
- signal processing
- amplitude
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Picture Signal Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来回路の一例の回路構成図、第2図は本考案
回路の一実施例の回路構成図、第3図A〜Eは第2図示
の回路各部の信号波形図である。
1、6.7・・・端子、2・・・映像信号伝送回路、3
・・・クランプ回路、4・・・中間調処理回路、5・・
・CRT、 fJ・・・ブランキング回路。FIG. 1 is a circuit configuration diagram of an example of a conventional circuit, FIG. 2 is a circuit configuration diagram of an embodiment of the circuit of the present invention, and FIGS. 3A to 3E are signal waveform diagrams of various parts of the circuit shown in FIG. 1, 6.7...Terminal, 2...Video signal transmission circuit, 3
... Clamp circuit, 4... Halftone processing circuit, 5...
・CRT, fJ...Blanking circuit.
Claims (1)
とする映像信号処理回路において、中間処理を指示する
制御信号の該映像信号の水平ブランキング期間に対応し
た部分を消去して出力するブランキング回路と、該映像
信号のクランプを行なう回路より前段に設けられており
該ブラシキング回路よりも制御信号を供給されて該映像
信号の直流レベル及び振幅のうち少なくとも一方を低下
させる中間調処理回路とを具備してなる映像信号処理回
路。In a video signal processing circuit that lowers the DC level and amplitude of a video signal to make an image halftone, a block that erases and outputs a portion of a control signal that instructs intermediate processing that corresponds to the horizontal blanking period of the video signal is used. a ranking circuit, and a halftone processing circuit that is provided before the circuit that clamps the video signal and is supplied with a control signal from the brushing circuit to reduce at least one of the DC level and amplitude of the video signal. A video signal processing circuit comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1143184U JPS60124167U (en) | 1984-01-30 | 1984-01-30 | Video signal processing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1143184U JPS60124167U (en) | 1984-01-30 | 1984-01-30 | Video signal processing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60124167U true JPS60124167U (en) | 1985-08-21 |
JPH0317505Y2 JPH0317505Y2 (en) | 1991-04-12 |
Family
ID=30493547
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1143184U Granted JPS60124167U (en) | 1984-01-30 | 1984-01-30 | Video signal processing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60124167U (en) |
-
1984
- 1984-01-30 JP JP1143184U patent/JPS60124167U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0317505Y2 (en) | 1991-04-12 |
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