JPS58123673U - Screen distortion correction circuit for television receivers - Google Patents
Screen distortion correction circuit for television receiversInfo
- Publication number
- JPS58123673U JPS58123673U JP1850182U JP1850182U JPS58123673U JP S58123673 U JPS58123673 U JP S58123673U JP 1850182 U JP1850182 U JP 1850182U JP 1850182 U JP1850182 U JP 1850182U JP S58123673 U JPS58123673 U JP S58123673U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- screen distortion
- signal
- correction circuit
- distortion correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Details Of Television Scanning (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のテレビジョン受信機の画面歪補正回路を
示す回路図、第２図は再生画面の絵柄を示す図、第３図
は第２図の絵柄再生時＆とおける第１図主要部の波形図
、第４図は再生画面の絵柄を示す図、第５図は第４図の
絵柄再生時における第１図主要部の波形図、第４図は本
考案の一実施例を示す回路図、第７図は第６図の主要部
の波形図である。Figure 1 is a circuit diagram showing the screen distortion correction circuit of a conventional television receiver, Figure 2 is a diagram showing the picture on the playback screen, and Figure 3 is the main part of Figure 1 when playing back the picture in Figure 2. FIG. 4 is a waveform diagram of the main part of FIG. 1 when the pattern in FIG. 4 is reproduced. FIG. 4 is a diagram showing an embodiment of the present invention. The circuit diagram, FIG. 7, is a waveform diagram of the main part of FIG. 6.
Claims (1)
する回路と、このビデオ信号に比例する信号を積分する
回路と、′積分した信号を増幅する回路とを備え、この
増幅した信号を可飽和トランスに加え、高圧負荷変動時
に於ける画面歪を補正する回路に於いて、このビデオ信
号に比例した信号に垂直ブランキングパルスか又は垂直
同期信号を加えることを特徴とするテレビジョン受信機
の画面歪補正回路。It is equipped with a circuit that detects a signal proportional to the video signal of the television receiver, a circuit that integrates the signal proportional to the video signal, and a circuit that amplifies the integrated signal. In addition to this, the screen distortion of a television receiver is characterized by adding a vertical blanking pulse or a vertical synchronizing signal to a signal proportional to the video signal in a circuit for correcting screen distortion during high voltage load fluctuations. correction circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1850182U JPS58123673U (en) | 1982-02-15 | 1982-02-15 | Screen distortion correction circuit for television receivers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1850182U JPS58123673U (en) | 1982-02-15 | 1982-02-15 | Screen distortion correction circuit for television receivers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58123673U true JPS58123673U (en) | 1983-08-23 |
Family
ID=30030753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1850182U Pending JPS58123673U (en) | 1982-02-15 | 1982-02-15 | Screen distortion correction circuit for television receivers |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58123673U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61193573A (en) * | 1985-02-22 | 1986-08-28 | Hitachi Ltd | High voltage control circuit of crt display device |
-
1982
- 1982-02-15 JP JP1850182U patent/JPS58123673U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61193573A (en) * | 1985-02-22 | 1986-08-28 | Hitachi Ltd | High voltage control circuit of crt display device |
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