JPS60144323U - Pulse generation circuit - Google Patents

Pulse generation circuit

Info

Publication number
JPS60144323U
JPS60144323U JP1984032033U JP3203384U JPS60144323U JP S60144323 U JPS60144323 U JP S60144323U JP 1984032033 U JP1984032033 U JP 1984032033U JP 3203384 U JP3203384 U JP 3203384U JP S60144323 U JPS60144323 U JP S60144323U
Authority
JP
Japan
Prior art keywords
circuit
pulse generation
generation circuit
current
constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984032033U
Other languages
Japanese (ja)
Inventor
八巻 和郎
孝彦 田村
徳原 正春
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP1984032033U priority Critical patent/JPS60144323U/en
Publication of JPS60144323U publication Critical patent/JPS60144323U/en
Pending legal-status Critical Current

Links

Landscapes

  • Processing Of Color Television Signals (AREA)
  • Pulse Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案を適用し得・る従来の自動ホワイトバラ
ンス調整回路を含むテレビ受像機のブロック図、第2図
は第1図のタイミングチャート、第3図は本考案の実施
例を示す回路図、第4図は第3図のタイミングチャート
である。 なお図面に用いた符号において、VBLK・・・垂直ブ
ランキングパルス、Q1〜Q□。・・・トランジスタ、
44・・・時定数回路、■、・・・定電流である。
Fig. 1 is a block diagram of a television receiver including a conventional automatic white balance adjustment circuit to which the present invention can be applied, Fig. 2 is a timing chart of Fig. 1, and Fig. 3 is an embodiment of the present invention. The circuit diagram and FIG. 4 are timing charts of FIG. 3. In the symbols used in the drawings, VBLK: vertical blanking pulse, Q1 to Q□. ...transistor,
44...Time constant circuit, ■,...Constant current.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 駆動パルスによりオン・オフされる定電流回路と、この
定電流回路の電流を充放電する時定数回′  路と、こ
の時定数回路の電圧により電流をオン・オフするスイッ
チ回路とから成るパルス発生回路。
Pulse generation consists of a constant current circuit that is turned on and off by driving pulses, a time constant circuit that charges and discharges the current of this constant current circuit, and a switch circuit that turns on and off the current according to the voltage of this time constant circuit. circuit.
JP1984032033U 1984-03-05 1984-03-05 Pulse generation circuit Pending JPS60144323U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984032033U JPS60144323U (en) 1984-03-05 1984-03-05 Pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984032033U JPS60144323U (en) 1984-03-05 1984-03-05 Pulse generation circuit

Publications (1)

Publication Number Publication Date
JPS60144323U true JPS60144323U (en) 1985-09-25

Family

ID=30533175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984032033U Pending JPS60144323U (en) 1984-03-05 1984-03-05 Pulse generation circuit

Country Status (1)

Country Link
JP (1) JPS60144323U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03185991A (en) * 1989-12-15 1991-08-13 Hitachi Ltd Automatic white balance adjustment circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03185991A (en) * 1989-12-15 1991-08-13 Hitachi Ltd Automatic white balance adjustment circuit

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