JPS60150653A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60150653A JPS60150653A JP59005727A JP572784A JPS60150653A JP S60150653 A JPS60150653 A JP S60150653A JP 59005727 A JP59005727 A JP 59005727A JP 572784 A JP572784 A JP 572784A JP S60150653 A JPS60150653 A JP S60150653A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- eutectic
- plate
- pattern
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052802 copper Inorganic materials 0.000 claims abstract description 35
- 239000010949 copper Substances 0.000 claims abstract description 35
- 239000011819 refractory material Substances 0.000 claims abstract description 9
- 239000008188 pellet Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 230000005496 eutectics Effects 0.000 abstract description 16
- 239000000919 ceramic Substances 0.000 abstract description 15
- 239000000758 substrate Substances 0.000 abstract description 8
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 6
- 238000005304 joining Methods 0.000 abstract description 5
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 239000007789 gas Substances 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 238000003486 chemical etching Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052755 nonmetal Inorganic materials 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 229910052845 zircon Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Products (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は、大電力］−ランジスタ、サイリスクモジュー
ル等の半導体装置に関し、待に人４ノイズのベレット又
は外部接続端子等を直接１δ合できる半導体素子搭載用
基椴を有する生産↑１の良い半導体装置である。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to semiconductor devices such as high-power transistors and silice modules, and relates to semiconductor devices that can directly connect 4-noise bullets or external connection terminals by 1δ. It is a semiconductor device with a good production rate of ↑1, which has a base board for mounting elements.
［冗明の技術向背ｆｆｉ］
従来の大電力トランジスタやザイリスタモジュール等の
半導体装置にあっては第１図のごとき手工９体素子搭載
用基板１が使用されることが多い。[Unexpected Technical Disadvantage] In conventional semiconductor devices such as high-power transistors and Zyristor modules, a handcrafted nine-element mounting board 1 as shown in FIG. 1 is often used.
間板１は非金属耐火１Ａ料板３（セラミック板ともいう
）、回路パターン２および下部銅板４により構成される
。 回路パターン２は種々の形状の銅又は銅合金の銅系
金属板２ａ （パターン部品２ａどｂいう）からなり、
パターン部品２ａはセラミック板３の上面に接合され所
定の回路パターン２を形成する。 下部鋼板４は銅又は
銅合金の銅系金属板でセラミック板３の下面に接合され
実装時には放熱器又は架台等に固着され、多くの場合ア
ース電位で使用される。 パターン部品２ａはパターン
形状に応じて分【ノてプレス打抜等にて作成され、セラ
ミック板３に治具等で位置を決めてから炉通し接合され
る。 この接合方法にはセラミックをメタライズしてｐ
ｌｙ−８ｎはんだ等を用い間接に接合Ｊる方法や特開昭
５８−１０３９８４号および特開昭５８−１０２５３２
号に開示されている方法が用いられる。 回路パターン
２の所定のパターン部品２ａ上にはこれど接合した半導
体ベレット等があり半導体装置を形成゛りる。The spacer plate 1 is composed of a nonmetallic refractory 1A material plate 3 (also referred to as a ceramic plate), a circuit pattern 2, and a lower copper plate 4. The circuit pattern 2 consists of copper-based metal plates 2a (referred to as pattern parts 2a and b) made of copper or copper alloy in various shapes,
The pattern component 2a is bonded to the upper surface of the ceramic plate 3 to form a predetermined circuit pattern 2. The lower steel plate 4 is a copper-based metal plate made of copper or a copper alloy, and is bonded to the lower surface of the ceramic plate 3. When mounted, it is fixed to a heat sink or a frame, and is often used at ground potential. The pattern component 2a is created by punching with a press or the like according to the pattern shape, and after being positioned on the ceramic plate 3 using a jig or the like, it is bonded through a furnace. This joining method involves metallizing the ceramic and p
Indirect bonding method using LY-8N solder etc. and JP-A-58-103984 and JP-A-58-102532
The method disclosed in No. A semiconductor pellet or the like is bonded to a predetermined pattern component 2a of the circuit pattern 2 to form a semiconductor device.
［背景技術の問題点」
従来の半導体素子搭載用基板１は回路パターン２を構成
覆るパターン部品２ａをぞれぞれ個々にプレス打抜等の
方法にＣ作成しレラミック仮３３に接合したものである
。 このよ゛）な崖）♀体素子搭載用基板１には次のご
とき問題点かある。 通畠プレス加工の工程が増える分
たけＩｔｌｉ格が高くなる。[Problems in the Background Art] The conventional substrate 1 for mounting semiconductor elements is made by individually forming pattern parts 2a that constitute and cover the circuit pattern 2 by a method such as press punching, and joining them to a relamic temporary 33. be. The following problems arise with this type of device mounting substrate 1. The more the number of steps in the Tobata press process increases, the higher the Itli rating will be.
そのため個々のパターン部品２ａの（Φ類が多くなれば
基板の価格も畠くなる。 又位置）ノシめのためにパタ
ーン部品２ａを治具にセットする時間が増加し価格高ど
なる。 又回路パターン２の刈払粘度は治具の精度ど治
具による位１ｍ決め作業により左右される。 まＩごパ
ターン部品２ａ 、 Ｌ！ラミック板３および冶具等の
線膨張係数イを吸収覆るため相互の嵌合に相当のスキマ
を設けるのＣ′接合された回路パターン２の精度が良く
ない。 一般に個々のパターン部品は細長いものが多く
、変形し゛１Ｙ〕リ−く取扱いが大変である。 そのた
め不良の原因どもなっている。As a result, the cost of each pattern component 2a increases (as the number of Φ types increases, the cost of the board also increases. Also, the time required to set the pattern component 2a on a jig for cutting position) increases, resulting in an increase in price. Moreover, the cutting viscosity of circuit pattern 2 is influenced by the accuracy of the jig and the work of determining the distance of 1 m using the jig. Ma Igo pattern parts 2a, L! In order to absorb and cover the coefficient of linear expansion of the ramic plate 3 and the jig, etc., a considerable gap is provided for mutual fitting, but the precision of the circuit patterns 2 that are C'-joined is not good. In general, individual pattern parts are often long and narrow, deformable, and difficult to handle. Therefore, it becomes the cause of defects.
以上のことから回路パターンの形状が復雑なもの（、表
と上記問題点が大きくなり半導体素子搭載用４仮の価格
は高くな１つ精度し悉くなり、これを使用する半導体装
置に悪影υ上を与えくいる。From the above, if the shape of the circuit pattern is complicated (Table 1), the above-mentioned problems will increase, the price will be high, and the accuracy will be reduced, which will have a negative impact on the semiconductor device that uses it. Give υ above.
［発明の目的コ
４＼光明は入電）〕トランジスタ、サイリスタモジュー
ル等の半導体装置において、半導体素子搭載用基板に関
りる前記問題点を解決し、組立工程が簡単でパターン積
瓜の良い半導体素子搭載用基板を具（釉づる生産性の優
れた半導体装置を提供すること・３目的どりる。[Objective of the invention 4\Gwangmyeong is receiving electricity] To solve the above-mentioned problems related to substrates for mounting semiconductor elements in semiconductor devices such as transistors and thyristor modules, and to provide a semiconductor element with a simple assembly process and good pattern stacking. Three objectives: To provide semiconductor devices with excellent productivity by glazing mounting substrates.
［発明の概要］
本発明の半導体装置は（ａ ）非金属耐火材料板と、（
［１）該非金属耐火材料板＋：Ｃｕ−Ｃｕ、Ｑ」（晶接
合８れるどともに、該接合された一枚の又はパターン連
結形の銅系金属板からエツチング若しくは機械加工され
ＩＣ回路パターンと、（Ｃ）該回路パターンの面にダイ
ボンデインクした半導体ベレットどを貝１悄することを
特１攻とづる゛１′ン；う１４−装置である。 ツなわ
ら本発明の４′尋体装置に使用される半導体素子搭載用
基板は回路パターンを非金属耐火材料板にＣｕ −ｃｕ
２０共品接合し１．：ものＣある＜ ｆｉ間昭５８−
１０３９８／Ｉ号おＪ、σ特開昭５８−１０２５３２号
）。 またこの回路パターンは非金属耐火′４／Ｊ￥３
１板にＣｌ１−ＣＩｌ ：！ ＯＪｔ品接合された一枚
の銅又は銅合金の銅系金属１ｋからエツチングにＪ：り
形成されたしのである。 あるいはまたこの回路パター
ンは、パターン部品を補強と、個々の部品に分離しない
ように相互を連結し一体としｌどパターン連結形（・あ
っｃ、Ｊｌ企屈耐火ｖＪ料板にＣＬＩ −ＣＩｌ ２０
共晶接合された銅系金属板からエツチング若しくは機械
加二りにＪ、り連結した部分を除去したちのｅある。
本発明では上記のごとく半導体素子搭載用基板の回路パ
ターンがＣｕ−Ｃｕ２Ｏ共晶接合された一枚の又はパタ
ーン連結形の銅系金属板から得られるのぐ従来の問題点
を解決することができる。 またＱｕ−Ｃｕ２０共品接
合された回路パターンは非金属耐ゾ＜ ４Ａ ＩＩ仮と
強靭な接合を形成するどともに回路パターンの熱膨張係
数がシリコンなど半導体ペレツ１〜のそれに近づき熱緩
衝様を介在させずに人１ナイズのベレットを直接パター
ン部品にダイボンディングすることが可ｆｉＬである。[Summary of the Invention] The semiconductor device of the present invention includes (a) a nonmetallic refractory material plate;
[1] Said non-metallic refractory material plate +: Cu-Cu, Q'' (crystal bonded 8) and etched or machined from said bonded single or pattern-connected copper-based metal plate to form an IC circuit pattern. , (C) This is a special attack device in which a semiconductor pellet is die-bonded and inked on the surface of the circuit pattern. The circuit pattern is printed on a non-metallic refractory material plate using Cu-cu.
20 items joined together 1. : There is a thing C< fi period 1978-
10398/I OJ, σ JP-A-58-102532). Also, this circuit pattern is non-metal fireproof '4/J ¥3
Cl1-CIl on one board:! It is formed by etching from a single piece of copper-based metal 1k of copper or copper alloy that has been bonded as an OJt product. Alternatively, this circuit pattern can be used to strengthen the pattern parts and connect them to each other so as not to separate them into individual parts.
The connected portions are removed by etching or mechanical machining from eutectic bonded copper-based metal plates.
As described above, the present invention can solve the problems of the conventional method in which the circuit pattern of a semiconductor element mounting board is obtained from a single copper-based metal plate bonded with Cu-Cu2O eutectic or a pattern-connected copper-based metal plate. . In addition, the circuit pattern bonded with Qu-Cu20 has a non-metal resistance resistance of < 4A II and forms a strong bond, and the thermal expansion coefficient of the circuit pattern approaches that of semiconductor pellets such as silicon with a thermal buffer provided. It is possible to directly die-bond a bullet of one size per person to a patterned part without causing any damage.
以上により生産性の優れた特性の均一な大電力トランジ
スタ、サイリスクモジュール等の半導体装置を提供する
ことが可能である。As described above, it is possible to provide semiconductor devices such as high-power transistors, silice modules, etc. with uniform characteristics and excellent productivity.
非金属耐火４ＡＪａｉｌ板としくはアルミナ、へりリア
、）Ａルスデライ１〜、ジルコン、マグネシア、石英、
スピネル等が挙げられる。 また銅系金属板とじ（は銅
又は銅合金Ｃ１０，００８重望％以上０．３９重早％未
満の酸素を含有するものを使用する。Non-metallic fireproof 4A Jail plates include alumina, herria, )A Lusdelai 1~, zircon, magnesia, quartz,
Examples include spinel. In addition, copper-based metal sheet binding (copper or copper alloy C containing 10,008% by weight or more and less than 0.39% by weight of oxygen) is used.
［発明の実施例１
第１図ないし第３図にムどづい″′Ｃ本発明を具体的に
説明ツる。 第１図の半導体素子搭載用基板１は従来の
ぞれど外観はほぼ同一であって回路パターン２、非金属
耐火材料板３（以下セラミック板という）および下部銅
板４により構成される。[Embodiment 1 of the Invention The present invention will be explained in detail with reference to FIGS. 1 to 3. The semiconductor element mounting substrate 1 shown in FIG. It is composed of a circuit pattern 2, a nonmetallic refractory material plate 3 (hereinafter referred to as a ceramic plate), and a lower copper plate 4.
回路パターン２は種々の形状のパターン部品２ａにより
形成される。 回路パターン２は第１図に示Ｍ例Ｃは＋
０１１４１のパターン部品２ａＪ：り成る。The circuit pattern 2 is formed by pattern components 2a of various shapes. Circuit pattern 2 is shown in FIG.
01141 pattern part 2aJ: consists of.
下部銅板４ Ｊ３ Ｊ、ひパターン部品２ａ１．Ｌ銅又
は銅合金の銅系金属板で例えば厚さ ０．３ｍｍ、酸素
含（４？０．０４重里％の電ｆ１？銅板を使用り−く）
っ ：！ ／、：Ｊｌ”金属耐火月料板３シま例えば厚
さ Ｏ，Ｃ１３ｍｍの９６％△１２０３のセラミック板
である。 パターン部品２ａど銅板４（よ’１６間昭５
８−１０２５３２号Ｊ５Ｊこび特開昭５８−１０３９８
４月に開示されている方法によつ−（セラミック板３に
接合されＣいる。Lower copper plate 4 J3 J, pattern parts 2a1. Use a copper-based metal plate made of L copper or copper alloy, for example, 0.3 mm thick and containing oxygen (4% to 0.04% F1 copper plate).
:! /, :Jl" metal refractory plate 3 is a ceramic plate with a thickness of 96%△1203 with a thickness of O, C13mm. Patterned parts 2a, etc.
No. 8-102532 J5J Kobi JP 1987-10398
It is bonded to the ceramic plate 3 by the method disclosed in April.
リーなわら前記銅系金属板をレンミック（ｋに１台るさ
せてコンベア一式加熱炉中に仕込・７メ、Ｎ２気流中Ｃ
例えば１０７０℃に１０分間保持ηる。 この間前記銅
系金属板の表面はＣ１ｌ ＣＬ１２０の共ｈ（１体によ
って濡れ、その後徐冷りるど共融イホは共晶に生長し前
記銅系金属板と一体組織どなり、池方共融体はレラミッ
クの微細な間隙に注入したよｓｉ： Ｊ（品に生長し接
合するので前記銅系金１ｉら仮は共晶を介してセラミッ
ク板と強靭に接合される。 回路パターン２は次の方法
により形成されたちのである。Then, the copper-based metal plate was placed in a heating furnace with a conveyor set (one unit was placed in the remik).
For example, it is held at 1070° C. for 10 minutes. During this time, the surface of the copper-based metal plate is wetted by a eutectic body of C1l and CL120, and then slowly cooled to form a eutectic structure, forming an integral structure with the copper-based metal plate, forming an Ikegata eutectic. is injected into the minute gaps of the reramic. Since the copper-based gold 1i grows and bonds to the product, the copper-based gold 1i is strongly bonded to the ceramic plate through the eutectic.Circuit pattern 2 is made by the following method. It is formed by.
ぞの一つは第２図に示すごとくセラミック板３の上面下
面にそれぞれ一枚の銅板４が前記ＣＵ −ＣＩ＋２０共
晶を利用して接合される。Ｉ？ラミック板３の上面の銅
板４に通常のケミカルエツチング方法と同様レジストを
ｔ８ ’ｆＩｉ Ｌ、パターンを印刷し−（、所定の回
路パターンを塩化第二鉄等の薬品でケミカルエツチング
して作成覆る。 他の一つは第３図に示すごとくセラミ
ック板３の上面にパターン連結形の銅板２′を又セラミ
ック板３の下面に銅（ル４を（れぞれ前記Ｃｕ −Ｃｌ
２０共晶を利用しく接合ヅる。 パターン連結形の銅
板２′は回路パターン２を構成するパターン部品２ａを
補強と分離しないように相互に連結したもので前記銅系
金属４ｆｉからプレス打抜き、放電加工あるいはケミカ
ルエツチング等の方法により作られる。In one of these, as shown in FIG. 2, one copper plate 4 is bonded to the upper and lower surfaces of the ceramic plate 3, respectively, using the CU-CI+20 eutectic. I? A pattern is printed on the copper plate 4 on the upper surface of the ramic plate 3 using a resist similar to the usual chemical etching method, and a predetermined circuit pattern is created and covered by chemical etching with a chemical such as ferric chloride. The other one, as shown in FIG.
20 eutectic is used for joining. The pattern-connected copper plate 2' is made by interconnecting the pattern parts 2a constituting the circuit pattern 2 so as not to separate them from the reinforcement, and is made from the copper-based metal 4fi by press punching, electric discharge machining, chemical etching, etc. .
亡ラミック板３に接合されたパターン連結形の銅１１Ｍ
２ ’ のパターン部品２ａの相互に連結された部分
を通常のケミカルエツチングの方法によりあるいはトリ
ミング等の機械的方法により除去し、第１図に示す回路
パターン２が得られる。Pattern-connected copper 11M bonded to lamic board 3
The interconnected portions of pattern parts 2a of 2' are removed by a conventional chemical etching method or by a mechanical method such as trimming, to obtain the circuit pattern 2 shown in FIG.
所定のパターン部品２ａ土に半導体チップ、外部接続端
子、接続リード等が格戟され４′導体装置を形成−りる
。A semiconductor chip, external connection terminals, connection leads, etc. are arranged on a predetermined patterned part 2a to form a 4' conductor device.
［発明の効果コ
本発明によれば半２９体素子搭載用基板の回路パターン
は非金属耐火材料板にＣ（１−Ｃ１１２０共晶接合され
ているのＣ・人サイズの半Ｌ’Ｊ ｆ４ｉベレツｌ−が
直接基板に接合りることがでさ放熱特１゛１シ良くなる
。 また本発明によれば基板上に形成された回路パター
ンのパターン部品【よりミカルエツヂングまｌζはプレ
ス加工により同吋にう１１作されるの’Ｃ： ％ｆ末の
パターン部品に分は個々にプレス製作しでいたのに比し
パターン部品製作工程が大幅に減少りる。 これは回路
パターンの形状が１ｖ雑になればなるほど効果が大にな
る。 例えばパターンＩａ１品点数が１０点あればバク
ーン部品製作１：稈）Ｊ約１／１０に減少する。 従来
のものはパターン部品をセラミック板に接０ｇる場合、
位ぼ決めのために治具をセットするが、このセツティン
グ時間し大幅に減り、かつ治具合せによる変形位置ズレ
も無くなる。 また従来に比しパターンの位置精度が良
くなり従来は±０．２１１１’ｌｌｌが限界であったが
、±０．０２ｍｍの粘度が（ｑられるようになり、複雑
な回路、微細な回路も容易に作ることかできるようにな
る。 これも回路が複雑になる程効果が大となる。 両
路で考えれば、回路パターンのパターン部品数が１０〜
１５点の場合従来のものに比べて３０％は安くできる。[Effects of the Invention] According to the present invention, the circuit pattern of the semi-29 element mounting board is C (1-C1120 eutectic bonded to the non-metallic refractory material plate). The heat dissipation properties are improved by directly bonding the l- to the board.Furthermore, according to the present invention, the patterned parts of the circuit pattern formed on the board can be bonded directly to the board by mechanical etching or by press working. 11 will be made in the next year'C: Compared to the case where the pattern parts at the end of %f were manufactured individually by press, the pattern part manufacturing process is greatly reduced.This is because the shape of the circuit pattern is For example, if the number of 1 items of pattern Ia is 10, the number of Bakun parts production 1: culm) J will be reduced to about 1/10. With the conventional model, when the pattern part is connected to the ceramic plate at 0g,
A jig is set for positioning, but the setting time is greatly reduced, and the deformation position deviation due to jig adjustment is also eliminated. In addition, the positional accuracy of the pattern has improved compared to before, and the viscosity of ±0.02mm (q) is now possible, whereas the previous limit was ±0.2111'lll, making it easier to create complex and fine circuits. This also becomes more effective as the circuit becomes more complex.If you consider both ways, the number of pattern components in the circuit pattern will be 10 to 10.
In the case of 15 points, it can be made 30% cheaper than the conventional one.
第１図は従来例および本発明の半導体素子塔載用基板を
示Ｊ図面で同図（ａ ）、（ｂ）はそれぞれ平面図、Ａ
−Ａ線断面図、第２図は非金属耐火４Δ科板の両面にそ
れぞれ一枚の銅系金属板がＣｕ−Ｃｔ＋２０Ｊｔ−品４
８合された基板を示す図面で同図（ａ）、（ｂ）はそれ
ぞれ平面図、［３−Ｂｌｄ断面図、第３図は非金属耐火
材料板にｃｕ −ｃｕ ２０共品接合されたパターン連
結形の銅系金属板を具備づる基板を示１図面で、同図（
ａ ）、（ｂ）はそれぞれ平面図、Ｃ−ＣＦＡｇｌｌｉ
ｉＩｉｉ図である。
１・・・半導体素子搭載用基板、 ２・・・回路パター
ン、 ２′・・・パターン連結形の銅系金属楡、２ａ・
・・回路パターンを４笥成する銅系金属板＜１＜ターン
部品ともいう）、 ３・・・非金属耐火材料板−（１ラ
ミツク板としいう）、 ４・・・一枚の朴シ系金属板。Figure 1 shows a conventional example and a substrate for mounting a semiconductor element according to the present invention.
-A cross-sectional view, Figure 2 shows one copper-based metal plate on each side of the non-metallic fireproof 4Δ plate.
Figures (a) and (b) are plan views, respectively, and a 3-Bld cross-sectional view, and Figure 3 shows a pattern in which CU-CU 20 were bonded to a non-metallic refractory material plate. Figure 1 shows a board equipped with connected copper-based metal plates.
a) and (b) are plan views, C-CFAgli
Figure iii. DESCRIPTION OF SYMBOLS 1... Semiconductor element mounting board, 2... Circuit pattern, 2'... Pattern-connected copper-based metal frame, 2a.
・・Copper-based metal plate that forms 4 circuit patterns<1<<Also referred to as turn parts), 3...Non-metallic fireproof material board (referred to as 1 lamic board), 4...One piece of parchment type metal plate.
Claims (1)
接合されるどどもに、該接０された一枚の又はパターン
連結形の銅系金属板からエツチング若しくは機械加工さ
れノこ回路パターンと、 （Ｃ）該回路バクーンの面にクイボンデヂングした半導
体ペレットと を具備り゛ることを特徴とりる手心ＩＡ装置。[Scope of Claims] 1 (a) A nonmetallic refractory material plate; 1. A manual IA device comprising: a sawtooth circuit pattern etched or machined from a pattern-connected copper-based metal plate; and (C) a semiconductor pellet bonded to the surface of the circuit backing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59005727A JPS60150653A (en) | 1984-01-18 | 1984-01-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59005727A JPS60150653A (en) | 1984-01-18 | 1984-01-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60150653A true JPS60150653A (en) | 1985-08-08 |
Family
ID=11619153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59005727A Pending JPS60150653A (en) | 1984-01-18 | 1984-01-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60150653A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6365653A (en) * | 1986-09-05 | 1988-03-24 | Dowa Mining Co Ltd | Manufacture of ceramic wiring board |
| FR2623046A1 (en) * | 1987-11-10 | 1989-05-12 | Telemecanique Electrique | METHOD FOR BINDING A COPPER SHEET TO A SUBSTRATE OF ELECTRICALLY INSULATING MATERIAL |
-
1984
- 1984-01-18 JP JP59005727A patent/JPS60150653A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6365653A (en) * | 1986-09-05 | 1988-03-24 | Dowa Mining Co Ltd | Manufacture of ceramic wiring board |
| JPH058866B2 (en) * | 1986-09-05 | 1993-02-03 | Dowa Mining Co | |
| FR2623046A1 (en) * | 1987-11-10 | 1989-05-12 | Telemecanique Electrique | METHOD FOR BINDING A COPPER SHEET TO A SUBSTRATE OF ELECTRICALLY INSULATING MATERIAL |
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