JPH0613755A - Ceramic multilayer wiring board and manufacture thereof - Google Patents

Ceramic multilayer wiring board and manufacture thereof

Info

Publication number
JPH0613755A
JPH0613755A JP4170595A JP17059592A JPH0613755A JP H0613755 A JPH0613755 A JP H0613755A JP 4170595 A JP4170595 A JP 4170595A JP 17059592 A JP17059592 A JP 17059592A JP H0613755 A JPH0613755 A JP H0613755A
Authority
JP
Japan
Prior art keywords
ceramic
wiring board
green sheet
multilayer wiring
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4170595A
Other languages
Japanese (ja)
Inventor
Shosaku Ishihara
昌作 石原
Norihiro Ami
徳宏 阿美
Takashi Kuroki
喬 黒木
Seiichi Tsuchida
誠一 槌田
Etsuko Takane
悦子 高根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4170595A priority Critical patent/JPH0613755A/en
Publication of JPH0613755A publication Critical patent/JPH0613755A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To enable a thin film wiring layer to be well formed so as to enhance a ceramic multilayer wiring board in reliability by a method wherein conductor pattern exposed on both sides of a ceramic multilayer wiring board is formed flush with the surface of ceramic. CONSTITUTION:A flat thin film wiring layer 1 is formed on one side of a ceramic multilayer wiring board where a conductor pattern is exposed, and a sealing cap can be joined firmly. Input/output pins 7, solder bumps, and the like can be bonded onto the other side of ceramic wiring board firmly. As the through-hole conductor metal layer 2 of an outer ceramic green sheet 81 is larger than that of inner ceramic green sheets 83 and 84 in area, the misalignment of the through-hole conductor metal layer 2 for electrical connection of the outer ceramic green sheet 81 to the inner ceramic green sheets 83 and 84 due to burning shrinkage is absorbed to surely connect the outer sheet 81 to the inner sheets 83 and 84, and furthermore the through-hole conductor metal layer 2 of the green sheet is large in area, so that the metal layer 2 is firmly fixed to a ceramic 4, and input/output pins 7, solder bumps, and a sealing cap can be enhanced in bonding strength.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、セラミック配線基板に
係り、とくに基板表裏面のI/Oピンや封止キャップ等
の接続強度を強化した平坦なセラミック配線基板及びそ
の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic wiring board, and more particularly to a flat ceramic wiring board having enhanced connection strength such as I / O pins and sealing caps on the front and back surfaces of the board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】セラミック配線基板は、小型化が可能で
信頼性が高いため半導体チップや小型電子部品搭載用の
基板として電子計算機、通信機器、家電品等に用いら
れ、とくに、グリ−ンシ−トを用いた湿式セラミック配
線基板は高密度配線に有利であるので広く用いられてい
る。この湿式セラミック配線基板は、セラミック原料粉
末を有機樹脂で結合したセラミック生シ−ト(以下、グ
リ−ンシ−ト)に貫通孔を加工した後、各シ−トに導体
ペ−ストの配線パタ−ンを形成して配線パタ−ンを接続
する貫通孔にも導体ペ−ストを充填し、これを所定枚数
積層して圧着後、焼成して作製される。
2. Description of the Related Art Ceramic wiring boards are used in electronic calculators, communication devices, home appliances, etc. as substrates for mounting semiconductor chips and small electronic parts because they can be miniaturized and have high reliability. Wet-type ceramic wiring boards that use switches are widely used because they are advantageous for high-density wiring. In this wet type ceramic wiring board, a through hole is formed in a ceramic raw sheet (hereinafter referred to as a green sheet) in which ceramic raw material powder is bonded with an organic resin, and then a wiring pattern of a conductor paste is formed on each sheet. The conductive paste is also filled in the through holes for forming the patterns and connecting the wiring patterns, a predetermined number of the conductive pastes are stacked, pressure-bonded, and then baked.

【0003】また、日経エレクトロニクス、1985
年、6月17日、P243〜266「マルチチップ・パ
ッケ−ジを水冷する」に記載のように、上記焼成したセ
ラミック配線基板の表面に、さらに薄膜配線を形成し、
裏面には入出力ピンがろう材を接続したりする。また、
入出力端子が微小で配置密度が高い場合には、はんだバ
ンプを形成して上記入出力ピンを接続し、LSIやチッ
プキャリア等を搭載後、キャップ等をはんだ封じしてこ
れらを気密保護する。
Nikkei Electronics, 1985
, June 17, pp. 243 to 266 "Water cooling the multi-chip package", further forming thin film wiring on the surface of the fired ceramic wiring board,
I / O pins connect the brazing material on the back side. Also,
When the input / output terminals are minute and the arrangement density is high, solder bumps are formed to connect the input / output pins, and after mounting an LSI, a chip carrier, etc., a cap or the like is sealed with solder to hermetically protect them.

【0004】上記薄膜配線を形成する必要上、基板表面
には平坦性が要求される。これに対して焼成後のセラミ
ック配線基板には反りや凹凸や基板表面の配線パタ−ン
の突出があるため、基板表面を平坦に研磨する必要があ
った。しかし、基板表面を平坦に研磨するためには基準
面となる基板裏面側をまず平坦に研磨する必要があっ
た。また、特開平1−140699号公報には、セラミ
ック基板表面の配線導体を加熱、加圧してその厚み分だ
け表面層に埋め込むようにすることが開示されている。
In order to form the above-mentioned thin film wiring, the substrate surface is required to have flatness. On the other hand, since the ceramic wiring substrate after firing has a warp, an unevenness, and a protrusion of the wiring pattern on the substrate surface, it is necessary to polish the substrate surface flat. However, in order to polish the surface of the substrate flat, it was necessary to first polish the back surface of the substrate, which is the reference surface, to be flat. Further, Japanese Patent Application Laid-Open No. 1-140699 discloses that a wiring conductor on the surface of a ceramic substrate is heated and pressed to be embedded in the surface layer by the thickness thereof.

【0005】[0005]

【発明が解決しようとする課題】上記従来技術において
は、セラミック配線基板の表裏面を平坦にすることを主
眼としているため、セラミック配線基板裏面の入出力ピ
ンやはんだバンプ等の接続強度、基板表面の封止強度等
が不十分で配慮されていないといういう問題があった。
すなわち、セラミック配線基板の表裏面を研磨するの
で、基板裏面に接続する入出力用のパタ−ン、基板表面
の封止パタ−ン等は薄膜で形成される。このためピン接
続強度、バンプ剪断強度、封止強度等はこれらをセラミ
ック配線基板表裏面の厚膜パタ−ン上に直接設ける場合
に較べて約1/2〜1/3に弱くなり、十分な信頼性が
得られなかった。本発明の目的は、上記の問題を解消し
たセラミック配線基板とその製造方法を提供することに
ある。
In the above-mentioned prior art, since the main object is to make the front and back surfaces of the ceramic wiring board flat, the connection strength of the input / output pins and solder bumps on the back surface of the ceramic wiring board, the board surface. However, there is a problem that the sealing strength and the like are insufficient and no consideration is given.
That is, since the front and back surfaces of the ceramic wiring board are polished, the input / output pattern connected to the back surface of the board, the sealing pattern on the board surface, etc. are formed of thin films. Therefore, the pin connection strength, the bump shear strength, the sealing strength, etc. are weakened to about 1/2 to 1/3 as compared with the case where these are directly provided on the thick film pattern on the front and back surfaces of the ceramic wiring board, which is sufficient. The reliability was not obtained. An object of the present invention is to provide a ceramic wiring board and a method for manufacturing the same that solve the above problems.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
に、セラミック多層配線基板の表裏面に露出する導体パ
タ−ン面をセラミック表面と同一平面になるようにし、
その上に薄膜配線層を形成し、また、上記表面裏面に露
出する導体パタ−ン面に金属めっき膜を設けて入出力ピ
ン、はんだバンプ、封止キャップ等を接続するようにす
る。また、上記セラミック多層配線基板を、貫通孔に導
体金属を充填したセラミックグリ−ンシ−トを積層し、
さらにその表面の少なくとも片面に上記貫通孔より大き
な面積の貫通孔に導体金属を充填した表層用のセラミッ
クグリ−ンシ−トを積層して焼成し、次いで上記表層用
セラミックグリ−ンシ−トの表面を平坦に研磨して製造
する。
In order to solve the above-mentioned problems, the conductor pattern surfaces exposed on the front and back surfaces of the ceramic multilayer wiring board are made flush with the ceramic surface.
A thin film wiring layer is formed thereon, and a metal plating film is provided on the conductor pattern surface exposed on the front and back surfaces to connect the input / output pins, solder bumps, sealing caps and the like. In addition, the above ceramic multilayer wiring board is laminated with a ceramic green sheet having a through hole filled with a conductive metal,
Further, on at least one surface of the surface, a ceramic green sheet for surface layer in which a conductive metal is filled in a through hole having an area larger than the through hole is laminated and fired, and then the surface of the ceramic green sheet for surface layer. Is ground flat and manufactured.

【0007】このため、上記焼成前の表層用セラミック
グリ−ンシ−ト上にセラミックグリ−ンシ−トを積層し
て焼成し、次いで上記焼成後のセラミックグリ−ンシ−
ト体の表面を平坦に研磨して上記表層用セラミックグリ
−ンシ−トの貫通孔導体金属面を露出するようにし、上
記貫通孔導体金属の露出面に入出力ピン、はんだバン
プ、封止キャップ、薄膜配線層等を接続するようにす
る。
Therefore, a ceramic green sheet is laminated on the ceramic green sheet for surface layer before firing and fired, and then the ceramic green sheet after firing is fired.
The surface of the package body is flatly polished to expose the through-hole conductor metal surface of the surface layer ceramic green sheet, and the input / output pins, solder bumps, and sealing caps are exposed on the through-hole conductor metal surface. , The thin film wiring layer, etc. are connected.

【0008】[0008]

【作用】導体パタ−ン面が露出したセラミック多層配線
基板の片面には薄膜配線層が平坦に形成され、また、封
止キャップが密着性良く接続される。また、他の面には
入出力ピンやはんだバンプ等が密着性良く接続される。
また、上記表層セラミックグリ−ンシ−トの貫通孔導体
金属部の面積は内層部セラミックグリ−ンシ−トの貫通
孔導体金属部面積より大きいので、焼き縮み等により表
層部と内層部セラミックグリ−ンシ−トの貫通孔導体金
属の位置ずれを吸収して表層部と内層部間の接続を確実
にし、さらに、面積が大きいのでセラミック部に強固に
固着して入出力ピン、はんだバンプ、封止キャップ等の
接続強度を高める。
The thin film wiring layer is formed flat on one surface of the ceramic multi-layer wiring board with the conductor pattern surface exposed, and the sealing cap is connected with good adhesion. Input / output pins, solder bumps, etc. are connected to the other surface with good adhesion.
Since the area of the through-hole conductor metal portion of the surface layer ceramic green sheet is larger than the through-hole conductor metal portion area of the inner layer portion ceramic green sheet, the surface layer portion and the inner layer portion ceramic green portion due to shrinkage or the like. Through-hole of the sheet absorbs the displacement of the conductor metal to ensure the connection between the surface layer and the inner layer, and because the area is large, it is firmly fixed to the ceramic part and the input / output pins, solder bumps, and sealing Increase the connection strength of the cap, etc.

【0009】また、上記表層部セラミックグリ−ンシ−
トの焼成後の厚みを上記研磨量以上にするので研磨によ
り表層部の貫通孔導体金属部が削りとられることがな
い。焼成前に上記表層部の上に設けたグリ−ンシ−ト
は、貫通孔導体金属部面積がとくに大きい場合の導体ペ
−ストの充填を確実、容易化する。
Further, the surface green ceramic green sheet
Since the thickness of the conductive layer after firing is set to the above polishing amount or more, the through hole conductor metal portion of the surface layer portion is not scraped off by polishing. The green sheet provided on the surface layer portion before firing surely and easily fills the conductor paste when the area of the through-hole conductor metal portion is particularly large.

【0010】[0010]

【実施例】〔実施例 1〕図1は本発明により完成され
たムライト系材料のセラミック配線基板の部分断面図で
あり、図2に示す焼成前のセラミック配線基板をベ−ス
にして製作する。
[Embodiment 1] FIG. 1 is a partial cross-sectional view of a ceramic wiring board of a mullite material completed according to the present invention. The ceramic wiring board before firing shown in FIG. 2 is prepared as a base. .

【0011】まず、図2における各グリ−ンシ−トの作
製方法を説明する。グリ−ンシ−ト用のスラリ−は、7
2wt%のムライトの微粉末と、28wt%のアルミ
ナ、シリカ、マグネシア微粉末の焼結助剤よりなるセラ
ミック粉末6gに、ポリビニルブチラ−ルの有機バイン
ダ−とブチルフタリル・ブチルグリコレ−トよりなる可
塑剤2gを加え、さらにこれにトリクロルエチレン、テ
トラクロルエチレン、ブチルアルコ−ルからなるアゼオ
トロ−プ組成の溶剤を加えあわせてボ−ルミルにて十分
混合し、セラミック粉末を均一に分散させて作成する。
次いで、上記スラリ−を減圧下で撹拌、脱気して気泡分
を除去し、ドクタ−ブレイド型キャスチング装置を用い
て厚さ0.24mmにした後、所定寸法に切断してグリ
−ンシ−トを作製する。
First, a method of manufacturing each green sheet in FIG. 2 will be described. The slurry for the green sheet is 7
6 g of ceramic powder consisting of 2 wt% of mullite fine powder, 28 wt% of alumina, silica and magnesia fine powder of sintering aid, polyvinyl butyral organic binder and butylphthalyl butyl glycolate plasticizer 2 g was added, and a solvent having an azeotrope composition consisting of trichloroethylene, tetrachloroethylene, and butyl alcohol was added thereto, and the mixture was thoroughly mixed with a ball mill to uniformly disperse the ceramic powder.
Next, the slurry was agitated and deaerated under reduced pressure to remove air bubbles, and the thickness was adjusted to 0.24 mm using a doctor blade type casting device, followed by cutting into a predetermined size to obtain a green sheet. To make.

【0012】図2は上記グリ−ンシ−トを積層した焼成
前の基板の部分断面図である。内層部のグリ−ンシ−ト
83、84等の上下間の配線導通用の貫通孔は、超硬製
ピンを配置した打ち抜き金型を用いて穿孔する。同様
に、積層後基板裏面に露出するグリ−ンシ−トの入出力
用ピンの厚膜パタ−ンの貫通孔も金型を用いて穿孔す
る。次いで、上記内層部のグリ−ンシ−ト83、84等
の各貫通孔や配線パタ−ン部にタングステン導体ペ−ス
トを充填する。
FIG. 2 is a partial cross-sectional view of a substrate on which the green sheets are laminated and before firing. The upper and lower through holes for the wiring between the upper and lower green sheets 83, 84, etc. of the inner layer portion are punched using a punching die in which a cemented carbide pin is arranged. Similarly, the through holes of the thick film pattern of the input / output pins of the green sheet, which are exposed on the back surface of the substrate after the lamination, are also punched using a mold. Then, the through holes such as the green sheets 83 and 84 in the inner layer portion and the wiring pattern portion are filled with a tungsten conductor paste.

【0013】上記タングステン導体ペ−ストは次ぎのよ
うにしての作製する。内層部のグリ−ンシ−ト83、8
4内の配線パタ−ン用の導体ペ−スト(タングステンペ
−ストA)は、タングステン微粉末を80g、焼結助剤
としてガラス粉末を2g、エチルセルロ−スを3g、有
機溶剤としてジエチレングリコ−ルを15g加え合わ
せ、らいかい機および3本ロ−ルで混練した後、n−ブ
チルカルビト−ルアセテ−トを加えて粘度調製して作製
する。
The tungsten conductor paste is manufactured as follows. Green sheet 83, 8 on the inner layer
The conductor pattern (tungsten paste A) for the wiring pattern in 4 is 80 g of tungsten fine powder, 2 g of glass powder as a sintering aid, 3 g of ethyl cellulose, and diethylene glycol as an organic solvent. 15 g of the above ingredients are mixed and kneaded with a ladle mixer and three rolls, and then n-butyl carbitol acetate is added to adjust the viscosity.

【0014】同様に、上記貫通孔と積層後基板裏面に露
出するグリ−ンシ−トの入出力パタ−ン用の導体ペ−ス
ト(タングステンペ−ストB)を、粒度分布が異なるタ
ングステン微粉末を80g、焼結助剤としてガラス粉末
を4g、その他はタングステンペ−ストAと同様の方法
にて作製する。次いで、上記タングステンペ−ス−ト
A,Bを用い、スクリ−ン印刷法にて上記貫通孔にペ−
ストを充填し、表面に配線パタ−ンを形成する。
Similarly, the conductive paste (tungsten paste B) for the input / output pattern of the green sheet, which is exposed on the back surface of the substrate after the through holes and the stacked layers, is made of tungsten fine powder having a different particle size distribution. Of 80 g, a glass powder of 4 g as a sintering aid, and the others are manufactured by the same method as the tungsten paste A. Then, the tungsten pastes A and B are used to screen the through holes by a screen printing method.
Then, a wiring pattern is formed on the surface.

【0015】ここで、積層後基板裏面に露出するグリ−
ンシ−トの入出力用ピン用の貫通孔にはタングステンペ
−ス−トBを次ぎのようにして充填する。すなわち、上
記グリ−ンシ−トに貫通孔が無いグリ−ンシ−トを仮接
着した後、スクリ−ン印刷法により上記貫通孔により形
成される凹み部分にタングステンペ−ストBを充填す
る。次いで図2に示すように、上記各グリ−ンシ−トを
それぞれの配線パタ−ン間が電気的に接続されるように
して積み重ね、温度:130℃、圧力:100kg/c
2 でグリ−ンシ−トを互いに接着し一体化する。
Here, after the lamination, the grease exposed on the back surface of the substrate is formed.
Tungsten paste B is filled in the through holes for the input / output pins of the sheet as follows. That is, after the green sheet having no through holes is temporarily adhered to the green sheet, the concave portion formed by the through holes is filled with the tungsten paste B by the screen printing method. Then, as shown in FIG. 2, the green sheets are stacked so that the wiring patterns are electrically connected to each other, and the temperature is 130 ° C. and the pressure is 100 kg / c.
The green sheet is bonded and integrated with each other by m 2 .

【0016】上記図2の積層グリ−ンシ−ト体を焼成す
ると図3に示すような変形が発生する。貫通孔導体ペ−
ストの焼成収縮率がグリ−ンシ−トの焼成収縮率と同じ
であれば、焼成後の厚膜パタ−ンの厚みはグリ−ンシ−
ト一枚分と同じになる。また、上記導体ペ−ストの焼成
収縮率がグリ−ンシ−トより小さい場合は、貫通孔部分
が基板セラミック面より突き出し、焼成収縮率差が過大
だとクラックが発生する。
When the laminated green sheet body of FIG. 2 is fired, the deformation shown in FIG. 3 occurs. Through-hole conductor
If the firing shrinkage of the strike is the same as that of the green sheet, the thickness of the thick film pattern after firing is the green
It will be the same as one sheet. If the firing shrinkage of the conductor paste is smaller than the green sheet, the through-hole portion projects from the ceramic surface of the substrate, and if the firing shrinkage difference is too large, cracks occur.

【0017】またあ、導体ペ−ストの焼成収縮率がグリ
−ンシ−トより大きい場合には、貫通孔部分がセラミッ
ク基板面より凹み、焼成収縮率差が過大だとクラックや
隙間が発生する。また、厚膜パタ−ン部とセラミック部
の熱膨張率と等しくないと、クラックが発生したり、熱
膨張率差に基づく内部応力によって厚膜パタ−ン部の強
度が低下したりする。本発明では、上記のように導体ペ
−ストのビヒクル組成や割合、導体金属粒子の粒度、ガ
ラス成分やセラミック粉末の組成および添加量等を調節
して、厚膜パタ−ン部とグリ−ンシ−トの焼成収縮率や
熱膨張率等を等しくするようにしている。
If the firing shrinkage of the conductor paste is larger than the green sheet, the through-hole portion is recessed from the surface of the ceramic substrate, and if the firing shrinkage difference is too large, cracks or gaps occur. . If the coefficient of thermal expansion of the thick film pattern portion is not equal to that of the ceramic portion, cracks may occur or the strength of the thick film pattern portion may be reduced due to internal stress due to the difference in coefficient of thermal expansion. In the present invention, as described above, the vehicle composition and ratio of the conductor paste, the particle size of the conductor metal particles, the composition of the glass component and the ceramic powder and the addition amount are adjusted to adjust the thick film pattern portion and the green grease. -The firing shrinkage rate and the thermal expansion rate of the gut are made equal.

【0018】上記焼成は、上記積層グリ−ンシ−ト体を
台板上に置き、モリブデンを発熱体とする電気炉を用
い、窒素、水素、水蒸気の混合ガス雰囲気中で所定温度
にて作製する。なお、焼成後の大きさは200mm角、
一層分の厚みは、0.16mmであった。また、焼成後
の基板の反り、凹凸量等は60μmであった。次いで上
記焼成後の基板表面および裏面を、その平坦度が1μ
m、表面粗さが0.2μmとなるように図3に示す鎖線
Cレベルまで研磨する。研磨量は表面側が0.1mm、
裏面側が0.25mmである。次いで、基板裏面側にN
i/Auめっきをし、還元雰囲気中熱処理によりタング
ステンとNiを拡散させる。次いで図1に示すように、
基板表面に薄膜配線層1を形成し、基板裏面に入出力ピ
ン7をろう材で接続する。
The firing is performed at a predetermined temperature in a mixed gas atmosphere of nitrogen, hydrogen and water vapor using an electric furnace having the laminated green sheet body on a base plate and molybdenum as a heating element. . The size after firing is 200 mm square,
The thickness of one layer was 0.16 mm. In addition, the amount of warpage and unevenness of the substrate after firing was 60 μm. Then, the flatness of the front and back surfaces of the substrate after the above baking is 1 μm.
m, and the surface roughness is 0.2 μm, the surface is polished to the level of the chain line C shown in FIG. The polishing amount is 0.1 mm on the front side,
The back side is 0.25 mm. Next, N on the back side of the substrate
I / Au plating is performed, and tungsten and Ni are diffused by heat treatment in a reducing atmosphere. Then, as shown in FIG.
The thin film wiring layer 1 is formed on the front surface of the substrate, and the input / output pins 7 are connected to the back surface of the substrate with a brazing material.

【0019】〔比較例 1〕図4に示す従来のセラミッ
ク積層基板は上記本発明実施例1(図1)と同様の方法
で作製されているものの、厚膜パタ−ン導体金属3とそ
のグリ−ンシ−ト82が省略されている点が異なってい
る。基板の反り、凹凸量、一層当たりの厚み等は同じで
あったため、基板の表面と裏面側をそれぞれ0.1mm
研磨して同様の平坦度と表面粗さを得、表面に薄膜配線
層1を形成し、裏面には入出力ピン接続パタ−ンを形成
して入出力ピンをろう材で接続した。
COMPARATIVE EXAMPLE 1 The conventional ceramic laminated substrate shown in FIG. 4 is manufactured by the same method as in the first embodiment (FIG. 1) of the present invention, but the thick film pattern conductor metal 3 and its green are used. -The difference is that the sheet 82 is omitted. Since the warp, unevenness, thickness per layer, etc. of the substrate were the same, the front and back sides of the substrate were each 0.1 mm.
The same flatness and surface roughness were obtained by polishing, the thin film wiring layer 1 was formed on the front surface, and the input / output pin connection pattern was formed on the back surface to connect the input / output pins with a brazing material.

【0020】表1は引張強度試験機による上記実施例1
と比較例1の入出力ピン7の接続強度測定結果であり、
本発明により引張強度が略3倍に増加できることがわか
る。
Table 1 shows the above Example 1 by the tensile strength tester.
And the connection strength measurement result of the input / output pin 7 of Comparative Example 1,
It can be seen that the present invention can increase the tensile strength about three times.

【表1】 なお、上記研磨後の厚膜パタ−ンはその端部とセラミッ
ク部の界面での応力集中がないので、セラミック表面に
盛り上がった形状の厚膜パタ−ンの場合に較べて2〜3
割大きい接着強度が得られる。
[Table 1] Since the thick film pattern after polishing has no stress concentration at the interface between the end portion and the ceramic portion, the thickness of the thick film pattern is 2 to 3 compared to the case of the thick film pattern having a raised shape on the ceramic surface.
A relatively high adhesive strength can be obtained.

【0021】〔実施例 2〕図5はセラミック配線基板
裏面の厚膜パタ−ン導体金属31をはんだバンプを介し
て回路基板12に電気接続する本発明実施例の部分断面
図である。実施例2は実施例1に較べて、厚膜パタ−ン
導体金属31の密度をはんだバンプ11接続用に高めて
いる点と、基板表面に薄膜配層1の電気接続用の厚膜パ
タ−ン導体金属321および封止用厚膜パタ−ン導体金
属10を設けた点が異なっている。
[Embodiment 2] FIG. 5 is a partial sectional view of an embodiment of the present invention in which a thick film pattern conductor metal 31 on the back surface of a ceramic wiring board is electrically connected to a circuit board 12 via solder bumps. The second embodiment is higher than the first embodiment in that the density of the thick film pattern conductive metal 31 is increased for connecting the solder bumps 11, and the thick film pattern for electrical connection of the thin film layer 1 is formed on the substrate surface. The difference is that the conductive metal film 321 and the thick film pattern conductive metal film 10 for sealing are provided.

【0022】厚膜パタ−ン導体金属31の面積は比較的
小さてよいので、貫通孔導体金属(タングステンペ−ス
−トB)2はダミ−用のグリ−ンシ−トを仮接着せずに
スクリ−ン印刷法により充填することができる。封止用
厚膜パタ−ン導体金属10(タングステンペ−スト)は
実施例1と同様の方法で充填する。このセラミック配線
基板の表裏面を研磨してめっきを施し、熱処理後、基板
表面に薄膜配線層を形成し、基板表面をキャップ封止
し、裏面には接続用のはんだバンプを形成する。
Since the area of the thick film pattern conductive metal 31 may be relatively small, the through hole conductive metal (tungsten paste B) 2 is not temporarily bonded to the dummy green sheet. Can be filled by a screen printing method. The thick film pattern conductive metal 10 (tungsten paste) for sealing is filled in the same manner as in the first embodiment. The front and back surfaces of this ceramic wiring substrate are polished and plated, and after heat treatment, a thin film wiring layer is formed on the substrate surface, the substrate surface is capped, and solder bumps for connection are formed on the back surface.

【0023】〔比較例 2〕表2は引張強度試験機と剪
断強度試験機とによる上記実施例2と比較例2の封止部
分の引張強度およびはんだバンプの剪断強度の測定結果
であり、本発明により引張強度と剪断強度を略3倍に増
加できることがわかる。
[Comparative Example 2] Table 2 shows the measurement results of the tensile strength of the sealing portion and the shear strength of the solder bump in Example 2 and Comparative Example 2 by using the tensile strength tester and the shear strength tester. It is understood that the invention can increase the tensile strength and the shear strength by about three times.

【表2】 〔実施例 3〕本実施例では、セラミック配線基板の材
料をムライト系(実施例1)からアルミナ系に変えてい
る。
[Table 2] [Embodiment 3] In this embodiment, the material of the ceramic wiring board is changed from mullite type (Example 1) to alumina type.

【0024】セラミック粉末として、アルミナの微粉末
90wt%、焼結助剤としてコ−ジエライト組成となる
ようなタルクとクレイの混合粉末10wt%を用いた。
また、タングステンペ−ストには、実施例1とは粉度分
布が異なるタングステン微粉末を、またガラス粉末も組
成や添加料が異なるものを用いた。その他は実施例1と
同様の方法にて、基板を作製し、研磨、めっき・熱処
理、表面に薄膜形成をした後、裏面に入出力ピンをろう
材で接続した。
As the ceramic powder, 90% by weight of fine alumina powder and 10% by weight of mixed powder of talc and clay having a cordierite composition as a sintering aid were used.
As the tungsten paste, fine tungsten powder having a fineness distribution different from that in Example 1 was used, and glass powder having different composition and additives was used. Others were the same as in Example 1 except that a substrate was prepared, polished, plated and heat-treated, and a thin film was formed on the front surface, and then input / output pins were connected to the back surface with a brazing material.

【0025】〔比較例 3〕実施例3および比較例1と
同様に、研磨した基板表面に薄膜配線層を、基板裏面に
薄膜で入出力ピン接続パタ−ンを形成した入出力ピンを
ろう材で接続した。このように作製した基板の入出力ピ
ンの接続強度を引張試験機で測定した結果、実施例3は
比較例3の約3倍の接続強度であった。なお、はんだバ
ンプの剪断強度および封止部分の引張強度についても全
く同じ結果が得られた。
[Comparative Example 3] Similar to Example 3 and Comparative Example 1, a brazing filler metal was used for the I / O pins having the thin film wiring layer on the polished substrate surface and the I / O pin connecting pattern on the back surface of the substrate. I was connected with. As a result of measuring the connection strength of the input / output pins of the thus-prepared substrate with a tensile tester, the connection strength of Example 3 was about three times that of Comparative Example 3. The same results were obtained for the shear strength of the solder bump and the tensile strength of the sealing portion.

【0026】〔実施例 4〕セラミック配線基板のセラ
ミック材料を、アルミナフィラ−/ホウケイ酸ガラス
に、また導体材料を銅としたガラス配線基板を作製し、
研磨・薄膜形成した後、厚膜パタ−ン上および薄膜パタ
−ン上に、それぞれ入出力ピンの接続およびはんだバン
プの形成、キャップ封止を行い、入出力ピン引張強度お
よびはんだバンプ剪断強度、キャップ封止強度を調べ
た。その結果、前述と同様、厚膜パタ−ン上の引張強度
および剪断強度は、薄膜パタ−ン上の場合の約2.5〜
3倍の大きさであった。
Example 4 A glass wiring board was prepared in which the ceramic material of the ceramic wiring board was alumina filler / borosilicate glass, and the conductor material was copper.
After polishing and forming a thin film, I / O pin connection and solder bump formation and cap sealing are performed on the thick film pattern and thin film pattern, respectively, and the I / O pin tensile strength and solder bump shear strength are The cap sealing strength was examined. As a result, similar to the above, the tensile strength and the shear strength on the thick film pattern are about 2.5 to about 2.5 on the thin film pattern.
It was three times larger.

【0027】以上の実施例で述べたように、焼成した時
のセラミック配線基板において、基板表裏面となる厚膜
パタ−ンの厚みを裏面の研磨量以上にしておけば、上記
研磨後、基板表裏面の厚膜パタ−ンはそのまま残るの
で、これに入出力ピンを直接接続し、また、はんだバン
プの形成してそれぞれの接続強度を強めることができる
のである。また、同様にしてキャップを十分な封止強度
でとりつけることができる。また、本発明を他のセラミ
ック材料や導体材料を用いるグリ−ンシ−ト法によるセ
ラミック配線基板に適用して同様の効果を得ることがで
きる。
As described in the above embodiments, if the thickness of the thick film pattern on the front and back surfaces of the substrate in the ceramic wiring substrate after firing is set to be equal to or greater than the polishing amount of the back surface, the substrate after the polishing is finished. Since the thick film patterns on the front and back surfaces remain as they are, it is possible to directly connect the input / output pins to them and to form solder bumps to enhance the connection strength of each. Further, similarly, the cap can be attached with sufficient sealing strength. Further, the same effect can be obtained by applying the present invention to a ceramic wiring board by a green sheet method using another ceramic material or conductor material.

【0028】[0028]

【発明の効果】本発明により、セラミック多層配線基板
の表面に平坦な導体パタ−ン面を形成できるので、その
上に薄膜配線層を良好に設けることができ、さらに、入
出力ピン、はんだバンプ、封止キャップ等を密着性良く
接続してセラミック多層配線基板の信頼性を向上するこ
とができる。また、上記表層セラミックグリ−ンシ−ト
の貫通孔導体金属部の面積は内層部セラミックグリ−ン
シ−トの貫通孔導体金属部面積より大きいので、焼き縮
み等により表層部と内層部セラミックグリ−ンシ−トの
貫通孔導体金属の位置ずれを吸収して表層部と内層部間
の接続を確実にし、さらに、面積が大きいのでセラミッ
ク部に強固に固着して入出力ピン、はんだバンプ、封止
キャップ等の接続強度を高めることができる。
According to the present invention, since a flat conductor pattern surface can be formed on the surface of a ceramic multilayer wiring board, a thin film wiring layer can be satisfactorily provided on it, and further, input / output pins and solder bumps can be formed. The reliability of the ceramic multilayer wiring board can be improved by connecting the sealing cap and the like with good adhesion. Since the area of the through-hole conductor metal portion of the surface layer ceramic green sheet is larger than the through-hole conductor metal portion area of the inner layer portion ceramic green sheet, the surface layer portion and the inner layer portion ceramic green portion due to shrinkage or the like. Through-hole of the sheet absorbs the displacement of the conductor metal to ensure the connection between the surface layer and the inner layer, and because the area is large, it is firmly fixed to the ceramic part and the input / output pins, solder bumps, and sealing The connection strength of the cap or the like can be increased.

【図面の簡単な説明】[Brief description of drawings]

【表1】図1のセラミック配線基板と図4の従来基板の
入出力イピン接続強度比較表である。
1 is a comparison table of input / output pin connection strength between the ceramic wiring board of FIG. 1 and the conventional board of FIG.

【表2】図5のセラミック配線基板と従来基板の封止部
分引張強度とはんだバンプの剪断接続強度の比較表であ
る。
Table 2 is a comparison table of the sealing portion tensile strength and the solder bump shear connection strength of the ceramic wiring board of FIG. 5 and the conventional board.

【図1】本発明により表面に薄膜配線層を形成し、裏面
の厚膜パタ−ン上に入出力イピンを接続したセラミック
配線基板の部分断面図である。
FIG. 1 is a partial cross-sectional view of a ceramic wiring board according to the present invention in which a thin film wiring layer is formed on the front surface and input / output pins are connected on a thick film pattern on the back surface.

【図2】図1に用いる焼成前のセラミック配線基板の部
分断面図である。
FIG. 2 is a partial cross-sectional view of the ceramic wiring board before firing used in FIG.

【図3】図1に用いる焼成後のセラミック配線基板の部
分断面図である。
FIG. 3 is a partial cross-sectional view of the ceramic wiring board after firing used in FIG.

【図4】従来の表面に薄膜配線層を形成し、裏面の厚膜
パタ−ン上に入出力イピンを接続したセラミック配線基
板の部分断面図である。
FIG. 4 is a partial cross-sectional view of a conventional ceramic wiring substrate in which a thin film wiring layer is formed on the front surface and input / output pins are connected on a thick film pattern on the back surface.

【図5】本発明により表面に薄膜配線層と封止用厚膜パ
タ−ンを形成し、裏面の厚膜パタ−ン上にはんだバンプ
を形成したセラミック配線基板の部分断面図である。
FIG. 5 is a partial cross-sectional view of a ceramic wiring substrate having a thin film wiring layer and a thick film pattern for sealing formed on the front surface and solder bumps formed on the thick film pattern on the back surface according to the present invention.

【符号の説明】[Explanation of symbols]

1…薄膜配線層,2…貫通孔導体金属,3…厚膜パタ−
ン導体金属,4…セラミック部,5…めっき,6…ろう
材,7…入出力ピン,81…グリ−ンシ−ト,9…薄膜
パタ−ン,10…封止用厚膜パタ−ン導体金属,11…
はんだバンプ,12…回路基板,C…研磨面。
1 ... Thin film wiring layer, 2 ... Through-hole conductor metal, 3 ... Thick film pattern
Conductor metal, 4 ... Ceramic part, 5 ... Plating, 6 ... Brazing material, 7 ... Input / output pin, 81 ... Green sheet, 9 ... Thin film pattern, 10 ... Thick film pattern conductor for sealing Metal, 11 ...
Solder bumps, 12 ... Circuit board, C ... Polished surface.

フロントページの続き (72)発明者 槌田 誠一 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 高根 悦子 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内Front page continuation (72) Inventor Seiichi Mitsuda 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd.Institute of Industrial Science and Technology, Hitachi, Ltd. (72) Etsuko Takane 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd., Production Engineering Laboratory

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 セラミック多層配線基板において、上記
セラミック多層配線基板の表裏面に露出する導体パタ−
ン面をセラミック表面と同一平面にあるようにしたこと
を特徴とするセラミック多層配線基板。
1. In a ceramic multilayer wiring board, a conductor pattern exposed on the front and back surfaces of the ceramic multilayer wiring board.
A ceramic multilayer wiring board, characterized in that the inner surface is flush with the ceramic surface.
【請求項2】 請求項1において、上記セラミック多層
配線基板の表面及び/または裏面に薄膜配線層を形成し
たことを特徴とするセラミック配線基板。
2. The ceramic wiring board according to claim 1, wherein a thin film wiring layer is formed on a front surface and / or a back surface of the ceramic multilayer wiring board.
【請求項3】 請求項1において、上記セラミック多層
配線基板の表面裏面に露出する導体パタ−ン面に金属め
っき膜を設け、上記金属めっき膜上に入出力ピンの接
続、および/または、はんだバンプの形成、および/ま
たはキャップの封止を行なったことを特徴とするセラミ
ック配線基板。
3. The metal plating film according to claim 1, wherein a metal pattern film is provided on a conductor pattern surface exposed on a front surface and a back surface of the ceramic multilayer wiring board, and input / output pins are connected and / or solder is provided on the metal plating film. A ceramic wiring board having bumps formed and / or caps sealed.
【請求項4】 セラミック多層配線基板の製造方法にお
いて、所定の貫通孔に導体金属を充填した所定数のセラ
ミックグリ−ンシ−トを積層し、セラミックグリ−ンシ
−ト体の少なくとも片面に上記貫通孔より大きな面積の
貫通孔に導体金属を充填した表層用のセラミックグリ−
ンシ−トを積層して焼成し、次いで上記表層用セラミッ
クグリ−ンシ−トの表面を平坦に研磨するようにしたこ
とを特徴とするセラミック多層配線基板の製造方法。
4. A method for manufacturing a ceramic multilayer wiring board, wherein a predetermined number of ceramic green sheets filled with a conductive metal are laminated in predetermined through holes, and the through holes are formed on at least one surface of the ceramic green sheet body. Ceramic layer for surface layer in which conductive metal is filled in through-hole with larger area than hole
A method for manufacturing a ceramic multi-layer wiring board, characterized in that the sheets are laminated and fired, and then the surface of the ceramic green sheet for surface layer is polished flat.
【請求項5】 請求項4において、上記表層用セラミッ
クグリ−ンシ−トの上に、さらにセラミックグリ−ンシ
−トを積層して焼成し、次いで上記焼成後のセラミック
グリ−ンシ−ト体の表面を平坦に研磨して上記表層用セ
ラミックグリ−ンシ−トの貫通孔導体金属面を露出する
ようにしたことを特徴とするセラミック多層配線基板の
製造方法。
5. The ceramic green sheet according to claim 4, wherein a ceramic green sheet is further laminated on the surface green ceramic sheet and fired, and then the fired ceramic green sheet body is obtained. A method for manufacturing a ceramic multilayer wiring board, wherein the surface is polished flat to expose the through-hole conductor metal surface of the surface ceramic green sheet.
【請求項6】 請求項4または5において、上記表層用
セラミックグリ−ンシ−トの貫通孔導体金属面を金属め
っきして入出力ピン、および/または、はんだバンプ、
および/または封止キャップ、および/または薄膜配線
層等を接続するようにしたことを特徴とするセラミック
多層配線基板の製造方法。
6. The input / output pin and / or the solder bump according to claim 4, wherein the through hole conductor metal surface of the surface layer ceramic green sheet is metal-plated.
And / or a sealing cap, and / or a thin film wiring layer and the like are connected to the ceramic multilayer wiring board.
JP4170595A 1992-06-29 1992-06-29 Ceramic multilayer wiring board and manufacture thereof Pending JPH0613755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4170595A JPH0613755A (en) 1992-06-29 1992-06-29 Ceramic multilayer wiring board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4170595A JPH0613755A (en) 1992-06-29 1992-06-29 Ceramic multilayer wiring board and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0613755A true JPH0613755A (en) 1994-01-21

Family

ID=15907756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4170595A Pending JPH0613755A (en) 1992-06-29 1992-06-29 Ceramic multilayer wiring board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0613755A (en)

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WO2003101166A1 (en) * 2002-05-28 2003-12-04 Sumitomo Electric Industries, Ltd. Aluminum nitride sintered compact having metallized layer and method for preparation thereof
JP2005109462A (en) * 2003-09-09 2005-04-21 Ngk Spark Plug Co Ltd Manufacturing method of ceramic substrate, and the ceramic substrate
US7564131B2 (en) * 2002-06-07 2009-07-21 Lg Electronics Inc. Semiconductor package and method of making a semiconductor package
US20120205148A1 (en) * 2009-10-23 2012-08-16 Fujikura Ltd. Device packaging structure and device packaging method
JP2012178611A (en) * 2009-10-23 2012-09-13 Fujikura Ltd Method for manufacturing device mounting structure
JP2013232610A (en) * 2012-04-06 2013-11-14 Nichia Chem Ind Ltd Semiconductor device
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054652A (en) * 1997-04-18 2000-04-25 Fujitsu Limited Thin-film multi-layer substrate and electronic device
WO2003101166A1 (en) * 2002-05-28 2003-12-04 Sumitomo Electric Industries, Ltd. Aluminum nitride sintered compact having metallized layer and method for preparation thereof
US7564131B2 (en) * 2002-06-07 2009-07-21 Lg Electronics Inc. Semiconductor package and method of making a semiconductor package
JP2005109462A (en) * 2003-09-09 2005-04-21 Ngk Spark Plug Co Ltd Manufacturing method of ceramic substrate, and the ceramic substrate
JP4497533B2 (en) * 2003-09-09 2010-07-07 日本特殊陶業株式会社 Manufacturing method of ceramic substrate
US20120205148A1 (en) * 2009-10-23 2012-08-16 Fujikura Ltd. Device packaging structure and device packaging method
JP2012178611A (en) * 2009-10-23 2012-09-13 Fujikura Ltd Method for manufacturing device mounting structure
JP2013232610A (en) * 2012-04-06 2013-11-14 Nichia Chem Ind Ltd Semiconductor device
JP2019071420A (en) * 2013-08-26 2019-05-09 日立金属株式会社 Wafer for mounting substrate, multilayer ceramics substrate, mounting substrate, chip module and method for manufacturing the wafer for mounting substrate

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