JP3241945B2 - Glass ceramic multilayer circuit board and method of manufacturing the same - Google Patents

Glass ceramic multilayer circuit board and method of manufacturing the same

Info

Publication number
JP3241945B2
JP3241945B2 JP23909994A JP23909994A JP3241945B2 JP 3241945 B2 JP3241945 B2 JP 3241945B2 JP 23909994 A JP23909994 A JP 23909994A JP 23909994 A JP23909994 A JP 23909994A JP 3241945 B2 JP3241945 B2 JP 3241945B2
Authority
JP
Japan
Prior art keywords
copper
multilayer circuit
circuit board
glass
ceramic multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23909994A
Other languages
Japanese (ja)
Other versions
JPH08107277A (en
Inventor
正英 岡本
昭一 岩永
昌作 石原
信之 牛房
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23909994A priority Critical patent/JP3241945B2/en
Publication of JPH08107277A publication Critical patent/JPH08107277A/en
Application granted granted Critical
Publication of JP3241945B2 publication Critical patent/JP3241945B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、セラミック配線基板、
特に半導体部品を取り付けたり、電気信号の入出力のた
めのピンを取り付けて機能モジュールを構成するのに好
適なガラスセラミック多層回路基板およびその製造方法
に関するものである。
The present invention relates to a ceramic wiring board,
In particular, the present invention relates to a glass ceramic multilayer circuit board suitable for mounting a semiconductor component or mounting a pin for inputting / outputting an electric signal to form a functional module, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】周知のように、ガラスセラミック多層回
路基板は、低電気抵抗特性を有する銅(あるいは銅を主
成分とする合金)導体部と、銅の融点以下で焼結可能な
ガラスを主成分とする絶縁体部とからなっている。ガラ
スセラミック多層回路基板は、ガラスセラミック多層回
路基板に取り付けるLSI素子とガラスセラミック多層
回路基板との接続の信頼性を高めるために、ガラスセラ
ミック多層回路基板の熱膨張係数を、LSI素子の材料
であるシリコン(Si)の熱膨張係数(3.5×10~6
℃)に近似させてあるが、ガラスセラミック多層回路基
板は絶縁体部と高熱膨張の銅導体部とからなる複合体で
あるため、絶縁体部の熱膨張係数はガラスセラミック多
層回路基板の熱膨張係数より低く、通常3.0×10~6
/℃程度となっている。しかし、銅の熱膨張係数は1
6.5×10~6/℃とガラスセラミックスの5倍以上も
大きいため、このような銅とガラスセラミックスとの大
きな熱膨張差により、同時焼成後の冷却過程で銅の方が
大きく熱収縮し、銅導体部と絶縁体部の界面で絶縁体部
に引張り応力が働き、その結果、絶縁体部にクラックが
発生してしまう。
2. Description of the Related Art As is well known, a glass-ceramic multilayer circuit board mainly comprises a copper (or an alloy containing copper as a main component) conductor having low electric resistance characteristics and a glass which can be sintered at a temperature equal to or lower than the melting point of copper. And an insulator part as a component. The glass-ceramic multilayer circuit board is a material of the LSI element in which the thermal expansion coefficient of the glass-ceramic multilayer circuit board is increased in order to increase the reliability of connection between the LSI element mounted on the glass-ceramic multilayer circuit board and the glass ceramic multilayer circuit board. Thermal expansion coefficient of silicon (Si) (3.5 × 10 ~ 6 /
° C), but because the glass ceramic multilayer circuit board is a composite consisting of an insulator and a copper conductor with high thermal expansion, the thermal expansion coefficient of the insulator is the thermal expansion coefficient of the glass ceramic multilayer circuit board. lower than the coefficient, usually 3.0 × 10 ~ 6
/ ° C. However, the coefficient of thermal expansion of copper is 1
Since 6.5 × 10 6 / ° C., which is more than 5 times larger than that of glass ceramics, due to such a large difference in thermal expansion between copper and glass ceramics, copper undergoes a large thermal contraction in the cooling process after simultaneous firing. At the interface between the copper conductor and the insulator, a tensile stress acts on the insulator, and as a result, cracks occur in the insulator.

【0003】このようなクラック発生の問題を解決する
ための技術として、銅導体部の導体金属の嵩密度に対す
る気孔率を15%以上40%以下とする技術が特開平5
−174613号公報に開示されている。また、銅導体
部と絶縁体部の少なくとも一部がポリマー材料浸透可能
であり、この浸透可能な部分にポリマー材料を含浸させ
ることにより、焼成後の溶剤浸透などによる特性劣化の
問題を解決する技術が特公平5−63106号公報に開
示されている。また、銅導体部を形成する材料に、絶縁
体部を構成する材料と同一材料を含有させて銅導体部と
絶縁体部を焼成することにより、クラック発生の問題を
解決する技術が特公平4−20280号公報に開示され
ている。
As a technique for solving such a problem of the occurrence of cracks, a technique in which the porosity of the copper conductor portion with respect to the bulk density of the conductor metal is set to 15% or more and 40% or less is disclosed in Japanese Patent Application Laid-Open No. Hei 5 (1993) -205.
No. 174613. Also, at least a part of the copper conductor portion and the insulator portion is capable of permeating a polymer material, and by impregnating the permeable portion with the polymer material, a technique for solving the problem of characteristic deterioration due to solvent permeation after firing and the like. Is disclosed in Japanese Patent Publication No. 5-63106. Also, a technique for solving the problem of crack generation by firing the copper conductor portion and the insulator portion by including the same material as the material constituting the insulator portion in the material forming the copper conductor portion has been disclosed in Japanese Patent Application Publication No. Hei. No. -20280.

【0004】[0004]

【発明が解決しようとする課題】銅導体部を使用し、ガ
ラスセラミックスの絶縁体部との組合せで同時焼結した
基板を製造すると絶縁体部にクラックが発生するという
問題がある。問題を解決するための技術が開示されてい
るが、クラック発生を解決する本質的な解決策となって
おらず、また、銅本来の低電気抵抗という特性を充分に
生かした基板を製造することができていない。本発明
は、前記の従来技術の各欠点を改良し、熱膨張係数がシ
リコンの熱膨張係数に近似し、銅の融点以下の温度で焼
結可能なガラスを主成分とする絶縁体部と、銅を主成分
とする導体部とからなり、銅を主成分とする導体部近傍
の絶縁体部にクラックが発生せず、銅を主成分とする導
体部の固有抵抗が銅本来の固有抵抗に近いガラスセラミ
ック多層回路基板を提供することを目的とする。本発明
の他の目的は、前記の従来技術の各欠点を改良し、銅を
主成分とする導体部近傍の絶縁体部にクラックの発生が
なく、かつ、銅を主成分とする導体部の固有抵抗が銅本
来の固有抵抗に近いガラスセラミック多層回路基板の製
造方法、さらに、ガラスセラミック多層回路基板の銅を
主成分とする導体部を形成する銅ペースト組成物および
ガラスセラミック多層回路基板からなる半導体実装装置
を提供することにある。
When a substrate is manufactured by using a copper conductor and co-sintering a glass ceramic in combination with an insulator, there is a problem that cracks occur in the insulator. Although a technique for solving the problem is disclosed, it is not an essential solution for solving the occurrence of cracks, and it is necessary to manufacture a substrate that fully utilizes the characteristic of copper's inherent low electric resistance. Not done. The present invention improves on each of the disadvantages of the prior art described above, the thermal expansion coefficient is close to the thermal expansion coefficient of silicon, an insulator portion mainly composed of glass that can be sintered at a temperature equal to or lower than the melting point of copper, Consisting of a conductor part mainly composed of copper, cracks do not occur in the insulator part near the conductor part mainly composed of copper, and the specific resistance of the conductor part mainly composed of copper becomes the intrinsic resistance of copper. It is an object of the present invention to provide a near glass ceramic multilayer circuit board. Another object of the present invention is to improve the drawbacks of the above-mentioned prior art, to prevent the occurrence of cracks in the insulator portion near the conductor portion containing copper as a main component, and to provide a conductor portion containing copper as a main component. A method of manufacturing a glass ceramic multilayer circuit board having a specific resistance close to the intrinsic resistance of copper, further comprising a copper paste composition and a glass ceramic multilayer circuit board for forming a conductor portion containing copper as a main component of the glass ceramic multilayer circuit board It is to provide a semiconductor mounting device.

【0005】[0005]

【課題を解決するための手段】前記目的を達成するため
に、本発明のガラスセラミック多層回路基板は、銅を主
成分とする導体部と、銅の融点以下の温度で焼結可能な
ガラスを主成分とし、シリコンの熱膨張係数に近似した
熱膨張係数を有する絶縁体部とからなり、前記銅を主成
分とする導体部が体積割合で10%以下であるガラスセ
ラミック多層回路基板において、前記銅を主成分とする
導体部は、銅に無機粉末を添加して焼結し、固有抵抗が
3.5μΩ・cm以下であり、前記銅を主成分とする導
体部近傍の前記絶縁体部にクラックが発生しないように
したものである。
In order to achieve the above object, a glass ceramic multilayer circuit board according to the present invention comprises a conductor having copper as a main component and a glass which can be sintered at a temperature lower than the melting point of copper. A glass-ceramic multilayer circuit board comprising, as a main component, an insulator portion having a thermal expansion coefficient close to the thermal expansion coefficient of silicon, wherein the conductor portion containing copper as a main component is 10% or less by volume. The conductor portion containing copper as a main component is sintered by adding an inorganic powder to copper, and has a specific resistance of 3.5 μΩ · cm or less. Cracks do not occur.

【0006】また、本発明のガラスセラミック多層回路
基板は、銅を主成分とする導体部と、銅の融点以下の温
度で焼結可能なガラスを主成分とし、シリコンの熱膨張
係数に近似した熱膨張係数を有する絶縁体部とからな
り、前記銅を主成分とする導体部が体積割合で10%以
下であるガラスセラミック多層回路基板において、前記
銅を主成分とする導体部は、銅に無機粉末を添加して焼
結し、前記銅を主成分とする導体部と同一組成の材料を
同一焼成条件で焼結した圧粉焼結体の熱膨張係数α[×
10~6/℃]とヤング率E[MPa]の関係が の範囲であり、前記銅を主成分とする導体部近傍の前記
絶縁体部にクラックが発生しないようにしたものであ
る。
Further, the glass ceramic multilayer circuit board of the present invention has a conductor portion mainly composed of copper and a glass mainly sinterable at a temperature equal to or lower than the melting point of copper, and has a thermal expansion coefficient close to that of silicon. In a glass-ceramic multilayer circuit board comprising an insulator part having a coefficient of thermal expansion, and the conductor part containing copper as a main component is 10% or less by volume, the conductor part containing copper as a main component is made of copper. A thermal expansion coefficient α [× of a sintered compact obtained by adding an inorganic powder, sintering, and sintering a material having the same composition as that of the conductor containing copper as a main component under the same firing conditions.
10 ~ 6 / ℃] and the relationship between the Young's modulus E [MPa] is And cracks are not generated in the insulator portion near the conductor portion containing copper as a main component.

【0007】また、本発明のガラスセラミック多層回路
基板は、銅を主成分とする導体部と、銅の融点以下の温
度で焼結可能なガラスを主成分とし、シリコンの熱膨張
係数に近似した熱膨張係数を有する絶縁体部とからな
り、前記銅を主成分とする導体部が体積割合で10%以
下であるガラスセラミック多層回路基板において、前記
銅を主成分とする導体部は、銅に無機粉末を添加して焼
結し、前記銅を主成分とする導体部と同一組成の材料を
同一焼成条件で焼結した圧粉焼結体の熱膨張係数α[×
10~6/℃]とヤング率E[MPa]の関係が の範囲であり、前記銅を主成分とする導体部近傍の前記
絶縁体部にクラックが発生しないようにしたものであ
る。
Further, the glass-ceramic multilayer circuit board of the present invention has a conductor portion containing copper as a main component and a glass component sinterable at a temperature lower than the melting point of copper as a main component, and has a coefficient of thermal expansion close to that of silicon. In a glass-ceramic multilayer circuit board comprising an insulator part having a coefficient of thermal expansion, and the conductor part containing copper as a main component is 10% or less by volume, the conductor part containing copper as a main component is made of copper. A thermal expansion coefficient α [× of a sintered compact obtained by adding an inorganic powder, sintering, and sintering a material having the same composition as that of the conductor containing copper as a main component under the same firing conditions.
10 ~ 6 / ℃] and the relationship between the Young's modulus E [MPa] is And cracks are not generated in the insulator portion near the conductor portion containing copper as a main component.

【0008】さらに詳しくは、本発明のガラスセラミッ
ク多層回路基板は、絶縁体部の主成分が、ホウケイ酸ガ
ラスあるいはコージェライトあるいは2Al23・B2
3あるいはAl23・B23からなるものである。ま
た、本発明のガラスセラミック多層回路基板に使用する
銅ペーストは、無機粉末を配合した銅ペースト組成物に
おいて、前記無機粉末中の銅粉末の体積割合が92%以
上のものである。また、本発明の半導体実装装置は、本
発明のガラスセラミック多層回路基板の上面に、半導体
素子をはんだ付けにより装着したものである。また、本
発明の半導体実装装置は、本発明のガラスセラミック多
層回路基板の上面に、該ガラスセラミック多層回路基板
と同一材質のキャリア基板を介して半導体素子をはんだ
付けにより装着し、前記半導体素子と前記キャリア基板
との接続部分を樹脂等により封止したものである。
More specifically, in the glass ceramic multilayer circuit board of the present invention, the main component of the insulator portion is borosilicate glass, cordierite, or 2Al 2 O 3 .B 2
O 3 or is made of Al 2 O 3 · B 2 O 3. The copper paste used for the glass ceramic multilayer circuit board of the present invention is a copper paste composition containing an inorganic powder, wherein the volume ratio of the copper powder in the inorganic powder is 92% or more. Further, the semiconductor mounting device of the present invention has a semiconductor element mounted on the upper surface of the glass ceramic multilayer circuit board of the present invention by soldering. Further, the semiconductor mounting device of the present invention, the semiconductor element is mounted on the upper surface of the glass ceramic multilayer circuit board of the present invention by soldering via a carrier substrate of the same material as the glass ceramic multilayer circuit board, and the semiconductor element and The connection portion with the carrier substrate is sealed with a resin or the like.

【0009】また、本発明の半導体実装装置は、本発明
のガラスセラミック多層回路基板の上面に、該ガラスセ
ラミック多層回路基板と同一材質のキャリア基板を介し
て半導体素子をはんだ付けにより装着し、前記半導体素
子にキャップを被せ、該キャップを前記キャリア基板上
面端部と前記半導体素子上面とではんだ付けし、前記半
導体素子を前記キャップ内に封止したものである。ま
た、本発明のガラスセラミック多層回路基板の製造方法
は、ガラスセラミック原料粉末とバインダと他の助剤か
らグリーンシートを製造し、該グリーンシートに所要の
穴あけ後、無機粉末を配合し前記無機粉末中の銅粉末の
体積割合が92%以上である本発明の銅ペースト組成物
を穴埋め印刷およびパターン印刷し、銅ペースト組成物
を印刷したグリーンシートを位置合わせして複数枚積層
圧着し、焼成するものである。
Further, in the semiconductor mounting apparatus according to the present invention, the semiconductor element is mounted on the upper surface of the glass ceramic multilayer circuit board of the present invention by soldering via a carrier substrate made of the same material as the glass ceramic multilayer circuit board. The semiconductor element is covered with a cap, and the cap is soldered to the upper end of the carrier substrate and the upper surface of the semiconductor element to seal the semiconductor element in the cap. The method for producing a glass-ceramic multilayer circuit board of the present invention comprises producing a green sheet from a glass-ceramic raw material powder, a binder and other auxiliaries, forming a required hole in the green sheet, blending an inorganic powder with the inorganic powder, The copper paste composition of the present invention in which the volume ratio of the copper powder in the paste is 92% or more is filled and printed, a plurality of green sheets on which the copper paste composition is printed are aligned, laminated and pressed, and fired. Things.

【0010】[0010]

【作用】本発明のガラスセラミック多層回路基板は、銅
を主成分とする導体部と、銅の融点以下の温度で焼結可
能なガラスを主成分とし、シリコンの熱膨張係数に近似
した熱膨張係数を有する絶縁体部とからなり、前記銅を
主成分とする導体部が体積割合で10%以下であるガラ
スセラミック多層回路基板であって、前記銅を主成分と
する導体部は、銅に無機粉末を添加して焼結し、固有抵
抗が3.5μΩ・cm以下であり、前記銅を主成分とす
る導体部近傍の前記絶縁体部にクラックが発生しない。
The glass-ceramic multilayer circuit board of the present invention has a conductor portion mainly composed of copper, and a glass mainly sinterable at a temperature equal to or lower than the melting point of copper. A glass-ceramic multilayer circuit board comprising an insulator portion having a coefficient, and wherein the conductor portion containing copper as a main component is 10% or less by volume, wherein the conductor portion containing copper as a main component is formed of copper. Sintering is performed by adding an inorganic powder, the specific resistance is 3.5 μΩ · cm or less, and no crack is generated in the insulator near the conductor containing copper as a main component.

【0011】また、本発明のガラスセラミック多層回路
基板は、銅を主成分とする導体部と、銅の融点以下の温
度で焼結可能なガラスを主成分とし、シリコンの熱膨張
係数に近似した熱膨張係数を有する絶縁体部とからな
り、前記銅を主成分とする導体部が体積割合で10%以
下であるガラスセラミック多層回路基板であって、前記
銅を主成分とする導体部は、銅に無機粉末を添加して焼
結し、前記銅を主成分とする導体部と同一組成の材料を
同一焼成条件で焼結した圧粉焼結体の熱膨張係数α[×
10~6/℃]とヤング率E[MPa]の関係が の範囲であり、前記銅を主成分とする導体部近傍の前記
絶縁体部にクラックが発生しない。
Further, the glass-ceramic multilayer circuit board of the present invention has a conductor portion containing copper as a main component and a glass component sinterable at a temperature lower than the melting point of copper as a main component, and has a thermal expansion coefficient close to that of silicon. A glass ceramic multilayer circuit board comprising an insulator portion having a coefficient of thermal expansion, wherein the conductor portion containing copper as a main component is 10% or less by volume, and the conductor portion containing copper as a main component is: An inorganic powder is added to copper and sintered, and a material having the same composition as that of the conductor part containing copper as a main component is sintered under the same firing conditions.
10 ~ 6 / ℃] and the relationship between the Young's modulus E [MPa] is And no crack occurs in the insulator portion near the conductor portion containing copper as a main component.

【0012】また、本発明のガラスセラミック多層回路
基板は、銅を主成分とする導体部と、銅の融点以下の温
度で焼結可能なガラスを主成分とし、シリコンの熱膨張
係数に近似した熱膨張係数を有する絶縁体部とからな
り、前記銅を主成分とする導体部が体積割合で10%以
下であるガラスセラミック多層回路基板であって、前記
銅を主成分とする導体部は、銅に無機粉末を添加して焼
結し、前記銅を主成分とする導体部と同一組成の材料を
同一焼成条件で焼結した圧粉焼結体の熱膨張係数α[×
10~6/℃]とヤング率E[MPa]の関係が の範囲であり、前記銅を主成分とする導体部近傍の前記
絶縁体部にクラックが発生しない。
Further, the glass-ceramic multilayer circuit board of the present invention has a conductor portion containing copper as a main component and a glass component sinterable at a temperature lower than the melting point of copper as a main component, and has a coefficient of thermal expansion close to that of silicon. A glass ceramic multilayer circuit board comprising an insulator portion having a coefficient of thermal expansion, wherein the conductor portion containing copper as a main component is 10% or less by volume, and the conductor portion containing copper as a main component is: An inorganic powder is added to copper and sintered, and a material having the same composition as that of the conductor part containing copper as a main component is sintered under the same firing conditions.
10 ~ 6 / ℃] and the relationship between the Young's modulus E [MPa] is And no crack occurs in the insulator portion near the conductor portion containing copper as a main component.

【0013】また、本発明の半導体実装装置は、本発明
のガラスセラミック多層回路基板の上面に、半導体素子
をはんだ付けにより装着する。また、本発明の半導体実
装装置は、本発明のガラスセラミック多層回路基板の上
面に、該ガラスセラミック多層回路基板と同一材質のキ
ャリア基板を介して半導体素子をはんだ付けにより装着
し、前記半導体素子と前記キャリア基板との接続部分を
樹脂等により封止する。また、本発明の半導体実装装置
は、本発明のガラスセラミック多層回路基板の上面に、
該ガラスセラミック多層回路基板と同一材質のキャリア
基板を介して半導体素子をはんだ付けにより装着し、前
記半導体素子にキャップを被せ、該キャップを前記キャ
リア基板上面端部と前記半導体素子上面とではんだ付け
し、前記半導体素子を前記キャップ内に封止する。ま
た、本発明のガラスセラミック多層回路基板の製造方法
は、ガラスセラミック原料粉末とバインダと他の助剤か
らグリーンシートを製造し、該グリーンシートに所要の
穴あけ後、無機粉末を配合し前記無機粉末中の銅粉末の
体積割合が92%以上である本発明の銅ペースト組成物
を穴埋め印刷およびパターン印刷し、銅ペースト組成物
を印刷したグリーンシートを位置合わせして複数枚積層
圧着し、焼成する。
Further, in the semiconductor mounting apparatus of the present invention, a semiconductor element is mounted on the upper surface of the glass ceramic multilayer circuit board of the present invention by soldering. Further, the semiconductor mounting device of the present invention, the semiconductor element is mounted on the upper surface of the glass ceramic multilayer circuit board of the present invention by soldering via a carrier substrate of the same material as the glass ceramic multilayer circuit board, and the semiconductor element and A connection portion with the carrier substrate is sealed with a resin or the like. Further, the semiconductor mounting device of the present invention, on the upper surface of the glass ceramic multilayer circuit board of the present invention,
A semiconductor element is mounted by soldering via a carrier substrate of the same material as the glass ceramic multilayer circuit board, a cap is placed on the semiconductor element, and the cap is soldered at an end of the upper surface of the carrier substrate and the upper surface of the semiconductor element. Then, the semiconductor element is sealed in the cap. The method for producing a glass-ceramic multilayer circuit board of the present invention comprises producing a green sheet from a glass-ceramic raw material powder, a binder and other auxiliaries, forming a required hole in the green sheet, blending an inorganic powder with the inorganic powder, The copper paste composition of the present invention in which the volume ratio of the copper powder in the paste is 92% or more is filled and printed, a plurality of green sheets on which the copper paste composition is printed are aligned, laminated and pressed, and fired. .

【0014】[0014]

【実施例】実施例の説明に入るまえに、本発明にかかる
基本事項を説明する。ガラスセラミック多層回路基板に
おいて、銅導体部と絶縁体部の界面で、絶縁体部に働く
引張り応力の一例として、最も応力の集中するスルーホ
ール界面における応力を、組み合わせ円筒モデルから算
出する式は下記(1)式のように表わされる。 但し、P:スルーホール界面で絶縁体部に働く引張り応
力[MPa]、T:応力発生温度領域[℃]、b:スル
ーホールピッチ/2[μm]、c:スルーホール径/2
[μm]、α:熱膨張係数[×10~6/℃]、E:ヤン
グ率[MPa]、γ:ポアソン比[−]、添字 1:銅導
体部、添字 2:絶縁体部。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments, the basic items according to the present invention will be described. In the glass ceramic multilayer circuit board, at the interface between the copper conductor and the insulator, as an example of the tensile stress acting on the insulator, the equation for calculating the stress at the through-hole interface where the stress is most concentrated from the combined cylindrical model is as follows: It is expressed as in equation (1). Here, P: tensile stress [MPa] acting on the insulator at the through-hole interface, T: stress generation temperature region [° C.], b: through-hole pitch / 2 [μm], c: through-hole diameter / 2
[Μm], α: coefficient of thermal expansion [× 10 6 / ° C.], E: Young's modulus [MPa], γ: Poisson's ratio [−], subscript 1 : copper conductor portion, subscript 2 : insulator portion.

【0015】熱膨張係数がSiの熱膨張係数に近似して
おり、銅の融点以下の温度で焼結可能なガラスの代表例
としては、ホウケイ酸ガラス、コージェライト析出型結
晶化ガラス、2Al23・B23あるいはAl23・B
23析出型結晶化ガラスなどがある。前記ガラスを主成
分とした絶縁体部の物性値には何れも大きな差はなく、
熱膨張係数α2 =3.0×10~6/℃、ポアソン比γ2
=0.25、ヤング率E2 =1.2×105 MPaであ
る。また、銅導体部のポアソン比は、銅を主成分として
いる限り、大きな違いはなく、γ1 =0.30である。
また、ガラスセラミック多層回路基板は、ガラスセラミ
ック多層回路基板中に占める銅導体部の割合が大きいほ
ど、銅導体部近傍の絶縁体部にクラックが発生しやすい
が、一般にセラミック多層回路基板中の導体部の体積割
合は最大でも10%程度であり、この最大の場合をスル
ーホールの径とピッチにあてはめると、例えばスルーホ
ール径160μm、スルーホール・ピッチ450μmと
なる。
Representative examples of glasses whose thermal expansion coefficient is close to that of Si and which can be sintered at a temperature equal to or lower than the melting point of copper include borosilicate glass, cordierite-precipitated crystallized glass, and 2Al 2. O 3 · B 2 O 3 or Al 2 O 3 · B
There is a 2 O 3 precipitation type crystallized glass. There is no significant difference in the physical property values of the insulator portion containing glass as a main component,
Thermal expansion coefficient α 2 = 3.0 × 10 6 / ° C, Poisson's ratio γ 2
= 0.25 and Young's modulus E 2 = 1.2 × 10 5 MPa. The Poisson's ratio of the copper conductor portion is not so different as long as copper is the main component, and γ 1 = 0.30.
In the glass ceramic multilayer circuit board, as the proportion of the copper conductor portion in the glass ceramic multilayer circuit board increases, cracks are more likely to occur in the insulator portion near the copper conductor portion. The volume ratio of the portion is at most about 10%, and when this maximum case is applied to the diameter and pitch of the through hole, for example, the through hole diameter is 160 μm and the through hole pitch is 450 μm.

【0016】応力発生温度領域は、焼成後の冷却過程で
ガラスが固まる温度すなわち軟化温度がT=820℃で
あり、これも前記のガラスの種類によらずほぼ一定であ
る。スルーホール界面で絶縁体部に働く引張り応力P
が、前記のホウケイ酸ガラス、コージェライト析出型結
晶化ガラス、2Al23・B23あるいはAl23・B
23析出型結晶化ガラスなどを主成分とした絶縁体部材
料の一般的な強度200MPaを超えると、絶縁体部に
クラックが生じる。これらの数値を上記(1)式に代入
して、スルーホール界面で絶縁体部に働く引張り応力が
P<200MPaとなるための、銅導体部の熱膨張係数
α1 とヤング率E1の関係を求めると下記(2)式のよ
うになる。
In the stress generation temperature range, the temperature at which the glass solidifies during the cooling process after firing, that is, the softening temperature is T = 820 ° C., and this is also substantially constant regardless of the type of the glass. Tensile stress P acting on insulator at the interface of through hole
Are borosilicate glass, cordierite-precipitated crystallized glass, 2Al 2 O 3 .B 2 O 3 or Al 2 O 3 .B
When the general strength of the insulator portion material mainly containing 2 O 3 precipitation-type crystallized glass or the like exceeds 200 MPa, cracks occur in the insulator portion. By substituting these numerical values into the above equation (1), the relationship between the thermal expansion coefficient α 1 of the copper conductor and the Young's modulus E 1 for the tensile stress acting on the insulator at the through-hole interface to be P <200 MPa. Is obtained as in the following equation (2).

【0017】前記(2)式を図示したものが、図2であ
る。ガラスセラミック多層回路基板の銅導体部の熱膨張
係数α1とヤング率E1は、前記銅導体部と同一組成の材
料を同一焼成条件で焼結した圧粉焼結体の熱膨張係数α
とヤング率Eとそれぞれ等しいと考えることができる。
したがって、熱膨張係数がSiの熱膨張係数に近似し、
銅の融点以下の温度で焼結可能なガラスを主成分とする
絶縁体部と銅を主成分とする導体部とからなり、前記銅
を主成分とする導体部が体積割合で10%以下のガラス
セラミック多層回路基板において、銅を主成分とする導
体部と同一組成の材料を同一焼成条件で焼結した圧粉焼
結体の熱膨張係数とヤング率の関係が図2の斜線の範囲
内にあるような銅を主成分とする導体部であると、銅を
主成分とする導体部近傍の絶縁体部に働く引張り応力の
値が絶縁体部材料の一般的な強度200MPaを超えな
いので、絶縁体部にクラックが発生しない。また、通
常、セラミック配線基板の配線導体部の固有抵抗は、配
線導体部の主成分である金属の固有抵抗の2倍の値以下
であり、逆にそれぐらいでないと、その金属本来の電気
抵抗の特性を充分に生かしているとはいえない。本発明
の銅を主成分とする導体部の場合も、純銅の固有抵抗が
1.7μΩ・cmであることから、銅を主成分とする導
体部の固有抵抗は少なくとも3.5μΩ・cm以下であ
る必要がある。
FIG. 2 illustrates the equation (2). The coefficient of thermal expansion α 1 and the Young's modulus E 1 of the copper conductor of the glass ceramic multilayer circuit board are determined by the coefficient of thermal expansion α of a sintered compact obtained by sintering a material having the same composition as the copper conductor under the same firing conditions.
And the Young's modulus E, respectively.
Therefore, the coefficient of thermal expansion approximates the coefficient of thermal expansion of Si,
Consisting of an insulator portion mainly composed of glass that can be sintered at a temperature equal to or lower than the melting point of copper and a conductor portion mainly composed of copper, and the conductor portion mainly composed of copper has a volume ratio of 10% or less. In the glass ceramic multilayer circuit board, the relationship between the coefficient of thermal expansion and the Young's modulus of the compact sintered body obtained by sintering a material having the same composition as that of the conductor having copper as a main component under the same sintering conditions is within the range of the hatched portion in FIG. In the case of a conductor portion mainly composed of copper as in the above, since the value of the tensile stress acting on the insulator portion near the conductor portion mainly composed of copper does not exceed the general strength of the insulator portion material of 200 MPa. In addition, no crack occurs in the insulator portion. In addition, the specific resistance of the wiring conductor of the ceramic wiring board is usually equal to or less than twice the specific resistance of the metal that is the main component of the wiring conductor. It cannot be said that the characteristics of the above are fully utilized. Since the specific resistance of pure copper is 1.7 μΩ · cm also in the case of the conductor of the present invention containing copper as a main component, the specific resistance of the conductor containing copper as a main component is at least 3.5 μΩ · cm or less. Need to be.

【0018】実際に、銅に絶縁体部材料と同等のガラス
を添加して、ガラスセラミック基板と同一条件で焼成し
た圧粉焼結体の熱膨張係数と固有抵抗の関係を調べたと
ころ、図3のようになった。図3から、銅を主成分とす
る導体部の固有抵抗が、目標である3.5μΩ・cm以
下となるためには、銅を主成分とする導体部の熱膨張係
数は15.5×10~6/℃以上でなければならないこと
がわかる。すなわち、銅を主成分とする導体部の熱膨張
係数が15.5×10~6/℃以上であれば、銅を主成分
とする導体部の固有抵抗は3.5μΩ・cm以下とな
る。
The relationship between the coefficient of thermal expansion and the specific resistance of a sintered compact obtained by adding glass equivalent to the material of the insulator to copper and firing it under the same conditions as the glass ceramic substrate was examined. It looked like 3. From FIG. 3, the thermal expansion coefficient of the copper-based conductor is 15.5 × 10 5 in order for the specific resistance of the copper-based conductor to be the target of 3.5 μΩ · cm or less. It is understood that the temperature must be higher than ~ 6 / ° C. That is, when the coefficient of thermal expansion of the conductor containing copper as a main component is 15.5 × 10 6 / ° C. or more, the specific resistance of the conductor containing copper as a main component becomes 3.5 μΩ · cm or less.

【0019】したがって、熱膨張係数がSiの熱膨張係
数に近似し、銅の融点以下の温度で焼結可能なガラスを
主成分とする絶縁体部と銅を主成分とする導体部とから
なり、銅を主成分とする導体部が体積割合で10%以下
のガラスセラミック多層回路基板において、銅を主成分
とする導体部と同一組成の材料を同一焼成条件で焼結し
た圧粉焼結体の熱膨張係数α1とヤング率E1の関係が下
記(3)式で示される範囲内、 すなわち、図1に示す斜線の範囲内にあるような銅を主
成分とする導体部であると、銅を主成分とする導体部近
傍の絶縁体部に働く引張り応力の値が、絶縁体部材料の
一般的な強度200MPaを超えないので、絶縁体部に
クラックが発生せず、かつ銅を主成分とする導体部の固
有抵抗が3.5μΩ・cm以下となる。
Therefore, the thermal expansion coefficient is close to the thermal expansion coefficient of Si, and it is composed of an insulator portion mainly composed of glass and a conductor portion mainly composed of copper which can be sintered at a temperature lower than the melting point of copper. A sintered compact of a glass-ceramic multilayer circuit board having a conductor portion mainly composed of copper and having a volume ratio of 10% or less and having the same composition as the conductor portion mainly composed of copper sintered under the same firing conditions. The relationship between the thermal expansion coefficient α 1 and the Young's modulus E 1 is within the range shown by the following equation (3): In other words, if the conductor portion is mainly composed of copper and falls within the range of the hatched portion shown in FIG. 1, the value of the tensile stress acting on the insulator portion in the vicinity of the conductor portion mainly composed of copper is Since the general strength of the material does not exceed 200 MPa, cracks do not occur in the insulator portion, and the specific resistance of the conductor portion containing copper as a main component is 3.5 μΩ · cm or less.

【0020】絶縁体部は、低熱膨張であるホウケイ酸ガ
ラス、コージェライト析出型結晶化ガラス、2Al23
・B23あるいはAl23・B23析出型結晶化ガラス
などを主成分とすることにより、LSI素子と基板の接
続の信頼性が高い。銅を主成分とする導体部の銅に添加
する無機粉末としては、絶縁体部材料と同等のガラスが
好ましいが、銅より熱膨張係数の小さい無機粉末ならば
何でも良い。銅を主成分とする導体部を形成する銅ペー
スト組成物の無機粉末中の銅粉末の体積割合を92%以
上とすることにより、焼成後の銅を主成分とする導体部
の熱膨張係数が15.5×10~6/℃以上となり、固有
抵抗が3.5μΩ・cm以下となる。
The insulator portion is made of borosilicate glass having low thermal expansion, cordierite precipitation type crystallized glass, 2Al 2 O 3
The reliability of connection between the LSI element and the substrate is high by using B 2 O 3 or Al 2 O 3 .B 2 O 3 precipitated crystallized glass as a main component. As the inorganic powder to be added to the copper of the conductor containing copper as a main component, glass equivalent to the material of the insulator is preferable, but any inorganic powder having a smaller thermal expansion coefficient than copper may be used. By setting the volume ratio of the copper powder in the inorganic powder of the copper paste composition for forming the conductor portion containing copper as the main component to be 92% or more, the thermal expansion coefficient of the conductor portion containing copper as the main component after firing is reduced. It becomes 15.5 × 10 6 / ° C. or more, and the specific resistance becomes 3.5 μΩ · cm or less.

【0021】〔実施例 1〕以下、本発明を実施例によ
りさらに具体的に説明するが、本発明はこれら実施例に
限定されるものではない。ガラスセラミック多層回路基
板の製造方法は、まず、グリーンシートを製造するため
のスラリーを製造する。スラリーは、SiO2 を84重
量%、B23を9重量%、Al23を3重量%、アルカ
リ金属酸化物を4重量%の組成からなる平均粒径3μm
のホウケイ酸ガラス粉末63重量部と、平均粒径3μm
のムライト粉末37重量部と、メタクリル酸系のバイン
ダ20重量部と、トリクロルエチレン124重量部と、
テトラクロルエチレン32重量部と、n- ブチルアルコ
ール44重量部とを加え、ボールミルで24時間湿式混
合して製造する。
[Embodiment 1] Hereinafter, the present invention will be described more specifically with reference to embodiments, but the present invention is not limited to these embodiments. In a method for manufacturing a glass ceramic multilayer circuit board, first, a slurry for manufacturing a green sheet is manufactured. The slurry had an average particle diameter of 3 μm having a composition of 84% by weight of SiO 2 , 9% by weight of B 2 O 3 , 3 % by weight of Al 2 O 3 and 4% by weight of an alkali metal oxide.
63 parts by weight of borosilicate glass powder and an average particle diameter of 3 μm
37 parts by weight of mullite powder, 20 parts by weight of a methacrylic acid-based binder, 124 parts by weight of trichloroethylene,
It is manufactured by adding 32 parts by weight of tetrachloroethylene and 44 parts by weight of n-butyl alcohol and wet-mixing with a ball mill for 24 hours.

【0022】つぎに、真空脱気処理を行ない所要の粘度
に調整する。つぎに、このスラリーをドクターブレード
を使用してシリコーンコートしたポリエステルフィルム
上に0.5mmの厚さに塗布し、乾燥してグリーンシー
トを製造する。つぎに、このグリーンシートにポンチで
直径160μmの穴を450μmピッチで明け、種々の
量のガラスを添加した銅ペーストを印刷充填し、さらに
銅ペーストの印刷により、表面層、信号拡大層、シール
ド層、電源拡大層、電源層、X、Y配線層、変換層およ
び裏面層を形成した。
Next, a vacuum deaeration treatment is performed to adjust the viscosity to a required value. Next, this slurry is applied to a thickness of 0.5 mm on a silicone-coated polyester film using a doctor blade, and dried to produce a green sheet. Next, holes of 160 μm in diameter were punched in the green sheet at a pitch of 450 μm with a punch, and a copper paste to which various amounts of glass were added was printed and filled. Further, by printing the copper paste, a surface layer, a signal expansion layer, and a shield layer were formed. The power supply expansion layer, the power supply layer, the X and Y wiring layers, the conversion layer, and the back layer were formed.

【0023】スルーホールに充填する導体ペーストは、
平均粒径3μmの還元銅粉末を50〜100体積%、前
述の平均粒径3μmのホウケイ酸ガラス粉末を50〜0
体積%で配合し、この混合粉末100重量部にエチルヒ
ドロキシエチルセルロース30重量部、ブチルカルビト
ールアセテート100重量部を加えたものを、5分らい
かい(擂潰)機にて混合後、三本ロールを数回通して混
練し、所要の粘度に調整して製造した。スルーホール充
填印刷以外に使用した銅ペーストは、無機成分の95%
以上が銅である一般の銅ペーストである。前記のように
して製造したグリーンシート60枚を位置合わせして積
層した後、熱間プレスにより圧着した。圧着条件は、温
度130℃、圧力は150kgf/cm2 である。
The conductive paste to be filled in the through holes is as follows:
The reduced copper powder having an average particle diameter of 3 μm is 50 to 100% by volume, and the borosilicate glass powder having an average particle diameter of 3 μm is 50 to 0%.
% By weight, and 100 parts by weight of the mixed powder, 30 parts by weight of ethyl hydroxyethyl cellulose and 100 parts by weight of butyl carbitol acetate were mixed for 5 minutes using a triturator (crushing machine). Was kneaded several times, and adjusted to the required viscosity to produce. Copper paste used for printing other than through-hole filling is 95% of inorganic component
The above is a general copper paste which is copper. After aligning and laminating 60 green sheets manufactured as described above, they were pressed by a hot press. Crimping conditions are a temperature of 130 ° C. and a pressure of 150 kgf / cm 2 .

【0024】圧着後、脱脂のため100℃/hr以下の
昇温速度で昇温し、850℃で15時間保持した。雰囲
気は銅を酸化させず、グリーンシートのバインダを飛散
除去できるN2 +H2 +H2 O気流中である。その後、
雰囲気をN2 中に変え、さらに1000℃で2時間焼成
した。前記製造方法により製造したガラスセラミック多
層回路基板のスルーホール銅導体部近傍の絶縁体部のク
ラック発生状況を調べたところ、図4に示すように、図
2において銅を主成分とする導体部の熱膨張係数とヤン
グ率の関係が斜線の範囲内となる銅ペースト組成物を使
用したガラスセラミック多層回路基板ではクラックが発
生せず、斜線の範囲外となる銅ペースト組成物を使用し
たガラスセラミック多層回路基板ではクラックが発生し
た。
After pressing, the temperature was raised at a rate of 100 ° C./hr or less for degreasing, and the temperature was maintained at 850 ° C. for 15 hours. The atmosphere is in an N 2 + H 2 + H 2 O airflow that does not oxidize copper and can scatter and remove the binder of the green sheet. afterwards,
The atmosphere was changed to N 2 and baked at 1000 ° C. for 2 hours. When the state of occurrence of cracks in the insulator portion near the through-hole copper conductor portion of the glass ceramic multilayer circuit board manufactured by the above-described manufacturing method was examined, as shown in FIG. Glass ceramic multilayer circuit board using a copper paste composition in which the relationship between the coefficient of thermal expansion and Young's modulus falls within the range of the hatched lines. No cracks occur on the circuit board, and glass ceramic multilayers using the copper paste composition outside the range of the hatched lines. Cracks occurred on the circuit board.

【0025】〔実施例 2〕銅ペーストの無機成分のう
ちガラス粉末を5体積%とし、残り95体積%を銅粉末
とした銅ペースト組成物をスルーホール充填印刷および
パターン印刷に使用し、他は全て実施例1と同様の製造
方法でガラスセラミック多層回路基板を製造した。この
ガラスセラミック多層回路基板のスルーホール銅導体部
近傍の絶縁体部にクラックは見られず、また銅を主成分
とする導体部の固有抵抗は2.6μΩ・cmであった。
Example 2 A copper paste composition containing 5 vol% of glass powder and 95 vol% of copper powder among the inorganic components of copper paste was used for through-hole filling printing and pattern printing. A glass ceramic multilayer circuit board was manufactured by the same manufacturing method as in Example 1. No crack was observed in the insulator portion near the through-hole copper conductor portion of this glass ceramic multilayer circuit board, and the specific resistance of the conductor portion containing copper as a main component was 2.6 μΩ · cm.

【0026】〔実施例 3〕実施例2で製造したガラス
セラミック多層回路基板の上面に銅とポリイミドを使用
して薄膜多層回路を形成し、LSIチップをはんだ付け
により装着後、ピン付けを行ないモジュールを製造し
た。LSIチップを高精度に接続して製造したモジュー
ルの概略図を図5に示す。実施例2で製造したガラスセ
ラミック多層回路基板1には、ライン配線2およびスル
ーホール3が形成されている。このガラスセラミック多
層回路基板1の上面に銅とポリイミドを使用して薄膜多
層回路4を形成しており、LSIチップ5をはんだ6に
より装着し、ピン7をろう付けしている。ピン7は、銀
ろうによりろう付けされ、LSIチップ5は、Pb−S
nはんだ6により接着されている。ガラスセラミック多
層回路基板1に使用されている絶縁材料8の機械的強度
が大きいため、ピン7のろう付け、LSIチップ5のは
んだ付け等によるピン付け部周辺のクラックは認められ
なかった。またガラスセラミック多層回路基板1に反
り、変形等は認められなかった。
[Embodiment 3] A thin-film multilayer circuit is formed on the upper surface of the glass ceramic multilayer circuit board manufactured in Embodiment 2 using copper and polyimide, an LSI chip is mounted by soldering, and pinning is performed. Was manufactured. FIG. 5 is a schematic diagram of a module manufactured by connecting LSI chips with high precision. In the glass-ceramic multilayer circuit board 1 manufactured in Example 2, a line wiring 2 and a through hole 3 are formed. A thin-film multilayer circuit 4 is formed on the upper surface of the glass ceramic multilayer circuit board 1 using copper and polyimide. An LSI chip 5 is mounted by solder 6 and pins 7 are brazed. The pin 7 is brazed by silver brazing, and the LSI chip 5 is Pb-S
Adhered by n solder 6. Since the insulating material 8 used for the glass ceramic multilayer circuit board 1 has high mechanical strength, no cracks around the pinned portion due to brazing of the pin 7 or soldering of the LSI chip 5 were observed. Also, no warpage or deformation was observed in the glass ceramic multilayer circuit board 1.

【0027】〔実施例 4〕実施例3で製造したモジュ
ールにおいて、ガラスセラミック多層回路基板の上面に
形成した薄膜多層回路とLSIチップとの間に、ガラス
セラミック多層回路基板と同じ材質のキャリア基板をは
さみ、LSIチップとキャリア基板をはんだ付けにより
装着し、LSIチップとキャリア基板を接続しているは
んだの周りを樹脂等で覆ったモジュールを製造した。L
SIチップとキャリア基板を接続しているはんだの周り
を樹脂等で覆うことにより、LSIチップとガラスセラ
ミック多層回路基板とを接続する部分の信頼性を向上し
たモジュールの概略図を図6に示す。
[Embodiment 4] In the module manufactured in Embodiment 3, a carrier substrate of the same material as the glass ceramic multilayer circuit board is provided between the LSI chip and the thin film multilayer circuit formed on the upper surface of the glass ceramic multilayer circuit board. A module was manufactured in which the scissors, the LSI chip and the carrier substrate were mounted by soldering, and the periphery of the solder connecting the LSI chip and the carrier substrate was covered with a resin or the like. L
FIG. 6 is a schematic diagram of a module in which the solder connecting the SI chip and the carrier substrate is covered with a resin or the like to improve the reliability of the portion connecting the LSI chip and the glass ceramic multilayer circuit substrate.

【0028】実施例3で製造したモジュールのガラスセ
ラミック多層回路基板1の上面の薄膜多層回路4とLS
Iチップ5との間にガラスセラミック多層回路基板1と
同じ材質のキャリア基板9をはさみ、LSIチップ5と
キャリア基板9を接続しているはんだ6の周りを樹脂等
10で覆っている。キャリア基板9はスルーホール3の
みで、ラインの印刷を有しないグリーンシートを多層積
層して焼成したものであり、その上面にはポリイミドを
絶縁材料として銅を配線材料とした薄膜多層配線(ガラ
スセラミック多層回路基板1上面の薄膜多層回路4と同
じ)が形成されている。また、配線導体が設けられ、L
SIチップ5とガラスセラミック多層回路基板1とにそ
れぞれはんだ6によって接続されている。
The thin-film multilayer circuit 4 on the upper surface of the glass-ceramic multilayer circuit board 1 of the module manufactured in Example 3 and LS
A carrier substrate 9 made of the same material as the glass ceramic multilayer circuit substrate 1 is sandwiched between the I chip 5 and the solder 6 connecting the LSI chip 5 and the carrier substrate 9 is covered with a resin or the like 10. The carrier substrate 9 is formed by laminating and firing a plurality of green sheets having no line printing only through holes 3 and on the upper surface thereof, a thin film multilayer wiring (glass ceramic) using polyimide as an insulating material and copper as a wiring material. (The same as the thin-film multilayer circuit 4 on the upper surface of the multilayer circuit board 1). A wiring conductor is provided, and L
The SI chip 5 and the glass ceramic multilayer circuit board 1 are connected to each other by solder 6.

【0029】〔実施例 5〕実施例3で製造したモジュ
ールにおいて、ガラスセラミック多層回路基板の上面に
形成した薄膜多層回路とLSIチップとの間に、ガラス
セラミック多層回路基板と同じ材質のキャリア基板をは
さみ、LSIチップとキャリア基板をはんだ付けにより
装着し、さらに、LSIチップにLSIチップを覆うキ
ャップを被せ、キャップをキャリア基板の上面端部およ
びLSIチップ上面ではんだ付けして、LSIチップを
封止したモジュールを製造した。キャリア基板上面のL
SIチップにキャップを被せ、キャップをキャリア基板
の上面端部およびLSIチップ上面ではんだ付けして、
LSIチップを封止したモジュールの概略図を図7に示
す。
Fifth Embodiment In the module manufactured in the third embodiment, a carrier substrate made of the same material as the glass ceramic multilayer circuit board is provided between the LSI chip and the thin film multilayer circuit formed on the upper surface of the glass ceramic multilayer circuit board. The scissors, the LSI chip and the carrier board are mounted by soldering, the LSI chip is covered with a cap that covers the LSI chip, and the cap is soldered on the upper end of the carrier board and the top face of the LSI chip to seal the LSI chip. The manufactured module was manufactured. L on top of carrier substrate
Put the cap on the SI chip, solder the cap on the top edge of the carrier substrate and the top of the LSI chip,
FIG. 7 shows a schematic view of a module in which an LSI chip is sealed.

【0030】実施例3で製造したモジュールのガラスセ
ラミック多層回路基板1の上面の薄膜多層回路4とLS
Iチップ5との間にガラスセラミック多層回路基板1と
同じ材質のキャリア基板9をはさみ、LSIチップ5に
キャップ11を被せ、キャップ11をキャリア基板9の
上面端部およびLSIチップ5上面ではんだ6により接
合し、LSIチップ5を封止している。なお、キャリア
基板9の上面には実施例4同様薄膜多層配線4が形成さ
れている。また、LSIチップ5とガラスセラミック多
層回路基板1との接続は、実施例4同様それぞれはんだ
6によって接続されている。
The thin-film multilayer circuit 4 on the upper surface of the glass-ceramic multilayer circuit board 1 of the module manufactured in Example 3 and LS
A carrier substrate 9 made of the same material as the glass ceramic multilayer circuit substrate 1 is sandwiched between the I-chip 5 and the LSI chip 5, and a cap 11 is put on the LSI chip 5. To seal the LSI chip 5. The thin-film multilayer wiring 4 is formed on the upper surface of the carrier substrate 9 as in the fourth embodiment. Further, the connection between the LSI chip 5 and the glass-ceramic multilayer circuit board 1 is connected by solder 6 as in the fourth embodiment.

【0031】[0031]

【発明の効果】本発明によれば、熱膨張係数がシリコン
の熱膨張係数に近似し、銅の融点以下の温度で焼結可能
なガラスを主成分とする絶縁体部と、銅を主成分とする
導体部とからなり、銅を主成分とする導体部近傍の絶縁
体部にクラックが発生せず、銅を主成分とする導体部の
固有抵抗が銅本来の固有抵抗に近いガラスセラミック多
層回路基板を提供することができる。また、銅を主成分
とする導体部近傍の絶縁体部にクラックの発生がなく、
かつ銅を主成分とする導体部の固有抵抗が銅本来の固有
抵抗に近いガラスセラミック多層回路基板の製造方法、
さらにガラスセラミック多層回路基板の銅を主成分とす
る導体部を形成する銅ペースト組成物およびガラスセラ
ミック多層回路基板からなる半導体実装装置を提供する
ことができる。熱膨張係数がシリコンの熱膨張係数に近
似し、銅の融点以下の温度で焼結可能なガラスを主成分
とする絶縁体部と銅を主成分とする導体部とからなり、
銅を主成分とする導体部が体積割合で10%以下のガラ
スセラミック多層回路基板において、銅を主成分とする
導体部近傍の絶縁体部にクラックを発生させないように
することができる。また、熱膨張係数がシリコンの熱膨
張係数に近似し、銅の融点以下の温度で焼結可能なガラ
スを主成分とする絶縁体部と銅を主成分とする導体部と
からなり、銅を主成分とする導体部が体積割合で10%
以下のガラスセラミック多層回路基板において、銅を主
成分とする導体部近傍の絶縁体部にクラックの発生がな
く、かつ銅を主成分とする導体部の固有抵抗を3.5μ
Ω・cm以下とすることができる。
According to the present invention, an insulator portion whose main component is glass whose thermal expansion coefficient is close to that of silicon and can be sintered at a temperature equal to or lower than the melting point of copper; No cracks occur in the insulator near the conductor containing copper as the main component, and the resistivity of the conductor containing copper as the main component is close to the intrinsic resistivity of copper. A circuit board can be provided. In addition, there is no occurrence of cracks in the insulator portion near the conductor portion containing copper as a main component,
And a method of manufacturing a glass-ceramic multilayer circuit board in which the specific resistance of the conductor portion containing copper as a main component is close to the specific resistance of copper,
Further, it is possible to provide a semiconductor mounting device comprising a copper paste composition for forming a conductor portion containing copper as a main component of the glass ceramic multilayer circuit board and the glass ceramic multilayer circuit board. The coefficient of thermal expansion is close to the coefficient of thermal expansion of silicon, consisting of an insulator part mainly composed of glass and a conductor part mainly composed of copper that can be sintered at a temperature equal to or lower than the melting point of copper,
In a glass-ceramic multilayer circuit board in which a conductor portion containing copper as a main component has a volume ratio of 10% or less, cracks can be prevented from being generated in an insulator portion near a conductor portion containing copper as a main component. In addition, the coefficient of thermal expansion is close to the coefficient of thermal expansion of silicon, and is composed of an insulator portion mainly composed of glass that can be sintered at a temperature equal to or lower than the melting point of copper and a conductor portion mainly composed of copper. Conductor as main component is 10% by volume
In the following glass-ceramic multilayer circuit board, there is no crack in the insulator near the conductor containing copper as a main component, and the specific resistance of the conductor containing copper as a main component is 3.5 μm.
Ω · cm or less.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明における銅を主成分とする導体部の熱膨
張係数とヤング率との関係領域を示すグラフ。
FIG. 1 is a graph showing a relational region between a thermal expansion coefficient and a Young's modulus of a conductor mainly containing copper in the present invention.

【図2】本発明における銅を主成分とする導体部の熱膨
張係数とヤング率との関係領域を示すグラフ。
FIG. 2 is a graph showing a relational region between a coefficient of thermal expansion and a Young's modulus of a conductor mainly containing copper in the present invention.

【図3】本発明における銅を主成分とする導体部の熱膨
張係数と固有抵抗の関係を示すグラフ。
FIG. 3 is a graph showing a relationship between a coefficient of thermal expansion and a specific resistance of a conductor mainly containing copper according to the present invention.

【図4】本発明の実施例における銅を主成分とする導体
部の熱膨張係数とヤング率の関係およびクラックの発生
状況を示すグラフ。
FIG. 4 is a graph showing a relationship between a thermal expansion coefficient and a Young's modulus of a conductor portion containing copper as a main component and a state of occurrence of cracks in an example of the present invention.

【図5】本発明のガラスセラミック多層回路基板の上面
にLSIチップを装着したモジュールの断面概要図。
FIG. 5 is a schematic sectional view of a module in which an LSI chip is mounted on the upper surface of the glass ceramic multilayer circuit board of the present invention.

【図6】本発明のガラスセラミック多層回路基板の上面
に装着したLSIチップとキャリア基板の間を樹脂で覆
ったモジュールの断面概要図。
FIG. 6 is a schematic cross-sectional view of a module in which a space between an LSI chip mounted on an upper surface of a glass ceramic multilayer circuit board of the present invention and a carrier board is covered with a resin.

【図7】本発明のガラスセラミック多層回路基板の上面
に装着したLSIチップをキャップで封止したモジュー
ルの断面概要図。
FIG. 7 is a schematic cross-sectional view of a module in which an LSI chip mounted on the upper surface of the glass ceramic multilayer circuit board of the present invention is sealed with a cap.

【符号の説明】[Explanation of symbols]

1 ガラスセラミック多層回路基板 2 ライン配線 3 スルーホール 4 薄膜多層回路 5 LSIチップ 6 はんだ 7 ピン 8 絶縁材料 9 キャリア基板 10 樹脂 11 キャップ DESCRIPTION OF SYMBOLS 1 Glass ceramic multilayer circuit board 2 Line wiring 3 Through hole 4 Thin film multilayer circuit 5 LSI chip 6 Solder 7 Pin 8 Insulation material 9 Carrier substrate 10 Resin 11 Cap

───────────────────────────────────────────────────── フロントページの続き (72)発明者 牛房 信之 神奈川県横浜市戸塚区吉田町292番地 株式会社日立製作所 生産技術研究所内 (56)参考文献 特開 平5−144316(JP,A) 特開 平6−104575(JP,A) 特開 平6−104573(JP,A) (58)調査した分野(Int.Cl.7,DB名) H05K 3/46 H05K 1/09 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Nobuyuki Ushifusa 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. JP-A-6-104575 (JP, A) JP-A-6-104573 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 3/46 H05K 1/09

Claims (9)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】銅を主成分とする導体部と、 銅の融点以下の温度で焼結可能なガラスを主成分とし、
シリコンの熱膨張係数に近似した熱膨張係数を有する絶
縁体部とからなり、 前記銅を主成分とする導体部が体積割合で10%以下で
あるガラスセラミック多層回路基板において、 前記銅を主成分とする導体部は、銅に無機粉末を添加し
て焼結し、前記銅を主成分とする導体部と同一組成の材
料を同一焼成条件で焼結した圧粉焼結体の熱膨張係数α
[×10-6/℃]とヤング率E[MPa]の関係が次式 15.5<α<1.32×10 5 /(E)+8.58 の範囲であることを特徴とするガラスセラミック多層回
路基板。
1. A conductor portion mainly composed of copper, and a glass mainly sinterable at a temperature not higher than the melting point of copper,
A glass-ceramic multilayer circuit board comprising an insulator portion having a thermal expansion coefficient close to the thermal expansion coefficient of silicon, wherein a conductor portion containing copper as a main component is 10% or less in volume ratio; The conductor portion to be sintered is obtained by adding an inorganic powder to copper and sintering the same, and sintering a material having the same composition as that of the conductor portion containing copper as a main component under the same sintering condition.
Glass ceramic [× 10 -6 / ℃] and the relation of Young's modulus E [MPa] is characterized in that it is a range of the formula 15.5 <α <1.32 × 10 5 / (E) +8.58 Multilayer circuit board.
【請求項2】前記絶縁体部の主成分がホウケイ酸ガラス
からなることを特徴とする請求項1記載のガラスセラミ
ック多層回路基板。
2. The glass ceramic multilayer circuit board according to claim 1, wherein a main component of said insulator portion is made of borosilicate glass.
【請求項3】前記絶縁体部の主成分がコージェライトか
らなることを特徴とする請求項1記載のガラスセラミッ
ク多層回路基板。
3. The glass-ceramic multilayer circuit board according to claim 1, wherein a main component of said insulator portion is made of cordierite.
【請求項4】前記絶縁体部の主成分が2Al23・B2
3 もしくはAl23・B23からなることを特徴とす
請求項1記載のガラスセラミック多層回路基板。
4. The main component of said insulator portion is 2Al 2 O 3 .B 2
O 3 or glass ceramic multilayered circuit board according to claim 1, characterized in that it consists of Al 2 O 3 · B 2 O 3.
【請求項5】前記導体部は、無機粉末を配合した銅ペー
スト組成物を焼成したものであり、前記無機粉末中の銅
粉末の体積割合が92%以上であることを特徴とする
求項1記載のガラスセラミック多層回路基板。
5. A copper sheet containing an inorganic powder, wherein the conductor is made of a copper sheet.
Is obtained by firing the strike composition, the volume ratio of the copper powder of the inorganic powder is characterized in that at least 92%
The glass-ceramic multilayer circuit board according to claim 1.
【請求項6】請求項1乃至5に記載のいずれか一つの
ラスセラミック多層回路基板の上面に、半導体素子をは
んだ付けにより装着してなることを特徴とする半導体実
装装置。
6. A semiconductor mounting device comprising: a semiconductor element mounted on an upper surface of one of the glass ceramic multilayer circuit boards according to claim 1 by soldering.
【請求項7】請求項1乃至5に記載のいずれか一つの
ラスセラミック多層回路基板の上面に、前記ガラスセラ
ミック多層回路基板と同一材質のキャリア基板を介して
半導体素子をはんだ付けにより装着し、前記半導体素子
と前記キャリア基板との接続部分を樹脂により封止して
なることを特徴とする半導体実装装置。
7. On the top surface of one of the glass <br/> Las ceramic multilayer circuit board according to claims 1 to 5, soldering a semiconductor element via the carrier substrate of the glass-ceramic multilayer circuit board of the same material A semiconductor mounting device, wherein the semiconductor device is mounted by attaching, and a connection portion between the semiconductor element and the carrier substrate is sealed with a resin .
【請求項8】請求項1乃至5に記載のいずれか一つの
ラスセラミック多層回路基板の上面に、前記ガラスセラ
ミック多層回路基板と同一材質のキャリア基板を介して
半導体素子をはんだ付けにより装着し、前記半導体素子
にキャップを被せ、前記キャップを前記キャリア基板上
面端部と前記半導体素子上面とではんだ付けし、前記半
導体素子を前記キャップ内に封止してなることを特徴と
する半導体実装装置。
8. A semiconductor element is soldered on an upper surface of any one of the glass ceramic multilayer circuit boards according to claim 1 via a carrier substrate made of the same material as the glass ceramic multilayer circuit board. applied by wearing, put a cap on the semiconductor element, and characterized in that the cap is soldered between the semiconductor element upper surface and the carrier substrate top surface edge, formed by sealing the semiconductor element in the cap Semiconductor mounting equipment.
【請求項9】ガラスセラミック原料粉末とバインダと他
の助剤からグリーンシートを製造し、前記グリーンシー
トに所要の穴あけ後、請求項1に記載の銅を主成分とす
る導体部を形成するために無機粉末中の銅粉末の体積割
合が92%以上である無機粉末を配合した銅ペースト組
成物を穴埋め印刷及びパターン印刷し、前記銅ペースト
組成物を印刷したグリーンシートを位置合わせして複数
枚積層圧着し、焼成することを特徴とするガラスセラミ
ック多層回路基板の製造方法。
9. A preparation of green sheets of a glass ceramic material powder and a binder and other auxiliaries, after the required drilling in the green sheet, to the main component of copper according to claim 1
Volume fraction of copper powder in inorganic powder to form conductive part
Characterized in that the engagement is filling printing and pattern printing a copper paste composition containing inorganic powder is 92% or more, by aligning the green sheets printed with the copper paste composition laminating a plurality crimping, firing Of manufacturing a glass ceramic multilayer circuit board.
JP23909994A 1994-10-03 1994-10-03 Glass ceramic multilayer circuit board and method of manufacturing the same Expired - Fee Related JP3241945B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23909994A JP3241945B2 (en) 1994-10-03 1994-10-03 Glass ceramic multilayer circuit board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23909994A JP3241945B2 (en) 1994-10-03 1994-10-03 Glass ceramic multilayer circuit board and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH08107277A JPH08107277A (en) 1996-04-23
JP3241945B2 true JP3241945B2 (en) 2001-12-25

Family

ID=17039800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23909994A Expired - Fee Related JP3241945B2 (en) 1994-10-03 1994-10-03 Glass ceramic multilayer circuit board and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3241945B2 (en)

Also Published As

Publication number Publication date
JPH08107277A (en) 1996-04-23

Similar Documents

Publication Publication Date Title
EP0211619B1 (en) A multilayer ceramic circuit board
JPS6014494A (en) Ceramic multilayer wiring board and method of producing same
JP3401102B2 (en) Circuit board and method of manufacturing the same, electronic device package, green sheet
JP3652196B2 (en) Manufacturing method of ceramic wiring board
EP0591733A1 (en) Method for producing multilayered ceramic substrate
JP4454105B2 (en) Manufacturing method of multilayer wiring board
JP4535098B2 (en) Manufacturing method of multilayer ceramic electronic component
JPH0727995B2 (en) Ceramic wiring board
JP3241945B2 (en) Glass ceramic multilayer circuit board and method of manufacturing the same
JP4535576B2 (en) Manufacturing method of multilayer wiring board
JP2718152B2 (en) Manufacturing method of ceramic circuit board
JP4029163B2 (en) Multilayer ceramic electronic component and manufacturing method thereof
JPH0613755A (en) Ceramic multilayer wiring board and manufacture thereof
JP2516981B2 (en) Ceramic package and method of manufacturing the same
JP4071908B2 (en) Multilayer wiring board and manufacturing method thereof
JP4493158B2 (en) Ceramic circuit board
JPH0283995A (en) Ceramic multilayer circuit board and its applications
JP3111865B2 (en) Manufacturing method of ceramic substrate
JP3748283B2 (en) Manufacturing method of laminated glass ceramic circuit board
JP2669033B2 (en) Manufacturing method of ceramic circuit board
JP3909186B2 (en) Manufacturing method of glass ceramic substrate
JP2004146701A (en) Method for manufacturing glass ceramic substrate
JPH0828558B2 (en) Ceramic substrate and method for manufacturing the same
JP2001015930A (en) Multilayer printed wiring board and manufacture thereof
JPH06120633A (en) Ceramic wiring board

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071019

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081019

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091019

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091019

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101019

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111019

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees