JPH10209335A - Ceramic circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability on the junction of a chip to be joined to a ceramic board. SOLUTION: At the green sheet 12 in the surface layer of a low-temperature baked ceramic board 11, a ceramic layer 16 having intermediate thermal expansion coefficient between that of low-temperature baked ceramic and a semiconductor chip 15 is printed at the section to mount the semiconductor chip 15. The green sheet 12 is made of the low-temperature baked ceramic material consisting of the mixture between CaO-Al2 O3 -SiO2 -B2 O3 glass powder and alumina powder, and the ceramic layer 16 is made of low-temperature baked ceramic material where Bi2 O3 is mixed by 0.5-15wt.% outwardly to this low-temperature baked ceramic material, and there the thermal expansion coefficient is smaller than that of the low-temperature baked ceramics not containing Bi2 O3 . After simultaneous baking of the low-temperature baked ceramic board 11 and the ceramic layer 16, a surface resistor 18 is printed and baked on the topside of the low-temperature baked ceramic substrate 11, and a semiconductor chip 16 is mounted on the ceramic layer 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic circuit board capable of relieving thermal stress generated at a joint between circuit elements such as a semiconductor chip, a surface resistor, and a surface conductor, which are joined to a mounting surface of a ceramic substrate. Things.

[0002]

2. Description of the Related Art In general, a ceramic substrate has advantages such as excellent heat resistance as compared with a plastic substrate, a small coefficient of thermal expansion, and easy fine patterning. Widely used as. With the recent increase in density and miniaturization, flip chip mounting in which a semiconductor bare chip is directly mounted on a ceramic substrate tends to increase. In this flip-chip mounting, if the difference in thermal expansion coefficient between the chip (Si) and the ceramic substrate is large, a residual stress due to the difference in thermal expansion during mounting occurs at the chip bonding portion, or the chip is relatively heated due to heat generation during normal use. A large thermal stress is generated, and the repetition of the thermal stress easily causes thermal fatigue failure of the chip bonding portion, thereby lowering bonding reliability.

[0003] Among the current ceramic substrates, the most used alumina substrate has a thermal expansion coefficient of 7.0 × 1.
0 ^-6 / deg, which is considerably smaller than the plastic substrate in thermal expansion coefficient. Nevertheless, the thermal expansion coefficient of the alumina substrate is still lower than that of Si (3.5 × 10 ^-6 / de).
Compared with g), the difference in thermal expansion coefficient between them is as large as 3.5 × 10 ⁻⁶ / deg. For this reason, in the case of the alumina substrate, the reliability of flip-chip mounting is reduced.

[0004]

Therefore, in recent years, as shown in Japanese Patent Publication No. 3-53269, a low-temperature fired ceramic substrate which has a smaller thermal expansion coefficient than an alumina substrate and can be fired at 1000 ° C. or lower has been developed. . This low-temperature fired ceramic substrate has a thermal expansion coefficient of about 5.5 × 10 ⁻⁶ / de.
g, and the difference in thermal expansion coefficient from Si is smaller than that of the alumina substrate. However, the difference in thermal expansion coefficient from Si is still about 2.0 × 10 ⁻⁶ / deg. In the case of flip chips, the residual stress and the thermal stress at the chip joint are not sufficiently reduced. Accordingly, with the recent trend toward larger flip-chips, it has been desired to further improve the reliability of flip-chip mounting even on low-temperature fired ceramic substrates.

The difference in the coefficient of thermal expansion between the ceramic substrate and the surface layer thick film pattern portion such as a surface resistor or a surface conductor, which is printed and fired with a thick film paste on the mounting surface of the ceramic substrate, must be reduced. Leads to an improvement in the reliability of the surface layer thick film pattern portion. Generally, the coefficient of thermal expansion of a surface resistor formed of a RuO ₂ -based resistor paste is 5.5 to 7.5.
× 10 ^-6 / deg, Ag, Cu, Au, Ag / P
The thermal expansion coefficient of the surface conductor formed of a conductive paste having a low conductive loss such as d is generally 14 to 20 × 10 ⁻⁶ / deg, and each of them is significantly different from the thermal expansion coefficient of the semiconductor chip.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and accordingly, an object of the present invention is to improve the reliability of circuit elements, such as flip chips and surface layer thick film pattern portions, which are bonded to the mounting surface of a ceramic substrate. An object of the present invention is to provide a ceramic circuit board that can be improved.

[0007]

According to a first aspect of the present invention, there is provided a ceramic circuit board having a ceramic layer having a thermal expansion coefficient different from that of the ceramic substrate on a mounting surface of the ceramic substrate. It has become. With this configuration, even if the difference between the coefficient of thermal expansion of the circuit element (flip chip or the like) bonded to the mounting surface of the ceramic substrate and the coefficient of thermal expansion of the ceramic substrate is large, an intermediate coefficient of thermal expansion between the two is provided between the two. With the ceramic layer interposed, residual stress and thermal stress generated at the joint of the circuit element can be reduced by the ceramic layer.

In this case, the ceramic layer is partially formed on the mounting surface of the ceramic substrate,
It is preferable that a plurality of types of circuit elements having different coefficients of thermal expansion be arranged closer to one of the mounting surfaces of the ceramic layer and the other ceramic substrate than those having a smaller coefficient of thermal expansion.
With this configuration, even when a plurality of types of circuit elements having different coefficients of thermal expansion are arranged on one ceramic substrate, the circuit elements are arranged so as to reduce the difference in coefficient of thermal expansion between each circuit element and its joint surface. And good bonding properties can be obtained. In addition, since only the ceramic layer is provided partially on the ceramic substrate, the stress generated between the ceramic layer and the ceramic substrate during firing can be reduced as compared with the case where the ceramic layer is provided on the entire surface of the substrate (this stress). Is large, the ceramic substrate is warped).

Further, the thermal expansion coefficient of the ceramic layer is set smaller than the thermal expansion coefficient of the ceramic substrate and larger than the thermal expansion coefficient of a semiconductor chip mounted on the ceramic layer. Is preferred. In this way, even if the difference in thermal expansion coefficient between the ceramic substrate and the semiconductor chip is large, a ceramic bare chip is directly mounted by interposing a ceramic layer having an intermediate thermal expansion coefficient therebetween. Chip mounting becomes possible.

If the difference in thermal expansion coefficient between the ceramic substrate and the ceramic layer is large, the ceramic substrate may warp or the ceramic layer may be peeled off due to stress during firing.

As a countermeasure against this, the difference in the coefficient of thermal expansion between the ceramic substrate and the ceramic layer is reduced by 1.5.
It is preferable to set it to ^10-6 / deg or less. In this case, warpage of the ceramic substrate and peeling of the ceramic layer during firing can be suppressed.

The ceramic layer may be fired after the firing of the fired ceramic substrate, but the ceramic substrate and the ceramic layer may be fired simultaneously. In this way, the number of firing steps does not increase,
Productivity does not decrease.

Further, in the case of applying the present invention to the low-temperature fired ceramic substrate, as in claim 6, a ceramic _{substrate, CaO-Al 2 O 3 -SiO} 2 -B 2 O 3 based glass powder and alumina powder , And a ceramic layer is formed by externally applying Bi ₂ O ₃ to the low-temperature fired ceramic material in a range of 0.5 to 0.5.
It may be formed of a low-temperature fired ceramic material blended at 15% by weight. As shown in Tables 1 and 2 below, Bi ₂
The thermal expansion coefficient of a low-temperature fired ceramic not containing O ₃ is
In contrast to 5.2 to 5.7 × 10 ⁻⁶ / deg, Bi
_The coefficient of thermal expansion of a low-temperature fired ceramic containing 0.5 to 15% by weight of ₂ O ₃ on an outer basis is 4.6 to 5.0 × 10 ⁻⁶ / d.
eg, the thermal expansion coefficient of Si (3.5 × 10 ⁻⁶ / de)
g). As a result, the advantage of low thermal expansion coefficient, which is one of the advantages of the low-temperature fired ceramic, can be further improved, and the reliability of flip-chip mounting can be improved.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] First, a first embodiment of the present invention will be described with reference to FIG.
A configuration example of the low-temperature fired ceramic circuit board according to the embodiment will be described. The low-temperature fired ceramic substrate 11 is obtained by laminating a plurality of low-temperature fired ceramic green sheets 12, thermocompression bonding, and firing at 800 to 1000 ° C.

Green sheet 12 of low-temperature fired ceramic
Is manufactured by the following procedure. First, CaO: 10
55 wt%, SiO _2: 45~70 wt%, Al ₂ O
_3: 0-30 wt%, impurities: 0 to 10% by weight and in outer percentage B ₂ O _3: A mixture containing 5 to 20 wt% 1450
After vitrified by melting at ° C., quenched in water, which was triturated to prepare a _{CaO-Al 2 O 3 -SiO 2} -B 2 O 3 based glass powder. 50-65% by weight of this glass powder
(Preferably 60% by weight) and 0 to 10% by weight of impurities
Of Al ₂ O ₃ powder of 50 to 35% by weight (preferably 40% by weight) to produce a low-temperature fired ceramic powder,
A solvent (for example, toluene,
Xylene), a binder resin (for example, an acrylic resin) and a plasticizer are added and sufficiently kneaded to prepare a slurry, and a green sheet is prepared using a normal doctor blade method.

The green sheet is cut into a predetermined size,
A via hole (not shown) is punched at the predetermined position,
The green sheet 12 of each layer is formed. Then, Ag, Ag / Pd,
An Ag-based conductor paste such as Ag / Pt is filled, and an inner-layer conductor pattern 13 is screen-printed on the inner-layer green sheet 12 using an Ag-based conductor paste having the same composition as the above. The surface conductor pattern 14 is screen printed. In this case, the conductor paste to be used is C instead of Ag-based conductor paste.
Other low melting point metals such as u and Au may be used.

Further, the uppermost green sheet 12 includes
A ceramic layer 16 having a coefficient of thermal expansion intermediate between the coefficient of thermal expansion of the low-temperature fired ceramic and the coefficient of thermal expansion of the semiconductor chip 15 is formed by screen printing on a portion where the semiconductor chip 15 is mounted. The composition of the ceramic layer 16 is for the Bi ₂ O ₃ with respect to the low-temperature co-fired ceramic material having the same composition as the green sheet 12 described above and by outer percentage blending 0.5 to 15 wt%, the low-temperature co-fired ceramic material A binder resin (ethyl cellulose or polyvinyl butyral) and a solvent are added to the mixture, and the mixture is sufficiently kneaded to produce a paste of a low-temperature fired ceramic material.
Is partially screen-printed at a predetermined position to form a ceramic layer 16. Pads 17 for connecting the semiconductor chip 15 (flip chip) are screen-printed on the surface of the ceramic layer 16 with an Ag-based conductor paste.
Note that via conductors (not shown) for connecting the pads 17 to the conductor patterns 13 and 14 are screen-printed in advance on the ceramic layer 16 with an Ag-based conductor paste.

After the above-described printing process is completed, the green sheets 12 of each layer are laminated, and the green sheets 12 are, for example, 80 to 150.
° C (preferably 110 ° C), 50 to 250 kg / cm ²
Thermocompression bonding under the conditions described above. Then, the laminated body is heated at a substrate firing temperature of 800 to 1000 ° C. (preferably 9 ° C.).
(At 00 ° C.) for 20 minutes, and the low-temperature fired ceramic substrate 11 and the ceramic layer 16 are fired simultaneously. In this firing process, Bi contained in the ceramic layer 16
Part of the ₂ O ₃ diffuses into the surface green sheet 12 to form a ceramic having an intermediate thermal expansion coefficient around the ceramic layer 16. Thereby, the low temperature fired ceramic substrate 1
The coefficient of thermal expansion between the ceramic substrate 1 and the ceramic layer 16 changes continuously, thereby relaxing the stress during firing and preventing the low-temperature fired ceramic substrate 11 from warping.

Thereafter, the surface resistor 1 is formed on the upper surface of the low-temperature fired ceramic substrate 11 by using a RuO ₂ -based resistor paste.
8 is screen-printed, and an overcoat (not shown) is screen-printed on the surface resistor 18 using an overcoat paste. Thereafter, the surface resistor 18 and the overcoat are fired on the low-temperature fired ceramic substrate 11 at a temperature slightly lower than the substrate firing temperature (for example, 890 ° C.) for 10 minutes. Thus, the manufacture of the low-temperature fired ceramic substrate 11 is completed.

Thereafter, the low-temperature fired ceramic substrate 11
When the semiconductor chip 15 is flip-chip mounted on the substrate, the electrode on the lower surface of the semiconductor chip 15 is connected to the pad 17 of the ceramic layer 16 of the low-temperature fired ceramic substrate 11 by Ag epoxy 19 or solder bump.

The present inventor measured the thermal expansion coefficients of low-temperature fired ceramics having three types of compositions A, B and C shown in Table 1 below.

[0022]

[Table 1]

In Table 1, each component (C
aO, Al ₂ O ₃ , SiO ₂ , B ₂ O ₃ )
Expressed as a weight ratio to the low-temperature fired ceramic. Composition A is a mixture of _{CaO-Al 2 O 3 -SiO 2} -B 2 O 3 based glass powder 60 wt% and Al ₂ O ₃ powder 40 wt%, the thermal expansion coefficient of 5.5 × 10 ^-6 / Deg.

Composition B is composed of CaO—Al ₂ O ₃ —SiO ₂
-B ₂ O ₃ based glass powder 55 wt% and Al ₂ O ₃ powder 4
5% by weight, and has a thermal expansion coefficient of 5.7 × 10
⁻⁶ / deg.

The composition C is CaO--Al ₂ O ₃ --SiO ₂
-B ₂ O ₃ system 65 wt% glass powder and the Al ₂ O ₃ powder 3
5% by weight, and has a coefficient of thermal expansion of 5.2 × 10
⁻⁶ / deg. The thermal expansion coefficients of the low-temperature fired ceramics of these compositions A, B, and C are all smaller than the thermal expansion coefficient of the alumina substrate (7.0 × 10 ⁻⁶ / deg).

Further, the present inventor conducted a test for evaluating the relationship between the composition of the low-temperature fired ceramic material forming the ceramic layer 16 and the coefficient of thermal expansion. The test results are shown in Table 2 below.

[0027]

[Table 2]

Table 2 shows the compositions A, B, and C of Table 1 described above.
When Bi ₂ O ₃ is added to the low temperature firing ceramic of
It is a measure of how much the coefficient of thermal expansion changes with the amount of i ₂ O ₃ added. From this measurement result, Bi ₂
If the added amount of O ₃ is 0.5 to 15% by weight on the outside,
In any of the compositions, the coefficient of thermal expansion is 5.0 × 10 ⁻⁶ / de.
g or less, and the coefficient of thermal expansion is smaller than that of the low-temperature fired ceramic containing no Bi ₂ O ₃ .

The present inventor has proposed a low-temperature fired ceramic substrate 11.
In order to evaluate the bonding reliability of the semiconductor chip 15 mounted on the ceramic layer 16 of the above, a ceramic layer was added to the surface layer of the low-temperature fired ceramic substrate 11 using a paste made by adding Bi ₂ O ₃ to the low-temperature fired ceramic of the composition A. After printing and firing this, the semiconductor chip 15 is mounted on the ceramic layer 16 with an Ag epoxy 19, and subjected to a temperature cycle test (−55 ° C. 30 minutes / + 150 ° C. 30 minutes: 100).
Cycle), and the failure rate of the chip junction was measured. The measurement results are shown in Table 3 below.

[0030]

[Table 3]

As is clear from the test results in Table 3,
When the addition amount of Bi ₂ O ₃ is 0% by weight (substantially the same as when there is no ceramic layer 16), the failure rate is 0.5%.
However, the added amount of Bi ₂ O ₃ is 0.5 to 15
If it is% by weight, the thermal expansion coefficient is 4.9 × 10 ⁻⁶ / deg.
Since it is close to the thermal expansion coefficient (3.5 × 10 ⁻⁶ / deg) of the semiconductor chip 15 (Si), the failure rate is 0%, and extremely high bonding reliability can be obtained. Bi ₂
When the added amount of O ₃ is 20% by weight or more on the outside, the difference in thermal expansion coefficient from Si becomes large, so that the failure rate is 0.2%.
As a result, the bonding reliability decreases. Accordingly, to ensure sufficient bonding reliability, it is preferable to set the addition amount of Bi ₂ O ₃ in outer percentage in the range of 0.5 to 15 wt%. In this case, the difference in the coefficient of thermal expansion between the ceramic layer 16 and the Si is 1.2 to 1.4 × 10 ⁻⁶ / deg.
The elasticity of the resin can sufficiently reduce the residual stress and the thermal stress, and can maintain the failure rate at 0%.

If the difference in thermal expansion coefficient between the low-temperature fired ceramic substrate 11 and the ceramic layer 16 is large, the low-temperature fired ceramic substrate 11 may warp or the ceramic layer 16 may be peeled off due to stress during firing.

As described above, when the additive amount of Bi ₂ O ₃ is set within the range of 0.5 to 15% by weight, the thermal expansion coefficient of the ceramic layer 16 becomes 4.6 to 5.0 × 10 5. ^-6 /
deg (see Table 2), and the difference in thermal expansion coefficient between the ceramic layer 16 and the low-temperature fired ceramic substrate 11 is 0.9 × 1.
0 ⁻⁶ / deg or less. With such a difference in the coefficient of thermal expansion, the stress during the firing is sufficiently relaxed by forming a ceramic having an intermediate coefficient of thermal expansion around the ceramic layer 16 by diffusion of Bi ₂ O ₃ during the firing. Thus, warpage of the low-temperature fired ceramic substrate 11 and peeling of the ceramic layer 16 can be sufficiently suppressed. In general, if the difference in the thermal expansion coefficient between the ceramic layer 16 and the low-temperature fired ceramic substrate 11 is 1.5 × 10 ⁻⁶ / deg or less, the warpage of the low-temperature fired ceramic substrate 11 and the peeling of the ceramic layer 16 can be sufficiently reduced. Can be suppressed.

Next, the reliability of the surface resistor 18 will be considered. In general, the resistance of the surface resistor 18 after firing varies, so that the resistance is adjusted by trimming the surface resistor 18 by laser trimming or the like after firing. Surface resistor 1
In some cases, microcracks may be formed in 8 and the microcracks gradually progress in an actual use environment, causing the resistance value to change with time, thereby possibly lowering the reliability of the circuit. The progress of the microcracks is likely to occur in a state where a tensile stress is acting on the surface layer resistor 18. Therefore, in order to prevent the progress of microcracks, it is desirable to set the relationship of the thermal expansion coefficient of the low-temperature fired ceramic substrate 11> the thermal expansion coefficient of the surface resistor 18 so that a compressive force is applied to the surface resistor 18.

Generally, RuO for forming the surface layer resistor 18 is used.
_{The 2-} system resistor paste is made of RuO ₂ powder (thermal expansion coefficient:
6.0 × 10 ⁻⁶ / deg) and a glass powder, so that even if a glass powder having a small coefficient of thermal expansion is used,
The thermal expansion coefficient of the surface layer resistor 18 is set to 5.0 × 10 ⁻⁶ / deg.
It is difficult to make smaller. Therefore, the surface resistor 1
8 is 5.0 × 10 ⁻⁶ / d
A thermal expansion coefficient of at least eg is desirable. From this viewpoint, in the above embodiment, the surface resistor 18 is formed on the surface of the low-temperature fired ceramic substrate 11.

The surface resistor 18 is 0.5 mm or more (preferably 1 m) from the ceramic layer 16 so as not to be affected by the coefficient of thermal expansion of the ceramic layer 16 containing Bi ₂ O _3.
m or more).

The present inventor conducted the following test in order to evaluate the reliability of the surface resistor 18. As shown in FIG. 2, the low-temperature fired ceramic substrate 21 (thermal expansion coefficient:
5.5 × 10 ⁻⁶ / deg) on the surface of resistor electrode A
g conductors 22 were printed and fired at 2 mm intervals, and a surface resistor 23 (width 1 mm) having a thermal expansion coefficient of 5.3 × 10 ⁻⁶ / deg was printed and fired thereon. Thereafter, the surface resistor 23 is laser-trimmed to adjust its resistance to twice the initial value, and then subjected to a temperature cycle test (−55 ° C.).
30 minutes / + 150 ° C. 30 minutes: 100 cycles)
The rate of change of the resistance value of the surface resistor 23 was measured. When this measurement was performed for 100 samples, the following Table 4
Was obtained.

[0038]

[Table 4]

The rate of change of the resistance value of the surface resistor 23 measured in this test is as small as 0.23% at the maximum, and sufficiently satisfies the required value (within 1%). Therefore, even if a ceramic layer having a different thermal expansion coefficient partially exists on the surface of the low-temperature fired ceramic substrate 21, the reliability of the surface layer resistor 23 is not affected at all.

In the present embodiment (FIG. 1), the ceramic layer 16 is printed on the surface of the low-temperature fired ceramic substrate 11, but a green sheet formed of a material having the same composition as the ceramic layer 16 may be laminated.

[Second Embodiment] In the first embodiment, the ceramic layer 16 is printed on the surface of the low-temperature fired ceramic substrate 11, but in the second embodiment shown in FIG. An opening 25 is formed at a portion where the semiconductor chip 15 is mounted, and the opening 25 is
A ceramic layer 26 having an intermediate thermal expansion coefficient between the low-temperature fired ceramic substrate 11 and the semiconductor chip 15 is filled and fired, and the semiconductor chip 15 is mounted on the ceramic layer 26. The ceramic layer 26 has the same composition as that of the first embodiment, and may be formed by printing a paste of the ceramic layer 26, or may be formed by cutting a green sheet used in a third embodiment described later into predetermined dimensions and opening the green sheet. 25 may be fitted. The other configuration is the same as that of the first embodiment described above.

Although the surface resistor 18 is formed in the first and second embodiments, it goes without saying that the structure may be omitted. Further, the ceramic layers 1 are formed at a plurality of locations on one low-temperature fired ceramic substrate 11.
6 and 26 may be formed, and a plurality of flip chips may be mounted on one ceramic layer 16 and 26.

[Third Embodiment] In the first and second embodiments, the ceramic layers 16 and 26 are formed only on a part of the surface of the low-temperature fired ceramic substrate 11, but the third embodiment shown in FIG. In the embodiment, the green sheet 27 having an intermediate thermal expansion coefficient between the low-temperature fired ceramic substrate 11 and the semiconductor chip 15 is laminated as a “ceramic layer” on the uppermost layer (surface layer) of the low-temperature fired ceramic substrate 11 so that the low-temperature fired ceramic substrate 11 and the semiconductor chip 15 are stacked. Ceramic layers 27 having different thermal expansion coefficients are formed on the entire surface of the fired ceramic substrate 11. This ceramic layer 2
The composition of No. 7 is the same as that of the first embodiment. The green sheet forming the ceramic layer 27 is formed by tape-forming a slurry prepared by adding a binder resin, a solvent, and a plasticizer to a low-temperature fired ceramic material containing 0.5 to 15% by weight of Bi ₂ O ₃ on an outer surface. As the binder resin, an acrylic resin or polyvinyl butyral may be used.

In the third embodiment, two types of green sheets 12 and 27 having different coefficients of thermal expansion are stacked and fired. Therefore, in a normal firing method, the low-temperature fired ceramic substrate 11 is warped or the ceramic layer 27 is warped. May be peeled off. Green sheet 12,
What is necessary is just to bake while pressurizing the 27 laminated bodies. By this pressure firing, warpage of the low-temperature fired ceramic substrate 11 and peeling of the ceramic layer 27 can be prevented.

It should be noted that the third embodiment is preferably applied to a circuit board having no surface layer resistor on the board surface. When the surface resistor is provided, the thermal expansion coefficient of the substrate surface is smaller than the coefficient of thermal expansion of the surface resistor, and a tensile stress acts on the surface resistor to easily cause microcracks in the surface resistor. This is because the rate of change of the resistance value becomes large.

In each of the first to third embodiments, the low-temperature fired ceramic material is CaO—Al ₂ O ₃ —Si
A mixture of an O ₂ —B ₂ O ₃ -based glass powder and an alumina powder was used, but MgO—Al ₂ O ₃ —SiO ₂ —B ₂ O ₃
800-1 such as a mixture of base glass powder and alumina powder
Other low-temperature fired ceramics that can be fired at 000 ° C. may be used.

The ceramic circuit board of the present invention is not limited to a low-temperature fired ceramic circuit board, but can be applied to a circuit board formed of another ceramic such as an alumina circuit board.

[0048]

As is apparent from the above description, according to the first aspect of the present invention, a ceramic layer having an intermediate thermal expansion coefficient is provided between a ceramic substrate and a circuit element (flip chip or the like). Can be interposed, the residual stress and the thermal stress generated at the joint of the circuit element can be reduced by the ceramic layer, and the reliability of the circuit element can be improved.

Further, in the present invention, the ceramic layer is partially formed on the mounting surface of the ceramic substrate.
Even when a plurality of types of circuit elements having different coefficients of thermal expansion are arranged on one ceramic substrate, the circuit elements can be arranged so as to reduce the difference in the coefficient of thermal expansion between each circuit element and its joint surface. Sex can be obtained.

According to the third aspect, the coefficient of thermal expansion of the ceramic layer is set to be smaller than the coefficient of thermal expansion of the ceramic substrate and larger than the coefficient of thermal expansion of the semiconductor chip. High-performance flip-chip mounting can be performed.

Further, the difference in the coefficient of thermal expansion between the ceramic substrate and the ceramic layer is 1.5 × 10 ⁻⁶ / d.
Since it is set to be equal to or less than eg, the warpage of the ceramic substrate and the peeling of the ceramic layer during firing can be suppressed without firing under pressure, and the quality of the ceramic circuit board can be improved.

According to the fifth aspect, since the ceramic substrate and the ceramic layer are simultaneously fired, the number of firing steps is not increased, and a high quality ceramic circuit board can be manufactured efficiently.

According to claim 6, the ceramic substrate is made of C
aO-Al ₂ O ₃ —SiO ₂ —B ₂ O _{3 A} low-temperature fired ceramic material made of a mixture of a glass powder and an alumina powder, and a ceramic layer is formed by applying Bi ₂ O ₃ to the low-temperature fired ceramic material. Low thermal expansion coefficient, which is one of the advantages of the low temperature firing ceramic, is formed by using a low temperature firing ceramic material mixed with 0.5 to 15% by weight on the outside, while maintaining good sinterability between the ceramic substrate and the ceramic layer. Can be further improved, and the reliability of flip chip mounting can be improved.

[Brief description of the drawings]

FIG. 1 is an enlarged vertical sectional view schematically showing a structure of a ceramic circuit board according to a first embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a pattern of a surface resistor and a conductor used in a reliability evaluation test of the surface resistor.

FIG. 3 is an enlarged longitudinal sectional view schematically showing the structure of a ceramic circuit board according to a second embodiment of the present invention.

FIG. 4 is an enlarged longitudinal sectional view schematically showing the structure of a ceramic circuit board according to a third embodiment of the present invention.

[Explanation of symbols]

11: low-temperature fired ceramic substrate, 12: green sheet, 13: inner conductor pattern, 14: surface conductor pattern, 15: semiconductor chip, 16: ceramic layer, 17 ...
Pad, 18: Surface resistor, 19: Ag epoxy, 21
... Low-temperature fired ceramic substrate, 22 Ag conductor, 23 surface resistor, 26 ceramic layer, 27 green sheet (ceramic layer).

Claims (6)

[Claims] 1. A ceramic circuit board having, on a mounting surface of a ceramic substrate, a ceramic layer having a thermal expansion coefficient different from that of the ceramic substrate. 2. The ceramic layer is partially formed on a mounting surface of the ceramic substrate, and includes a plurality of circuit elements having different coefficients of thermal expansion between the ceramic layer and other mounting surfaces of the ceramic substrate. 2. The ceramic circuit board according to claim 1, wherein the ceramic circuit board has a thermal expansion coefficient close to that of the ceramic circuit board. 3. The thermal expansion coefficient of the ceramic layer is smaller than the thermal expansion coefficient of the ceramic substrate and larger than the thermal expansion coefficient of a semiconductor chip mounted on the ceramic layer. 4. The ceramic circuit board according to claim 1. 4. The ceramic according to claim 1, wherein a difference in thermal expansion coefficient between the ceramic substrate and the ceramic layer is 1.5 × 10 ⁻⁶ / deg or less. Circuit board. 5. The ceramic substrate according to claim 1, wherein said ceramic substrate and said ceramic layer are co-fired.
The ceramic circuit board according to any one of the above. 6. The ceramic substrate is made of CaO—Al _2.
The ceramic layer is formed of a low-temperature fired ceramic material made of a mixture of an O ₃ —SiO ₂ —B ₂ O ₃ -based glass powder and an alumina powder, and the ceramic layer is formed by applying Bi ₂ O ₃ to the low-temperature fired ceramic material. 6. The ceramic circuit board according to claim 1, wherein said ceramic circuit board is formed of a low-temperature fired ceramic material containing 0.5 to 15% by weight.