JPS60149173A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To enable the stress in a film to be controlled to the neighborhood of zero with good reproducibility by a method wherein the first film showing the compression or tensile stress in a film is adhered on a compound semiconductor substrate, and next the second film showing the stress reverse to that in the first film is adhered. CONSTITUTION:An N type ion implanted layer 24 is formed in the GaAs semi- insulation substrate 21 by using a photo resist 22 and an SiO2 23 as a masking material. Next, the resist 22 and the SiO2 23 are removed, and thereafter W 25 is adhered by means of an electron beam vapor deposition device. At this time, the stress in the film in tensile stress. Then, W 26 is adhered by means of a sputter vapor deposition device. At this time, the stress in the film is compression stress. This manner enables the two layers of W 25 and 26 to be adhered at a low stress in the film. After adhesion of an SiO2 27, the W's 25 and 26 are processed into a gate electrode 28. An N<+> layer 29 is formed by Si ion implantation with the W's 25 and 26 and the SiO2 27 as a mask, thus making the electrode 28 and the layer 29 into the self-alignment type. This manner improves the gate electrode in heat resistance and causes no exfoliation even by annealing.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a compound semiconductor Schottky barrier gate field effect transistor (hereinafter abbreviated as MBSFET) such as QaAs.
and its Schottky electrode formation method.

[Background of the invention]

In a self-aligned GaAs MESFET in which the n0 layer is formed by ion implantation using the gate electrode as a mask, the Schottky electrode is required to have high heat resistance. FIG. 1 shows an outline of an example of the manufacturing process.

(11 Semi-insulating GaAs substrate 11 with n layer 1”2)
After i ion implantation, gate electrode 13 is formed (Fig. 1 (11), 12R (7) gate polarization 13 and U CV
D8 An n+ layer 16 is formed by Si ion implantation using one fOi film and four film tubes (FIG. 1(2)). (3)
An 810*CVD film or a 5i-N plasma CVD film is deposited as a cap material 17 to serve as a surface protection film, and annealed in an H2 atmosphere (FIG. 1 (3)). (4) Form source/drain t4 (AuGe/Ni/Au) 18 to complete GaAsME8F'gT (Fig. 1 (4)
)).

The requirements required for this manufacturing process are (1) H2 annealing after ion implantation (near SOOC)
It must not peel off from the GaAs substrate due to

(2) The electrical properties of the Schottky electrode are improved by heat treatment.
The ideal index (n value), Schottky barrier height (φ), etc. should not deteriorate.

It is.

In order to prevent deterioration due to this heat treatment, there is a method of reducing the stress in the film by optimizing the composition of titanium tungsten silicide and tungsten silicide. (Onishi et al.''Ultra high speed uaAsVL8I
"W silicide gate self-alignment technology aimed at Met.

[Purpose of the invention]

The object of the present invention is to produce a QaA8MESFE' in which a high melting point metal or a high melting point metal compound with low internal stress is used for the gate electrode.
The object of the present invention is to provide a method for manufacturing l'.

[Summary of the Invention] Generally, when a metal thin film is coated on a substrate, the film itself has internal stress. This internal stress in the film is calculated from the following equation by measuring the warp of the substrate before and after the thin film is applied.

Here, σ; intramembrane stress Es; Young's modulus of the substrate D; Substrate thickness r; Radius of curvature of the substrate t: Thin film thickness C; Poisson's ratio It is.

The stress in the film differs depending on the deposition method, for example, sputter-deposited film, EB-deposited film, or cluster ion beam-deposited film. Generally, EB vapor deposited films tend to have tensile stress, and sputtered films tend to have compressive stress. Furthermore, the stress within the film changes depending on deposition conditions, such as substrate temperature, Ar pressure during deposition, deposition speed, Ar pressure during deposition, and the like. Regarding the sputtered film of W, an example in which the sputtered film was deposited on a glass plate and the stress in the film was investigated is as follows: -TL1ngst6Hm by R, 8, Wagner et al.
etallization for LSI appl
cations'J, vac, Sci, Techno
11.582 (1974). According to this, it is possible to change the stress in the film from compressive to tensile by changing the At pressure, RF pressure, substrate/earth. It has been difficult to control it with good reproducibility because the

Therefore, in forming the gate electrode of GaAsMEiSFE'l', the present method (1) deposits a first film exhibiting compressive or tensile internal stress on the aA8 substrate under stable conditions, and then deposits the first film exhibiting compressive or tensile internal stress on the aA8 substrate, and then deposits the first film exhibiting compressive or tensile internal stress on the aA8 substrate. The purpose is to coat the second film exhibiting stress to obtain a desired film thickness as a whole, and to control the stress within the film to be near the upper opening with good reproducibility. Furthermore, it is also possible in principle to use a multilayer film of three or more layers.

[Implementation sequence of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

[Implementation Fill] Figure 2 shows the manufacturing process of GaAs MESFET.

(1) Chromium<cr) doped GaA3 semi-insulating substrate 21 is coated with photoresist 22 of SiQ, 23 is used as a mask material, and n-type impurity Si is applied at a dose of 4X1012Crl.
The ion implantation layer 24 is formed under conditions of implantation energy of 75 KeV (FIG. 2(1)).

(2) After removing the photoresists 22 and 8i0i 23 mask materials, first deposit W25 using an EB evaporator (
Figure 2 12)). A film thickness of 200 nm is deposited at a substrate temperature of 300C. At this time, the stress in the film is σ==3xlO'dyne
The tensile force was /(-.Next, the film was coated with a W26 spacing evaporator.The film thickness was 200 nm and the substrate temperature was 250 nm.
The film was deposited using C at an argon pressure of 28 wTOrr during sputtering. At this time, the stress in the film was a compressive stress of σ=3X'' dYne/crl. Two layers W with total thickness 4 Q Q nm
25 and 26 can be deposited with low intra-film stress. Generally, if EB evaporation is used before forming a high melting point metal thin film, tensile stress can be stably obtained, and if sputter evaporation is used, compressive stress can easily be obtained. Using this property, Ta other than W
A stable film with low internal stress can also be obtained using high melting point metals such as.

(After depositing 31SiO*27 to a thickness of 300 nm, it is processed into the gate electrode 28 using normal photolithography technology (
Figure 2 (3)).

(4) Using W25.26 and S10*27 as mask materials, Si is ion-implanted to form the n9 layer 29, making the gate electrode 28 and the n+ layer 29 self-aligned. At this time, a photoresist 30 is used to prevent Bi ions from being implanted in areas other than the desired areas (FIG. 2 (4)).

(5) After removing the photoresists 30 and 5j0227, annealing is performed in an H2 atmosphere for 80 minutes (1, 2.0 minutes) to activate the n-no and n7 layers. At this time, in order to prevent thermal decomposition of GaAS, remove the cap and ax beforehand. t, csi-
An N plasma CVD film and an 8102CVD film are deposited (FIG. 2 (5)).

(6) Finally, source/drain electrodes 32 are formed using a three-layer film of AuGe/Ni/Au using a normal lift-off technique (FIG. 2 (6)).

According to the present invention, the resistance of silicide is ρ=7130.
W has a high gate resistance of μΩ1, which is disadvantageous for high-speed modulation, but W has a value of about 20 μΩ−m, which is advantageous for modulation.

The characteristics of the QaAsFET manufactured in this way are as follows: source-drain voltage V8D=2v%
Source-drain current I 4g = 34±4 under the conditions of ■
mA was obtained. Also, Idg per 1 μm of gate width is 0.
When the pinch-off voltage was measured under the condition of 5 μA, V,
=-1.8±0.1■ was obtained. Also, mutual conductor 7
Good results were obtained with gm=100 to 125 m5/+m.

[Example 2] Although Example 1 used a two-layer structure of an EB vapor-deposited film and a sputter-deposited film, it is also possible to use only a sputter-deposited film. Snow on a semi-insulating GaAS substrate (argon pressure in ivy 14 m)
Tungsten (VV) silicide is coated to a thickness of 200 nm under conditions of T or r. The stress in the film is compressive stress and σ=
2×IO'd)'ne/i. Next, as a second layer, 20011 m of W silicide is deposited under an argon pressure of 24 II 111 Torr. ('=-2X 10' d
The tensile stress was yne/cyd. The stress of this film as a whole was extremely small, the heat resistance of the gate electrode was improved, and no peeling occurred even after Ha annealing at 80 (I').

In addition, the stress in the film can also be controlled by applying a substrate bias during sputtering. In combination with this method, it was also possible to reduce the stress within the film.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the stress in the film of a high melting point metal or a high melting point metal ceramic (for example, a high melting point metal silicide) serving as a gate electrode with good reproducibility.

This eliminates the possibility of peeling off due to the activation of ion-implanted impurities, that is, high-temperature annealing in an H2 atmosphere when manufacturing a compound semiconductor MESFET such as GaAs.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a device showing the manufacturing process of GaAsMESFE'1'', and Figure 2 is a GaAsMBSFE using a gate electrode with a double-layer structure to reduce stress.
It is a sectional view of the apparatus showing the manufacturing process of T. 11.21...Semi-insulating GaA3 substrate, 12,24-
...nj-125,26...Refractory metal or refractory metal ceramic, 13.28...Gate electrode, 17゜31...Cap material, 18.32...Source/dray No. 1 Figure Y2 Continuation of figure 1 page @ Inventor Kobashi demoted Kunichi City Shio Research Institute 0 Inventor Takahashi Susumu Kokubunji City Shio Research Institute

Claims (1)

[Claims] 1.711M High melting point metal and high melting point metal silicide exhibiting compressive stress or tensile stress are used as the first layer, and high melting point metal and high melting point metal silicide exhibiting stress in the opposite direction to the first layer are used as the second layer. Overlapping Schottky electrodes are formed on a compound semiconductor, and impurities are introduced by ion implantation using at least the Schottky electrodes as a mask,
A method for manufacturing a compound semiconductor device, characterized in that an n+ layer is formed by subsequent heat treatment.