JPS61111525A - Forming method for electrode of semiconductor element - Google Patents

Forming method for electrode of semiconductor element

Info

Publication number
JPS61111525A
JPS61111525A JP23381884A JP23381884A JPS61111525A JP S61111525 A JPS61111525 A JP S61111525A JP 23381884 A JP23381884 A JP 23381884A JP 23381884 A JP23381884 A JP 23381884A JP S61111525 A JPS61111525 A JP S61111525A
Authority
JP
Japan
Prior art keywords
film
electrode
target
impressed
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23381884A
Other languages
Japanese (ja)
Inventor
Keiji Nagai
永井 慶次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23381884A priority Critical patent/JPS61111525A/en
Publication of JPS61111525A publication Critical patent/JPS61111525A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation

Abstract

PURPOSE:To obtain a tungsten silicide gate electrode for MESFET, which is low resistivity and favorable stability, adhesive, property chemical resistance, accuracy of forming pattern, reliability etc. at high temperature, by a method wherein a metallic alloy film is formed by means that simultaneous spattering to substance of metallic alloy is performed and negative bias is impressed to a semiconductor substrate at the time of spattering. CONSTITUTION:A tungsten target 1 and an Si target 2 are prepared and are impressed with voltage of target bias electrode 6, 6' respectively. A holder 4 is impressed at -10-50V voltage from a holder bias power supply 5. In such a manner, an adhered tungsten silicide film, whose film resistivity is about 20muOMEGAcm, is favorable, and the said film stress is very small tensile stress less than 2X108N/m<2>, then film exfoliation is not happened at all, so warpage of a wafer 3 is small too. Subsequently, an electrode pattern is formed by active ion-etching. In this case, accuracy of forming a photo-resist mask is improved, thus about 1mum thickness electrode pattern is formed accurately.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子の電極形成方法に係り、特Iこ高融
点金属合金電極の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming an electrode of a semiconductor device, and particularly to a method for forming a high melting point metal alloy electrode.

〔従来の技術〕[Conventional technology]

高融点金属合金は、比較的小さいバルク比抵抗、高温で
の安定性、化学的耐性等の性質を有することから、シリ
コンMOSデバイスでは、ポリシリコンにかわる材料と
して、またGaAsMESデバイスでは、アルミニウム
等にかわる材料として、ゲート電極用材料に用いられは
じめている。高融点金属合金の電極用途のための成膜方
法としては、フグ法、化学的気相成長法(CVD法)等
の方法がある。
Refractory metal alloys have properties such as relatively low bulk resistivity, stability at high temperatures, and chemical resistance, so they are used as materials to replace polysilicon in silicon MOS devices, and as materials such as aluminum in GaAs MES devices. As an alternative material, it is beginning to be used as a material for gate electrodes. Film forming methods for high melting point metal alloys for electrode applications include methods such as the blowfish method and chemical vapor deposition method (CVD method).

このうち同時蒸着法では、膜の基板段差被覆性(ステッ
プ・カバレージ)が悪く、電極の段切れを生じやすいと
いう欠点があり、CVD法は装置が開発されてからあま
り期間がなく、一般には用いられておらず、スパッタリ
ング法が一般的である。
Among these methods, the simultaneous vapor deposition method has the disadvantage that the step coverage of the film is poor and the electrode is easily broken, and the CVD method has not been used for a long time since its equipment was developed, so it is not generally used. The sputtering method is common.

しかしながら、スパッタリング法のうち、合金ターゲッ
トを用いた場合、ターゲットの製造過程で不純物が入り
やすく、膜の比抵抗値が高くなったり、放射性不純物に
よる素子の信@性が低下する等の問題のほか、膜の合金
組成比の制御性の点で問題がある。一方、同時スパッタ
法では、高純度の合金構成金属ターゲットの製造が可能
なため、不純物の影響はほとんどなく、また膜の合金組
成比の制御も容易で、半導体素子の電極形成用途として
は最も有望な方法であるが、膜中に多量のスパッタガス
(通常はアルゴンである)がとりこまれるために、膜応
力が大きくなる。この膜応力が大きい場合、特に膜の付
着力と同等以上の場合には膜の剥離が生じたり、また基
板にそりを生じ、通常のリングラフィ技術により電極パ
ターンの形成を行なう際に障害となり、パターン精度の
低下や更には基板の彼れを生じる場合がある。実際に、
同時スパッタにより形成した膜厚的4oooAのタング
ステン−シリサイド膜では、5 X 10”N/TF?
程度の引張り応力が生じており、はぼ膜剥離の限界近い
膜応力となっている。
However, when using an alloy target in the sputtering method, impurities tend to enter during the target manufacturing process, resulting in problems such as increasing the resistivity of the film and reducing device reliability due to radioactive impurities. However, there is a problem in the controllability of the alloy composition ratio of the film. On the other hand, the simultaneous sputtering method makes it possible to manufacture highly pure alloyed metal targets, so there is almost no influence from impurities, and the alloy composition ratio of the film can be easily controlled, making it the most promising application for forming electrodes in semiconductor devices. However, since a large amount of sputtering gas (usually argon) is incorporated into the film, film stress increases. If this film stress is large, especially if it is equal to or greater than the adhesion force of the film, the film may peel off or the substrate may warp, which becomes an obstacle when forming an electrode pattern using normal phosphorography technology. This may cause a decrease in pattern accuracy or even deformation of the substrate. actually,
A tungsten-silicide film with a film thickness of 400A formed by simultaneous sputtering has a thickness of 5 x 10"N/TF?
A certain amount of tensile stress is generated, and the membrane stress is close to the limit of membrane peeling.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明の目的は、同時スパッタ法による高融点金属合金
膜の膜応力が大きくなるという前記の問題点を解消し、
比抵抗が低く、高温での安定性、接着性、化学耐性、パ
ターン形成精度、信頼性等は良好にした半導体素子の電
極形成方法を提供することにある。
An object of the present invention is to solve the above-mentioned problem that the film stress of a high melting point metal alloy film increases due to simultaneous sputtering,
The object of the present invention is to provide a method for forming electrodes for semiconductor devices, which has low specific resistance, and has good stability at high temperatures, adhesion, chemical resistance, pattern formation accuracy, reliability, etc.

〔問題点を解決するための手段〕 本発明の構成は、高融点金属合金の電極を有する半導体
素子の電極形成方法において、前記金属合金の構成物質
の同時スパッタを行ない、かつスパッタ時に半導体基板
に負バイアスを印加して前記金属合金の膜を形成するこ
とを特徴とする。
[Means for Solving the Problems] The structure of the present invention is that, in a method for forming an electrode of a semiconductor element having an electrode of a high-melting point metal alloy, constituent materials of the metal alloy are simultaneously sputtered and sputtering is performed on a semiconductor substrate during sputtering. The method is characterized in that the film of the metal alloy is formed by applying a negative bias.

〔実施例〕〔Example〕

次に図面を参照しながら本発明の詳細な説明する。 Next, the present invention will be described in detail with reference to the drawings.

本発明の実施例として、MESFETのタングステン・
シリサイド・ゲート電極の形成方法を挙げる。
As an embodiment of the present invention, MESFET tungsten
A method for forming a silicide gate electrode will be described.

まず、G a A s半絶縁性基板にn9動作層を形成
したウェハ表面全面に同時スパッタにより、タングステ
ン・シリサイドを被着する。従来の同時スパッタの場合
、ウェハはアース電位に保たれたホルダにセットされた
状態で、スパッタが行なわれていた。この構造の場合、
ウェハに被着されたタングステン・シリサイド膜の膜応
力は強い引張り応力を示すことが実験的に確認されてい
る。この応力の発生原因として、膜中にとりこまれるア
ルゴン・ガスが考えられることから、ホルダの電位を変
えた場合の膜応力を調査したところ、ホルダの電位が一
1OV乃至−30Vの場合に膜応力がほぼゼロとなった
First, tungsten silicide is deposited by simultaneous sputtering on the entire surface of a wafer in which an N9 active layer is formed on a GaAs semi-insulating substrate. In the case of conventional simultaneous sputtering, sputtering is performed with the wafer set in a holder kept at ground potential. For this structure,
It has been experimentally confirmed that the film stress of a tungsten silicide film deposited on a wafer exhibits strong tensile stress. Argon gas trapped in the film is thought to be the cause of this stress, so we investigated the film stress when the holder potential was changed, and found that the film stress was has become almost zero.

第1図は本発明の実施例で用いる同時スパッタ装置の模
式図である。同図において、主な特徴であるホルダーバ
イアス電源5は、ホルダ4に一1OV乃至−30Vの電
圧を印加することが可能である。GaAs MES F
ET  のゲート電極用途のタングステン・シリサイド
同時スパッタの条件例として1才、以下の条件があげら
れる。アルゴンガス圧は10□T Or rs タング
ステンとシリコンとのスパッタ速度は5:3、ホルダー
バイアスは一2Ov、膜厚は5ooof 0以上の条件
で被着されたタングステン・シリサイド膜は、層比抵抗
は約20μΩ鋼と良好で、膜応力は2 X 10” N
/yj以下の非常に小さな引張り応力で、膜の剥離は全
くなくウェハ3の反りも小さい。次に、フォトレジスト
をマスクとして、8F、ガスのりアクティブ・イオンエ
ツチングにより電極パターンを形成する。この場合、ウ
ェハ3の反りが小さいため、フォトレジストのマスク形
成精度が良好となり、1μ、程度の電極パターンが精度
よく形成される。
FIG. 1 is a schematic diagram of a simultaneous sputtering apparatus used in an embodiment of the present invention. In the figure, the holder bias power supply 5, which is the main feature, can apply a voltage of -1OV to -30V to the holder 4. GaAs MES F
Examples of conditions for simultaneous tungsten and silicide sputtering for gate electrode applications in ET include the following conditions. Argon gas pressure is 10□T or rs Sputtering rate of tungsten and silicon is 5:3, holder bias is -2Ov, film thickness is 5ooof The tungsten silicide film deposited under conditions of 0 or more has a layer resistivity of Approximately 20 μΩ steel and good membrane stress of 2 x 10”N
With a very small tensile stress of /yj or less, there is no peeling of the film and the warping of the wafer 3 is small. Next, using the photoresist as a mask, an electrode pattern is formed by 8F gas paste active ion etching. In this case, since the warpage of the wafer 3 is small, the photoresist mask formation accuracy is good, and an electrode pattern of about 1 μm can be formed with high accuracy.

尚、第1図において、タングステン・ターゲット1とシ
リコン・ターゲット2とが用意され、それぞれターゲッ
ト・バイアス電源6,6′の電圧が印加される。さらに
、排気ポンプ7と、アルゴン・ガス導入口8とが設けら
れている。
In FIG. 1, a tungsten target 1 and a silicon target 2 are prepared, and voltages from target bias power supplies 6 and 6' are applied to them, respectively. Furthermore, an exhaust pump 7 and an argon gas inlet 8 are provided.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、金属合金膜の膜
応力を小さくできるという効果が得られる。
As explained above, according to the present invention, the effect of reducing the film stress of the metal alloy film can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例で用いる高融点金属合金の同時
スパッタ装置の模式図である。 同図において、1・・・・・・タングステン・ターゲッ
ト、2・・・・・・シリコン・ターゲット、3・・・・
・・半導体素子ウェハ、4・・・・・−ウェハーホルダ
、5・・・・・・ホルダーバイアス電源、6・・・・・
・ターゲットΦバイアス電源、7・・・・・−排気ポン
プ、8・・・・・・アルゴンガス導入口。 代理人 弁理士  内 原   音票T”:i’:S、
・l 第1図
FIG. 1 is a schematic diagram of a high melting point metal alloy simultaneous sputtering apparatus used in an embodiment of the present invention. In the same figure, 1...Tungsten target, 2...Silicon target, 3...
...Semiconductor element wafer, 4...-Wafer holder, 5...Holder bias power supply, 6...
・Target Φ bias power supply, 7...-exhaust pump, 8...Argon gas inlet. Agent Patent Attorney Uchihara Voice slip T”:i’:S,
・l Figure 1

Claims (1)

【特許請求の範囲】[Claims]  高融点金属合金の電極を有する半導体素子の電極形成
方法において、前記高融点金属合金の構成物質の同時ス
パッタを行ない、かつスパッタ時に半導体基板に負バイ
アスを印加して前記高融点金属合金の膜を形成すること
を特徴とする半導体素子の電極形成方法。
In a method for forming an electrode of a semiconductor device having an electrode of a high melting point metal alloy, constituent materials of the high melting point metal alloy are simultaneously sputtered, and a negative bias is applied to the semiconductor substrate during sputtering to form a film of the high melting point metal alloy. 1. A method for forming electrodes of a semiconductor element, the method comprising: forming an electrode of a semiconductor element;
JP23381884A 1984-11-06 1984-11-06 Forming method for electrode of semiconductor element Pending JPS61111525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23381884A JPS61111525A (en) 1984-11-06 1984-11-06 Forming method for electrode of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23381884A JPS61111525A (en) 1984-11-06 1984-11-06 Forming method for electrode of semiconductor element

Publications (1)

Publication Number Publication Date
JPS61111525A true JPS61111525A (en) 1986-05-29

Family

ID=16961048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23381884A Pending JPS61111525A (en) 1984-11-06 1984-11-06 Forming method for electrode of semiconductor element

Country Status (1)

Country Link
JP (1) JPS61111525A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS636837A (en) * 1986-06-26 1988-01-12 Agency Of Ind Science & Technol Manufscture of ohmic electrode
JPH04357827A (en) * 1990-02-12 1992-12-10 American Teleph & Telegr Co <Att> Electronic element and manufacture thereof
JP2003001057A (en) * 2001-06-26 2003-01-07 Yokoi Kogyo Kk Deodorization apparatus for malodorous gas

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS636837A (en) * 1986-06-26 1988-01-12 Agency Of Ind Science & Technol Manufscture of ohmic electrode
JPH04357827A (en) * 1990-02-12 1992-12-10 American Teleph & Telegr Co <Att> Electronic element and manufacture thereof
JP2003001057A (en) * 2001-06-26 2003-01-07 Yokoi Kogyo Kk Deodorization apparatus for malodorous gas

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