JPS61224423A - Reactive ion etching appratus - Google Patents
Reactive ion etching appratusInfo
- Publication number
- JPS61224423A JPS61224423A JP6540785A JP6540785A JPS61224423A JP S61224423 A JPS61224423 A JP S61224423A JP 6540785 A JP6540785 A JP 6540785A JP 6540785 A JP6540785 A JP 6540785A JP S61224423 A JPS61224423 A JP S61224423A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- etched
- wafer
- semiconductor wafer
- reactive ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/3255—Material
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
- H01J2237/3341—Reactive etching
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体ウェーハまたは半導体ウェーハ上の被エ
ツチング物をエツチングする反応性イオンエツチング装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a reactive ion etching apparatus for etching a semiconductor wafer or an object to be etched on a semiconductor wafer.
〔発明の技術的背景とその問題点９ 反応性イオンエツチング装置を第８図に示す。[Technical background of the invention and its problems 9 A reactive ion etching apparatus is shown in FIG.
エツチング室２上部には反応ガスを導入する導入管４が
設けられている。このエツチング室２内には電極６が設
けられ、この電極６上には複数の半導体ウェーハ８が載
置されている。エツチング時には、このエツチング室２
は真空ポンプ（図示せず）により真空にされ、導入管４
から反応ガスを導入する。このエツチング室２は上部電
極を兼ねていて接地され、エツチング室２と電極６間に
所定電力を印加することにより、物理的反応または科学
的反応により半導体ウェーハ８上の物質をエツチングす
る。At the top of the etching chamber 2, an introduction pipe 4 for introducing a reaction gas is provided. An electrode 6 is provided within the etching chamber 2, and a plurality of semiconductor wafers 8 are placed on the electrode 6. During etching, this etching chamber 2
is evacuated by a vacuum pump (not shown), and the inlet tube 4 is evacuated by a vacuum pump (not shown).
Reactant gas is introduced from This etching chamber 2 also serves as an upper electrode and is grounded, and by applying a predetermined power between the etching chamber 2 and the electrode 6, the material on the semiconductor wafer 8 is etched by a physical reaction or a chemical reaction.
従来の反応性イオンエツチング装置の電極６のウェーハ
載置部の形状を第９図に示す。第８図に示すように平板
の電極６上にテフロンで作られた絶縁板１０を介して半
導体ウェーハ８が載置されている。しかしこのような従
来の電極６の形状では、半導体ウェーハ８自体の厚さの
ために半導体ウェーハ８の周辺において第９図に示すよ
うに電界が集中し、エツチング速度が中央部より速くな
り、エツチングが均一におこなわれないという問題があ
った。FIG. 9 shows the shape of the wafer mounting portion of the electrode 6 of a conventional reactive ion etching apparatus. As shown in FIG. 8, a semiconductor wafer 8 is placed on a flat electrode 6 with an insulating plate 10 made of Teflon interposed therebetween. However, with such a conventional shape of the electrode 6, the electric field is concentrated at the periphery of the semiconductor wafer 8 as shown in FIG. There was a problem that the process was not performed uniformly.
このような電界集中を補償するため、第１０図に示すよ
うに電極６および絶縁板１０をウェーハ載置部が低くな
るように形成したものがある。すなわち、半導体ウェー
ハ８表面が絶縁板１０の表面より少し低くなるように座
ぐり１２を形成し、ウェーハ周辺部の電界集中を補正し
、均一な電界を得ている。電界が均一になれば均一なエ
ツチングが期待できる。In order to compensate for such electric field concentration, there is a device in which the electrode 6 and the insulating plate 10 are formed so that the wafer mounting portion is lowered, as shown in FIG. That is, the counterbore 12 is formed so that the surface of the semiconductor wafer 8 is slightly lower than the surface of the insulating plate 10, thereby correcting the electric field concentration around the wafer and obtaining a uniform electric field. If the electric field becomes uniform, uniform etching can be expected.
エツチングが物理的反応、すなわち反応ガスのイオンお
よびラジカルが半導体ウェーハ８面上に衝突することに
より物理的に削られることによりなされる場合には、電
界が均一になることで均一なエツチングがなされる。し
かしながら例えば金属のようにエツチングが科学的反応
によるものが主要な割合を占める場合には、反応ガス中
のエツチング種（反応ガス中で直接化学的反応に関係す
るイオンやラジカルのこと）の分布が問題となる。When etching is performed by a physical reaction, that is, when ions and radicals of a reaction gas collide with the surface of the semiconductor wafer and physically scrape it, uniform etching is achieved by making the electric field uniform. . However, in cases where etching is mainly due to chemical reactions, such as with metals, the distribution of etching species (ions and radicals directly involved in chemical reactions in the reaction gas) in the reaction gas changes. It becomes a problem.
例えばアルミニウムの場合、エツチングは主として下記
の化学式による化学反応によるものが支配的である。For example, in the case of aluminum, etching is mainly caused by a chemical reaction according to the following chemical formula.
したがってｃｎ”やＣｊｌ というエツチング種の分
布が均一でないとエツチング速度も均一でなくなる。Therefore, if the distribution of etching species such as cn'' and Cjl is not uniform, the etching rate will also not be uniform.
第１０図に示すような構造の電極６を有する反応性イオ
ンエツチング装置でアルミニウムをエツチングすると、
電界は均一であり、また反応ガスも均一に分布するので
、最初は均一にエツチングされる。しかし反応が進むに
つれて、半導体ウェーハ８の真上では反応を起こしてエ
ツチング種が減少するが、半導体ウェーハ８のない周辺
部では反応せずエツチング種がほとんど減少しない。こ
の結果エツチング種濃度が第１１図に示すように半導体
ウェーハ８の周辺はど濃くなる。エツチング種濃度の分
布に応じてエツチング速度も分布するため、均一なエツ
チングがおこなわれないという問題があった。When aluminum is etched using a reactive ion etching device having an electrode 6 having the structure shown in FIG.
Since the electric field is uniform and the reactive gas is uniformly distributed, etching is uniform at first. However, as the reaction progresses, a reaction occurs directly above the semiconductor wafer 8 and the number of etching species decreases, but a reaction does not occur in the peripheral area where the semiconductor wafer 8 is not present, and the number of etching species hardly decreases. As a result, the etching species concentration becomes very high around the semiconductor wafer 8, as shown in FIG. Since the etching rate varies depending on the distribution of the etching species concentration, there is a problem that uniform etching is not performed.
本発明は上記事情を考慮してなされたものでつニー八面
内で均一にエツチングすることができる反応性イオンエ
ツチング装置を提供することを目的とする。The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a reactive ion etching apparatus capable of uniformly etching within eight surfaces of a knee.
上記目的を達成するために本発明による反応性イオンエ
ツチング装置は、エツチング時に反応ガス−のエツチン
グ種を被エツチング物とほぼ同様の割合で減少させる物
質を、電極上の少なくともウェーへの周辺部に設けたこ
とを特徴とする。In order to achieve the above object, the reactive ion etching apparatus according to the present invention applies a substance that reduces the etching species of the reactive gas during etching at approximately the same rate as the object to be etched, to at least the peripheral area of the wafer on the electrode. It is characterized by having been established.
本発明の一実施例による反応性イオンエツチング装置の
ウェーハ載置部の構造を第１図に示す。FIG. 1 shows the structure of a wafer mounting section of a reactive ion etching apparatus according to an embodiment of the present invention.
本実施例では半導体ウェーハ８の周囲にエツチング補正
リング２０が設けられている点に特徴がある。すなわち
、電極６と絶縁板１０の座ぐりを半導体ウェーハ８の外
径より大きめにとり、座ぐりによる段差部１２と半導体
ウェーハ８との間に補正リング２０を設ける。This embodiment is characterized in that an etching correction ring 20 is provided around the semiconductor wafer 8. That is, the counterbore of the electrode 6 and the insulating plate 10 is made larger than the outer diameter of the semiconductor wafer 8, and the correction ring 20 is provided between the stepped portion 12 formed by the counterbore and the semiconductor wafer 8.
この補正リング２０の材料は、被エツチング物により異
なるが、少なくとも被エツチング物とほぼ同様の割合で
反応ガスのエツチング種を減少させるものであればよい
。被エツチング物とエツチング率がほぼ同じであればこ
の条件を満足する。The material of the correction ring 20 varies depending on the object to be etched, but it may be any material that reduces the etching species of the reactive gas at least at a rate substantially the same as that of the object to be etched. This condition is satisfied if the etching rate is approximately the same as that of the object to be etched.
この補正リング２０を被エツチング物または被エツチン
グ物を主成分とする物でつくればなお望ましい。It is more desirable if the correction ring 20 is made of a material to be etched or a material whose main component is the material to be etched.
例えば被エツチング物がアルミニウムの場合、補正リン
グ２０の材料としては、■アルミニウム（Ａρ）、■ア
ルミニウムを主成分とする物質、■チタンタングステン
（ＴｉＷ）、■チタンタングステンを主成分とする物質
が望ましい。また被エツチング物がモリブデンシリサイ
ド
（Ｍ ｏ Ｓ ｉ ２ ）の場合、補正リング２０の材
料としては、■モリブデンシリサイド、■モリブデンシ
リサイドを主成分とする物質、■シリコン（Ｓ ｉ ）
、■シリコンを主成分とする物質、■ポリシリコンが
望ましい。For example, when the object to be etched is aluminum, the correction ring 20 is desirably made of: ■ aluminum (Aρ), ■ a substance whose main component is aluminum, ■ titanium tungsten (TiW), and ■ a substance whose main component is titanium tungsten. . When the object to be etched is molybdenum silicide (M o Si 2 ), the materials for the correction ring 20 include: ■ molybdenum silicide, ■ a substance whose main component is molybdenum silicide, and ■ silicon (S i ).
, ■A substance whose main component is silicon, and ■Polysilicon are desirable.
このように本実施例によれば、半導体ウェーハの周辺に
も半導体ウェーハ上と同様にエツチング種を減少させる
物質があるため、エツチング種濃度の不均一な部分がよ
り外側に移り、第２図に示づようにｆ１体ウェーハ８上
では、エツチング物濃度が均一となる。したがって半導
体ウェーハが均一にエツチングされる。As described above, according to this embodiment, since there is a substance that reduces etching species around the semiconductor wafer as well as on the semiconductor wafer, the area where the concentration of etching species is uneven is moved to the outside, and as shown in FIG. As shown, the etching material concentration on the f1 wafer 8 is uniform. Therefore, the semiconductor wafer is etched uniformly.
補正リング２０の形状は、エツチング室の形状、電極間
路１Ｉｉｌｉ等にも依存しており、特定できないが、被
エツチング物がアルミニウムで補正リングも純
よアルミニウム（９９，９９５％〉を用いた場合、第３
図に示す断面形状が最適であった。すなわら、電極６の
座ぐりによる段差を５＃ＩＩＩ＋とし、絶縁板１０の厚
さを２闇とする。補正リング２０はリング幅１５ＩＭＲ
，厚さ５＃ｌｌ１１であり、半導体ウェーハ８側に３０
度のテーパをつけている。このときのエツチング速度の
実測値を第４図の曲線■に示す。The shape of the correction ring 20 depends on the shape of the etching chamber, the interelectrode path 1Iili, etc., and cannot be specified, but if the object to be etched is aluminum and the correction ring is pure,
When using aluminum (99,995%), the third
The cross-sectional shape shown in the figure was optimal. That is, the level difference due to the counterbore of the electrode 6 is set to 5#III+, and the thickness of the insulating plate 10 is set to 2mm. The correction ring 20 has a ring width of 15 IMR.
, thickness 5#ll11, and 30 mm on the semiconductor wafer 8 side.
It has a degree of taper. The measured value of the etching rate at this time is shown in curve (2) in FIG.
ウェーハ上でエツチング速度が均一であることがわかる
。特に従来のエツチング速度（曲線■）では中央と周辺
で１０％以上の差があったが、曲線■では２．４％のば
らつきに抑えることができた。It can be seen that the etching rate is uniform over the wafer. In particular, in the conventional etching speed (curve ■), there was a difference of 10% or more between the center and the periphery, but in curve ■, the variation could be suppressed to 2.4%.
なおエツチング条件は、平行平板型の陰極結合型の反応
性イオンエツチング装置を用い、反応ガスＳ：ＣＩ
流量１１００８ＣＣ，エツチング圧力１００ｍＴｏｒ
ｒ、ＲＦ％をカフ００■である。またエツチングされた
半導体ウェーハはシリコン単結晶基板上に５０００人の
熱酸化膜を介して１．０μｍのアルミニウム膜（Ａｌｌ
−２％５ｉｌｌｉ）を通常のスパッタ法で被着したもの
である。エツチングのマスキングにはフォトレジストを
使用し、そのパターニングには通常のフォトソングラフ
ィの手法を用いた。The etching conditions were as follows: a parallel plate cathode-coupled reactive ion etching device was used, and the reaction gas S:CI
Flow rate 11008CC, etching pressure 100mTor
r, RF% is cuff 00■. In addition, the etched semiconductor wafer is coated with a 1.0 μm aluminum film (All
-2% 5illi) was deposited by a conventional sputtering method. Photoresist was used for etching masking, and regular photolithography was used for patterning.
本発明による反応性イオンエツチング装置の電極構造の
変型例を第５図から第７図に示す。第５図は電極６と絶
縁板１０の座ぐりの段差部に傾斜を設け、半導体ウェー
ハ８の周辺にスパッタ等により補正リングと同様の物質
からなるエツチング補正膜２２を形成したものである。Modifications of the electrode structure of the reactive ion etching apparatus according to the present invention are shown in FIGS. 5 to 7. In FIG. 5, the stepped portion of the counterbore between the electrode 6 and the insulating plate 10 is sloped, and an etching correction film 22 made of the same material as the correction ring is formed around the semiconductor wafer 8 by sputtering or the like.
この補正膜２２もエツチング時には前述の補正リングと
同様の作用をするので、エツチング種の均一性、ひいて
はエツチングの均一性が確保される。第５図では半導体
ウェーハ８下には補正膜２２を形成しないようにしたが
、第６図に示すように半導体ウェー７１８の下まで膜２
４を形成してもよい。また第７図に示ずように座ぐりを
設けず、絶縁板１０上に膜２６を形成してもほぼ同様の
効果がある。Since this correction film 22 also functions in the same manner as the above-mentioned correction ring during etching, the uniformity of the etching species and thus the uniformity of etching is ensured. In FIG. 5, the correction film 22 is not formed under the semiconductor wafer 8, but as shown in FIG.
4 may be formed. Further, as shown in FIG. 7, substantially the same effect can be obtained even if the film 26 is formed on the insulating plate 10 without providing a counterbore.
なお、エツチング種が均一に減少させることができても
、反応ガスそのものの分布が不均一であれば、エツチン
グの均一性が確保できない。反応ガスの導入管４を第８
図に示すように中央にだけおくと、特にウェーハ間のエ
ツチングに差が出る可能性がある。このことを防止する
ためには、ウェーハごとにその真上に反応ガスの導入口
を設けるようにすればよい。Incidentally, even if the etching species can be uniformly reduced, if the distribution of the reactive gas itself is uneven, the uniformity of etching cannot be ensured. The reaction gas introduction pipe 4 is connected to the eighth
If it is placed only in the center as shown in the figure, there may be differences in etching, especially between wafers. In order to prevent this, a reactive gas inlet may be provided just above each wafer.
また本発明による反応性イオンエツチング装置でエツチ
ングする半導体ウェーハとしてはシリコン単結晶基板の
他、ガリウムヒ素単結晶基板でもよい。Further, the semiconductor wafer to be etched by the reactive ion etching apparatus according to the present invention may be a gallium arsenide single crystal substrate in addition to a silicon single crystal substrate.
以上の通り本発明によればウェーハ面内で被エツチング
物を均一にエツチングすることができる。As described above, according to the present invention, the object to be etched can be etched uniformly within the wafer surface.
第１図は本発明の一実施例による反応性イオンエツチン
グ装置の電極のウェーハ載置部の形状を示す図、第２図
は同反応性イオンエツチング装置におけるエツチング種
濃度分布を示すグラフ、第３図は同ウェーハ載置部の最
適な形状を示す図、第４図は同ウェーハ載置部を最適な
形状とした場合のエツチング速度分布を示すグラフ、第
５図、第６図、第７図は同ウェーハ載置部の変型例を示
す図、第８図は反応性イオンエツチング装置を示す図、
第９図、第１０図は従来の反応性イオンエツチング装置
の電極のウェーハ載置部の形状を示す図、第１１図は同
反応性イオンエツチング装置におけるエツチング種濃度
を示すグラフである。
２・・・エツチング室、４・・・導入管、６・・・電極
、８・・・ウェーハ、１０・・・絶縁板、１２・・・段
差部、２０・・・補正リング、２２，２４．２６・・・
エツチング補正膜。
第１図
（Ｑ）
第８図
第１０図
只FIG. 1 is a diagram showing the shape of the wafer mounting part of the electrode of a reactive ion etching apparatus according to an embodiment of the present invention, FIG. 2 is a graph showing the etching species concentration distribution in the same reactive ion etching apparatus, and FIG. The figure shows the optimal shape of the wafer platform, Figure 4 is a graph showing the etching rate distribution when the wafer platform is set to the optimal shape, and Figures 5, 6, and 7. 8 is a diagram showing a modified example of the same wafer mounting section, FIG. 8 is a diagram showing a reactive ion etching device,
9 and 10 are diagrams showing the shape of the wafer mounting portion of the electrode of a conventional reactive ion etching apparatus, and FIG. 11 is a graph showing the etching species concentration in the same reactive ion etching apparatus. 2... Etching chamber, 4... Introducing tube, 6... Electrode, 8... Wafer, 10... Insulating plate, 12... Step portion, 20... Correction ring, 22, 24 .26...
Etching correction film. Figure 1 (Q) Figure 8 Figure 10 Only
Claims (1)
一方の電極上に載置されたウェーハに前記反応ガスをあ
てて前記ウェーハ上の被エッチング物をエッチングする
反応性イオンエッチング装置において、 エッチング時に前記反応ガスのエッチング種を前記被エ
ッチング物とほぼ同様の割合で減少させる物質を、前記
電極上の少なくとも前記ウェーハの周辺部に設けたこと
を特徴とする反応性イオンエッチング装置。 ２、特許請求の範囲第１項記載の装置において、前記ウ
ェーハ上における電界が均一になるように、前記電極の
前記ウェーハが載置される部分の周辺が、ほぼ前記ウェ
ーハの表面より少し高く形成されていることを特徴とす
る反応性イオンエッチング装置。 ３、特許請求の範囲第１項または第２項記載の装置にお
いて、前記物質は前記被エッチング物とほぼ同じエッチ
ング速度であることを特徴とする反応性イオンエッチン
グ装置。 ４、特許請求の範囲第３項記載の装置において、前記物
質は、前記被エッチング物または前記被エッチング物を
主成分とすることを特徴とする反応性イオンエッチング
装置。[Claims] 1. A reactive gas is filled between the electrodes to which a predetermined power is applied,
In a reactive ion etching apparatus that applies the reactive gas to a wafer placed on one electrode to etch an object to be etched on the wafer, the etching species of the reactive gas during etching is substantially the same as that of the object to be etched. A reactive ion etching apparatus characterized in that a substance is provided on the electrode at least in a peripheral area of the wafer. 2. In the apparatus according to claim 1, the periphery of the portion of the electrode on which the wafer is placed is formed to be slightly higher than the surface of the wafer so that the electric field on the wafer is uniform. A reactive ion etching device characterized by: 3. A reactive ion etching apparatus according to claim 1 or 2, wherein the material has an etching rate substantially the same as that of the object to be etched. 4. A reactive ion etching apparatus according to claim 3, wherein the substance contains the object to be etched or the object to be etched as a main component.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6540785A JPS61224423A (en) | 1985-03-29 | 1985-03-29 | Reactive ion etching appratus |
| GB8607979A GB2175542B (en) | 1985-03-29 | 1986-04-01 | Reactive ion etching device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6540785A JPS61224423A (en) | 1985-03-29 | 1985-03-29 | Reactive ion etching appratus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61224423A true JPS61224423A (en) | 1986-10-06 |
Family
ID=13286140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6540785A Pending JPS61224423A (en) | 1985-03-29 | 1985-03-29 | Reactive ion etching appratus |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS61224423A (en) |
| GB (1) | GB2175542B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992007377A1 (en) * | 1990-10-23 | 1992-04-30 | Genus, Inc. | Sacrificial metal etchback system |
| JPH0574737A (en) * | 1990-04-25 | 1993-03-26 | Internatl Business Mach Corp <Ibm> | Processing apparatus having voltage driving electrode and particle collecting method |
| US5292399A (en) * | 1990-04-19 | 1994-03-08 | Applied Materials, Inc. | Plasma etching apparatus with conductive means for inhibiting arcing |
| US5556500A (en) * | 1994-03-03 | 1996-09-17 | Tokyo Electron Limited | Plasma etching apparatus |
| US5681419A (en) * | 1994-12-28 | 1997-10-28 | Hyundai Electronics Industries Co., Ltd. | Reactive ion etching apparatus |
| US5951814A (en) * | 1996-04-22 | 1999-09-14 | Nisshinbo Industries, Inc. | Electrode for plasma etching |
| US6171974B1 (en) * | 1991-06-27 | 2001-01-09 | Applied Materials, Inc. | High selectivity oxide etch process for integrated circuit structures |
| US6184150B1 (en) * | 1992-09-08 | 2001-02-06 | Applied Materials Inc. | Oxide etch process with high selectivity to nitride suitable for use on surfaces of uneven topography |
| JP2005277369A (en) * | 2003-09-05 | 2005-10-06 | Tokyo Electron Ltd | Focus ring and plasma processing apparatus |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4786359A (en) * | 1987-06-24 | 1988-11-22 | Tegal Corporation | Xenon enhanced plasma etch |
| US5498313A (en) * | 1993-08-20 | 1996-03-12 | International Business Machines Corp. | Symmetrical etching ring with gas control |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52137266A (en) * | 1976-05-12 | 1977-11-16 | Nichiden Varian Kk | Method of sputter etching |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4375385A (en) * | 1982-03-25 | 1983-03-01 | Rca Corporation | Plasma etching of aluminum |
-
1985
- 1985-03-29 JP JP6540785A patent/JPS61224423A/en active Pending
-
1986
- 1986-04-01 GB GB8607979A patent/GB2175542B/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52137266A (en) * | 1976-05-12 | 1977-11-16 | Nichiden Varian Kk | Method of sputter etching |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5292399A (en) * | 1990-04-19 | 1994-03-08 | Applied Materials, Inc. | Plasma etching apparatus with conductive means for inhibiting arcing |
| JPH0574737A (en) * | 1990-04-25 | 1993-03-26 | Internatl Business Mach Corp <Ibm> | Processing apparatus having voltage driving electrode and particle collecting method |
| WO1992007377A1 (en) * | 1990-10-23 | 1992-04-30 | Genus, Inc. | Sacrificial metal etchback system |
| US5330607A (en) * | 1990-10-23 | 1994-07-19 | Genus, Inc. | Sacrificial metal etchback system |
| US6171974B1 (en) * | 1991-06-27 | 2001-01-09 | Applied Materials, Inc. | High selectivity oxide etch process for integrated circuit structures |
| US6184150B1 (en) * | 1992-09-08 | 2001-02-06 | Applied Materials Inc. | Oxide etch process with high selectivity to nitride suitable for use on surfaces of uneven topography |
| US5556500A (en) * | 1994-03-03 | 1996-09-17 | Tokyo Electron Limited | Plasma etching apparatus |
| US5681419A (en) * | 1994-12-28 | 1997-10-28 | Hyundai Electronics Industries Co., Ltd. | Reactive ion etching apparatus |
| US5951814A (en) * | 1996-04-22 | 1999-09-14 | Nisshinbo Industries, Inc. | Electrode for plasma etching |
| JP2005277369A (en) * | 2003-09-05 | 2005-10-06 | Tokyo Electron Ltd | Focus ring and plasma processing apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8607979D0 (en) | 1986-05-08 |
| GB2175542A (en) | 1986-12-03 |
| GB2175542B (en) | 1989-06-28 |
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