JPH0193149A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0193149A
JPH0193149A JP62250351A JP25035187A JPH0193149A JP H0193149 A JPH0193149 A JP H0193149A JP 62250351 A JP62250351 A JP 62250351A JP 25035187 A JP25035187 A JP 25035187A JP H0193149 A JPH0193149 A JP H0193149A
Authority
JP
Japan
Prior art keywords
wiring
layer
film
bump electrode
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62250351A
Other languages
Japanese (ja)
Inventor
Shigeru Harada
繁 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62250351A priority Critical patent/JPH0193149A/en
Priority to DE3830131A priority patent/DE3830131A1/en
Publication of JPH0193149A publication Critical patent/JPH0193149A/en
Pending legal-status Critical Current

Links

Classifications

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the generation of peeling between a wiring and a bump electrode by a method wherein the wiring consisting of Al or Al alloy is formed into a laminated structure and the crystal particle diameter of a layer on the side of the bump electrode is set smaller than that of other layer. CONSTITUTION:An active region 22 is formed in the upper part of a semiconductor substrate 21 and a base insulating film 23 is provided thereon. The film 23 has a contact hole 24 at a position, where corresponds to the region 22, of the film 23. A protective insulating film 25 is provided on the film 23 and an aperture 26 is formed on the film 25. The lower part of a bump electrode 27 is arranged on the aperture 26. Bump base metals 28 and 29 are laminated under the lower part of the electrode 27 in order from the side of the substrate 21. On the other hand, a wiring 30 is formed into a laminated structure consisting of two layers of a layer 31 arranged on the side of the substrate 21 and a layer 32 arranged on the side of the electrode 27. Moreover, the wiring is formed of Al or an Al alloy. Moreover, the crystal particle diameter of the layer 32 is set smaller than that of the layer 31. Accordingly, the area of the interface between the crystal grain boundary of the wiring 30 and that of the metal 28 is increased and the adhesion between the wiring 30 and the metal 28 is improved.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、半導体装置に関し、特に、バンプ電極を存
する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device including bump electrodes.

［従来の技術］ 第６図、第７図は従来の半導体装置を示す縦断面図であ
る。[Prior Art] FIGS. 6 and 7 are longitudinal sectional views showing a conventional semiconductor device.

第６図において、半導体基板１は、その上部に活性領域
２を有し、その上面には下地絶縁膜３が設けられている
。下地絶縁膜３には、不純物拡散層２に対応する位置に
コンタクト孔４が形成されている。下地絶縁膜３の上に
は、保護絶縁膜５が形成されており、保護絶縁膜５は所
定位置に開口６を有している。開口６部分には、バンプ
電極７が設けられている。バンプ電極７の下部には、第
１および第２のバンプ下地金属層８．９が設けられてい
る。下地絶縁膜３と保護絶縁膜５との間には、アルミ配
線１０が配置されている。アミ配線１０は、その一部が
コンタクト孔４を通じて不純物拡散層２にオーミック接
触しており、その他部がバンプ電極７の第１のバンプ下
地金属８の下面にオーミック接触している。In FIG. 6, a semiconductor substrate 1 has an active region 2 on its upper part, and a base insulating film 3 is provided on its upper surface. A contact hole 4 is formed in the base insulating film 3 at a position corresponding to the impurity diffusion layer 2 . A protective insulating film 5 is formed on the base insulating film 3, and the protective insulating film 5 has an opening 6 at a predetermined position. A bump electrode 7 is provided in the opening 6 portion. Under the bump electrode 7, first and second bump underlying metal layers 8.9 are provided. An aluminum wiring 10 is arranged between the base insulating film 3 and the protective insulating film 5. A portion of the wire 10 is in ohmic contact with the impurity diffusion layer 2 through the contact hole 4, and the other portion is in ohmic contact with the lower surface of the first bump base metal 8 of the bump electrode 7.

なお、バンプ下地金属８は、たとえばＣｒより形成され
ている。Note that the bump base metal 8 is made of, for example, Cr.

［発明が解決しようとする問題点］ 前記従来の半導体装置をセラミック基板等に実装した場
合において、熱サイクルを印加し、機械的に引き剥がし
試験を行なったところ、アルミ配線１０と第１のバンプ
下地金属８の界面で剥離が発生しやすいという問題が生
じた。[Problems to be Solved by the Invention] When the conventional semiconductor device was mounted on a ceramic substrate, etc., when a thermal cycle was applied and a mechanical peeling test was performed, it was found that the aluminum wiring 10 and the first bump A problem arose in that peeling was likely to occur at the interface of the base metal 8.

そこで、このアルミ配線５とＣｒ膜である第１のバンプ
下地金属８の界面での剥離（以下、Ａｕ−Ｃｒ間剥離と
略す）の発生原因について調査した。その結果、Ａｌ−
Ｃｒ間の付着は、主として、アルミ膜の結晶粒界の部分
で、Ａ９とＣｒ間の相互拡散が起こりやすいことに起因
していることがわかった。Therefore, we investigated the cause of peeling (hereinafter abbreviated as Au-Cr peeling) at the interface between the aluminum wiring 5 and the first bump base metal 8, which is a Cr film. As a result, Al-
It has been found that the adhesion between Cr is mainly due to the fact that interdiffusion between A9 and Cr tends to occur at the grain boundaries of the aluminum film.

第７図に示すアルミ配線１０の結晶粒界１２は、結晶粒
１３内に比べてポーラスであるるため、比較的低温領域
でもＡｌｌ、とＣｒ間の相互拡散部１４が生じやすい。Since the crystal grain boundaries 12 of the aluminum wiring 10 shown in FIG. 7 are more porous than the inside of the crystal grains 13, interdiffusion portions 14 between All and Cr are likely to occur even in a relatively low temperature region.

そのため、結晶粒界１２とバンプ下地金属８との界面（
相互拡散部１４）は、結晶粒１３とバンプ下地金属８の
界面１５に比べて付着力が大きくなるのである。なお、
多結晶構造を有する材料において、結晶粒内と結晶粒界
の拡散係数が大きく異なることについては、古くから知
られている現象である（ＲｏＷ、Ｃａｈｎ著“Ｐｈｙｓ
ｉｃａｌ　　Ｍｅｔａｌｌｕｒｇｙ”　　（Ｎ。Therefore, the interface between the grain boundary 12 and the bump base metal 8 (
The mutual diffusion portion 14) has a greater adhesion force than the interface 15 between the crystal grain 13 and the bump base metal 8. In addition,
It has been known for a long time that in materials with a polycrystalline structure, the diffusion coefficients within a grain and at a grain boundary are significantly different (RoW, Cahn's “Phys.
ical Metallurgy” (N.

ｒｔｈ−Ｈｏｌｌａｎｄ））。rth-Holland)).

」二連のような理由から、従来の構成では、アルミ配線
１０とバンプ下地金属８との界面において、強い付着力
が得られるのはわずかな部分となる。For reasons such as ``double connection'', in the conventional configuration, strong adhesive force is obtained only in a small portion at the interface between the aluminum wiring 10 and the bump base metal 8.

このため、この界面で剥離が発生しやすくなるものと考
えられる。これは、これまでの通常のデバ°　　イスで
は問題とはされなかったが、より苛酷な条件下で使用さ
れる高信頼性を要求されるデバイスでは問題となってく
る。Therefore, it is thought that peeling is likely to occur at this interface. This has not been a problem in conventional devices, but it has become a problem in devices that are used under harsher conditions and require high reliability.

この発明は、上記のような問題点を解消するためになさ
れたもので、アルミ配線とバンプ電極との間での剥離の
発生を防止し、苛酷な条件下でも高い信頼性を有する半
導体装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it prevents the occurrence of peeling between aluminum wiring and bump electrodes, and provides a semiconductor device that has high reliability even under severe conditions. The purpose is to obtain.

［問題点を解決するための手段］ この発明に係る半導体装置は、活性領域ををする半導体
基板と、外部接続のためのバンプ電極と、活性領域とバ
ンプ電極とを電気的に接続するアルミあるいはアルミ合
金からなる配線とを含む半導体装置であって、前記配線
が積層構造であり、そのバンプ電極側の層の結晶粒径が
他の層よりも小さく設定されていることを特徴としてい
る。[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor substrate forming an active region, a bump electrode for external connection, and an aluminum or aluminum film for electrically connecting the active region and the bump electrode. A semiconductor device including a wiring made of an aluminum alloy, wherein the wiring has a layered structure, and the crystal grain size of the layer on the bump electrode side is set smaller than that of the other layers.

なお、前記配線と接するバンプ電極の下地金属は、たと
えば、クロム、チタン、バナジウム、モリブデン、タン
グステン、ニクロムあるいはこれらの元素を含む化合物
のいずれかである。また、前記配線のバンプ電極側の層
として、たとえば、窒素、酸素、水素、水の１群から選
ばれた少なくとも１つの反応性ガスを混入した膜が用い
られる。Note that the base metal of the bump electrode in contact with the wiring is, for example, chromium, titanium, vanadium, molybdenum, tungsten, nichrome, or a compound containing these elements. Further, as the layer on the bump electrode side of the wiring, for example, a film mixed with at least one reactive gas selected from the group consisting of nitrogen, oxygen, hydrogen, and water is used.

あるいは、前記配線のバンプ電極側の層として、銅、チ
タン、ボロン、マグネシウム、ジルコニウムの１群から
選ばれた少なくとも１つの元素を含むアルミ合金膜が用
いられる。Alternatively, an aluminum alloy film containing at least one element selected from the group consisting of copper, titanium, boron, magnesium, and zirconium is used as the layer on the bump electrode side of the wiring.

［作用］ 本発明に係る配線は積層構造となっており、そのバンプ
電極側の層の結晶粒径が他の層よりも小さく設定されて
いる。このため、配線の結晶粒界とバンプ電極との界面
の面積が増す。この部分では１．比較的低温でも金属の
相互拡散が起こりやす＜、シたがって、全体として配線
とバンプ電極との付着力が向上する。その結果、配線と
バンプ電極との間の剥離が防止され、苛酷な条件下でも
高い信頼性を有する半導体装置を得ることができるよう
になる。[Operation] The wiring according to the present invention has a laminated structure, and the crystal grain size of the layer on the bump electrode side is set smaller than that of the other layers. Therefore, the area of the interface between the crystal grain boundary of the wiring and the bump electrode increases. In this part, 1. Interdiffusion of metals is likely to occur even at relatively low temperatures, thus improving the adhesion between the wiring and bump electrodes as a whole. As a result, separation between the wiring and the bump electrode is prevented, and a semiconductor device having high reliability even under severe conditions can be obtained.

［実施例］ この発明の一実施例を示す第１図において、半導体基板
２１は、その上部に活性領域２２を有し、その上に下地
絶縁膜２３が設けられている。下地絶縁膜２３は、活性
領域２２に対応する位置にコンタクト孔２４を有してい
る。下地絶縁膜２３の上には、保護絶縁膜２５が設けら
れており、保護絶縁膜２５の所定位置には開口２６が形
成されている。開口２６には、バンプ電極２７の下部が
配置されており、バンプ電極２７は開口２６から第１図
の上方に突出している。バンプ電極２７の下部には、半
導体基板２１側から順に第１のバンプ下地金属２８と第
２のバンプ下地金属２９が積層状態で設けられている。[Embodiment] In FIG. 1 showing an embodiment of the present invention, a semiconductor substrate 21 has an active region 22 on its upper part, and a base insulating film 23 is provided thereon. The base insulating film 23 has a contact hole 24 at a position corresponding to the active region 22 . A protective insulating film 25 is provided on the base insulating film 23, and an opening 26 is formed at a predetermined position in the protective insulating film 25. A lower portion of a bump electrode 27 is disposed in the opening 26, and the bump electrode 27 projects upward from the opening 26 in FIG. Below the bump electrode 27, a first bump base metal 28 and a second bump base metal 29 are provided in a laminated state in order from the semiconductor substrate 21 side.

第１のバンプ下地金属２８はたとえばＣｒ膜よりなり、
第２のバンプ下地金属２９はたとえばＣｕ膜よりなって
いる。The first bump base metal 28 is made of, for example, a Cr film,
The second bump base metal 29 is made of, for example, a Cu film.

活性領域２２とバンプ電極２７との間は、配線３０によ
って電気的に接続されている。配線３０は、半導体基板
２１側に配置された第１の層３１と、バンプ電極２７側
に配置された第２の層３２との２層からなる積層構造と
なっている。また、配線３０は、アルミあるいはアルミ
合金によって形成されている。さらに、第２の層３２の
結晶粒径は、第１の層３１よりも小さく設定されている
。Active region 22 and bump electrode 27 are electrically connected by wiring 30 . The wiring 30 has a laminated structure consisting of two layers: a first layer 31 placed on the semiconductor substrate 21 side and a second layer 32 placed on the bump electrode 27 side. Further, the wiring 30 is formed of aluminum or an aluminum alloy. Furthermore, the crystal grain size of the second layer 32 is set smaller than that of the first layer 31.

配線３０は、下地絶縁膜２３と保護絶縁膜２５との間に
配置されており、その一部がコンタクト孔２４を通じて
活性領域２２にオーミック接触し、他部がバンプ電極２
７の第１のバンプ下地金属２８にオーミック接触してい
る。なお、配線３０のうち、第１の層３１が活性領域２
２に接触し、第２の層３２が第１のバンプ下地金属２８
に接触している。The wiring 30 is arranged between the base insulating film 23 and the protective insulating film 25, and a part thereof is in ohmic contact with the active region 22 through the contact hole 24, and the other part is in contact with the bump electrode 2.
It is in ohmic contact with the first bump base metal 28 of No. 7. Note that the first layer 31 of the wiring 30 is connected to the active region 2.
2 and the second layer 32 is in contact with the first bump underlying metal 28
is in contact with.

第１図に示す半導体装置では、第１のバンプ下地金属２
８に接触する配線３０の第２の層３２が結晶粒径の小さ
なアルミあるいはアルミ合金によって形成されているの
で、配線３０の結晶粒界とバンプ下地金属２８との界面
の面積が増す。この部分では、比較的低温でも金属の相
互拡散が起こりやすく、したがって、全体として配線３
０とバンプ下地金属２８との間の付着力が向上する。こ
の結果、苛酷な条件下で使用してもバンプ電極２７と配
線３０との間の剥離が生じず、信頼性の高い半導体装置
が得られる。In the semiconductor device shown in FIG.
Since the second layer 32 of the wiring 30 that contacts the bump 8 is made of aluminum or aluminum alloy with a small crystal grain size, the area of the interface between the grain boundary of the wiring 30 and the bump base metal 28 increases. In this part, metal interdiffusion is likely to occur even at a relatively low temperature, and therefore the wiring 3 as a whole
0 and the bump base metal 28 is improved. As a result, even when used under severe conditions, separation between bump electrodes 27 and wiring 30 does not occur, and a highly reliable semiconductor device can be obtained.

なお、第２図に、配線３０としてＡｕ膜を用いた場合の
配線３０の平均結晶粒径と、配線３０とバンプ下地金属
２８との間（Ａα−Ｃｒ間）の剥離発生率との関係を示
す。第２図から、配線３０の材質が同じであっても結晶
粒径を小さくすれば、配線３０とバンプ下地金属２８と
の間の剥離が発生しにくくなり、平均結晶粒径を２μｍ
以下にすれば剥離発生率を零にすることができることが
わかる。In addition, FIG. 2 shows the relationship between the average crystal grain size of the wiring 30 and the rate of peeling between the wiring 30 and the bump base metal 28 (between Aα and Cr) when an Au film is used as the wiring 30. show. From FIG. 2, even if the material of the wiring 30 is the same, if the crystal grain size is made smaller, peeling between the wiring 30 and the bump base metal 28 becomes less likely to occur, and the average crystal grain size is reduced to 2 μm.
It can be seen that the rate of peeling can be reduced to zero if the following conditions are met.

次に、第３Ａ図ないし第３Ｆ図および第４図を参照して
、本実施例に係る半導体装置の製造方法を説明する。Next, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to FIGS. 3A to 3F and FIG. 4.

（Ａ）　　まず、第３Ａ図に示すように、イオン注入法
などを用いて、半導体基板２１上部の所定位置に活性領
域（不純物拡散層）２２を形成する。(A) First, as shown in FIG. 3A, an active region (impurity diffusion layer) 22 is formed at a predetermined position on a semiconductor substrate 21 using an ion implantation method or the like.

次に、界面保護の目的で、リン、ガラスなどからなる下
地絶縁膜２３を堆積する。Next, a base insulating film 23 made of phosphorus, glass, or the like is deposited for the purpose of protecting the interface.

（Ｂ）　　写真製版およびエツチング法を用いて、第３
Ｂ図に示すように、下地絶縁膜２３の活性領域２２に対
応する位置にコンタクト孔２４を開口する。次に、真空
蒸着法やスパッタ法を用いて、配線３０を形成する。配
線材料としては、通常、Ａα膜やＡαにＳｔを１〜２ｗ
ｔ％添加したＡＭ−Ｓｔ合金膜が用いられる。その後、
活性領域２２と配線３０とのオーミック接触を得るため
に、４００〜５００℃の熱処理を行なう。(B) Using photolithography and etching method, the third
As shown in Figure B, a contact hole 24 is opened at a position corresponding to the active region 22 of the base insulating film 23. Next, the wiring 30 is formed using a vacuum evaporation method or a sputtering method. The wiring material is usually an Aα film or Aα with 1 to 2 w of St.
An AM-St alloy film doped with t% is used. after that,
In order to obtain ohmic contact between the active region 22 and the wiring 30, heat treatment is performed at 400 to 500°C.

しかしながら、Ａα膜やＡｕ−５層合金膜を使用して通
常のｈ゛法を採用すると、４００〜５００℃の熱処理に
おいて配線３０の結晶粒が容易に成長し、その平均粒径
が大きくなってしまう。However, when the normal h method is adopted using an Aα film or an Au-5 layer alloy film, the crystal grains of the wiring 30 easily grow during heat treatment at 400 to 500°C, and the average grain size becomes large. Put it away.

そこで、配線３０の結晶粒成長を抑制するため、真空蒸
着法やスパッタ法等で配線３０を形成するときに、Ｎ２
，０□＋　Ｎ２　＋　Ｉ（２０などの微量の反応性ガス
を混入する方法を採用する。但し、この方法によって形
成された膜は、一般にエレクトロ・マイグレーション耐
性が劣るので、電流密度の高い微細アルミ配線の場合に
は、単層膜として用いることができない。そこで、この
問題を解決するため、配線３０の第１の層３１を通常用
いらレテイルエレクトロ・マイグレーション耐性の良好
な結晶粒径の大きな膜とする。また、第１のバンプ下地
金属２８に接する第２の層３２を、前述のように微量の
反応性ガスを混入させて結晶粒径の小さな膜とし、これ
により積層構造の配線３０を形成する。Therefore, in order to suppress the growth of crystal grains in the wiring 30, when forming the wiring 30 by vacuum evaporation or sputtering, N2
, 0□ + N2 + I (20) is used. However, the film formed by this method generally has poor electromigration resistance, so fine aluminum with high current density is used. In the case of wiring, it cannot be used as a single layer film.Therefore, in order to solve this problem, the first layer 31 of the wiring 30 is usually made of a film with a large crystal grain size and good resistance to retail electromigration. In addition, the second layer 32 in contact with the first bump base metal 28 is made into a film with a small crystal grain size by mixing a small amount of reactive gas as described above. form.

このような結晶粒径の異なる積層構造の配線３０を形成
する方法を以下に述べる。たとえば、スパッタ法を用い
る場合には、第４図に示すような薄膜形成装置を用いる
。第４図において、真空容器５１内には、陰極（ターゲ
ット）５２と陽極（基板ホルダ）５３とが間隔を隔てて
対向するように配置されている。陰極５２お゛よび陽極
５３は真空容器５１外に配置された高電圧電源５４に接
続されている。真空容器５１には、Ａ「ガス導入バルブ
５６を介してたとえばＡｒガスが導入されるようになっ
ており、反応性ガス導入バルブ５７を介してたとえばＮ
２ガスが導入されるようになっている。また、真空容器
５１は、高真空バルブ５８を介して高真空ポンプユニッ
ト５９に接続され、高真空ポンプユニット５９によって
真空容器５１内が真空状態にされ得るようになっている
。A method for forming the wiring 30 having such a laminated structure with different crystal grain sizes will be described below. For example, when using the sputtering method, a thin film forming apparatus as shown in FIG. 4 is used. In FIG. 4, a cathode (target) 52 and an anode (substrate holder) 53 are arranged in a vacuum container 51 so as to face each other with a gap therebetween. The cathode 52 and anode 53 are connected to a high voltage power source 54 located outside the vacuum vessel 51. For example, Ar gas is introduced into the vacuum container 51 via an A gas introduction valve 56, and N gas, for example, is introduced via a reactive gas introduction valve 57.
Two gases are introduced. Further, the vacuum container 51 is connected to a high vacuum pump unit 59 via a high vacuum valve 58, so that the inside of the vacuum container 51 can be brought into a vacuum state by the high vacuum pump unit 59.

なお、６０は陽極上に置かれた製造途中の半導体基板、
６１は模式的に示した気体放電である。In addition, 60 is a semiconductor substrate in the process of being manufactured placed on the anode,
61 is a gas discharge schematically shown.

第４図の装置を用いた膜形成方法としては、まず、真空
容器５１内にＡｒガスのみを導入し、陰極５２と陽極５
３との間に高電圧を印加し、気体放電６１を発生させる
。これにより、通常のスパッタ法に従って、半導体基板
６０上に配線３０の第１の層３１（第３Ｂ図）を堆積す
る。次に、Ａｒガスとともに微量の反応性ガスも導入し
、反応性ガスの混入したアルミ膜を連続して堆積させる
。As a film forming method using the apparatus shown in FIG. 4, first, only Ar gas is introduced into the vacuum container 51, and the cathode 52 and anode 5
3 to generate a gas discharge 61. Thereby, the first layer 31 (FIG. 3B) of the wiring 30 is deposited on the semiconductor substrate 60 according to the usual sputtering method. Next, a trace amount of reactive gas is introduced together with the Ar gas, and an aluminum film mixed with the reactive gas is successively deposited.

これによって、配線３０の第２の層３２を（第３Ｂ図）
を形成する。気体放電６１を発生させるために導入する
Ａｒガスの圧力は、通常１〜５０×１０−”Ｔｏｒｒ程
度であるが、導入する反応性ガスの分圧はＮ２，０２．
Ｎ２．Ｎ２０いずれの場合であっても、２〜５０Ｘ１０
−　’　Ｔｏ　ｒ　ｒ程度とする。なお、このときの配
線３０の第２の層３２中への反応性ガスの混入量は１０
０〜５０００ｐｐｍのレベルである。As a result, the second layer 32 of the wiring 30 (FIG. 3B)
form. The pressure of the Ar gas introduced to generate the gas discharge 61 is usually about 1 to 50 x 10-'' Torr, but the partial pressure of the reactive gas introduced is N2,02.
N2. N20 In any case, 2~50X10
-'Torr approximately. Note that the amount of reactive gas mixed into the second layer 32 of the wiring 30 at this time is 10
The level is between 0 and 5000 ppm.

このような積層構造の配線３０を４００〜５００℃で熱
処理した場合、反応性ガスを含まない第１の層３１では
容易に結晶粒が成長して平均結晶粒径が２μｍ以上とな
る。これに対し、微量の反応柱ガスを含む第２の層３２
では、結晶粒の成長が抑制されるので、平均結晶粒径は
２μｍ以下となる。このため、この積層構造の配線３０
」二にバンプ電極２７を形成した場合でも、配線３０と
第１のバンプ下地金属２８との間の付着力は強く、両者
間の剥離の発生が防止できる。When the wiring 30 having such a laminated structure is heat-treated at 400 to 500° C., crystal grains easily grow in the first layer 31 that does not contain a reactive gas, and the average crystal grain size becomes 2 μm or more. In contrast, the second layer 32 containing a trace amount of reaction column gas
In this case, since the growth of crystal grains is suppressed, the average crystal grain size becomes 2 μm or less. Therefore, the wiring 30 of this laminated structure
Even when the bump electrode 27 is formed secondly, the adhesion between the wiring 30 and the first bump base metal 28 is strong, and peeling between the two can be prevented.

（Ｃ）　　次に、第３Ｃ図に示すように、配線３０を保
護するため、シリコン酸化膜、シリコン窒化膜などから
なる保護絶縁膜２５を、化学的気相成長法を用いて堆積
する。さらに、写真製版およびエツチング法を用いて、
バンプ電極２７を形成する部分に開口２６を形成する。(C) Next, as shown in FIG. 3C, in order to protect the wiring 30, a protective insulating film 25 made of a silicon oxide film, a silicon nitride film, or the like is deposited using chemical vapor deposition. Furthermore, using photolithography and etching methods,
An opening 26 is formed in a portion where a bump electrode 27 is to be formed.

（Ｄ）　　ｍ３Ｄ図に示すように、第１のバンプ下地金
属２８として、０．１〜０．３μｍ程度のＣｒ膜を堆積
し、さらに第２のバンプ下地金属２９として、０．５〜
３．０μｍ程度のＣｕ膜を真空蒸着法やスパッタ法を用
いて堆積する。ここで、第１のバンプ下地金属２８は配
線３０との付着力を高めるための膜として、第２のバン
プ下地金属２９はめっき用の電極として作用する。次に
、写真製版技術を用い、バンプ電極２７を形成する部分
のみに開口を有するフォトレジスト３３を設ける。(D) As shown in the m3D diagram, a Cr film of approximately 0.1 to 0.3 μm is deposited as the first bump base metal 28, and a Cr film of approximately 0.5 to 0.3 μm is deposited as the second bump base metal 29.
A Cu film of about 3.0 μm is deposited using a vacuum evaporation method or a sputtering method. Here, the first bump base metal 28 functions as a film for increasing adhesion to the wiring 30, and the second bump base metal 29 functions as an electrode for plating. Next, using photolithography, a photoresist 33 having an opening only in the portion where the bump electrode 27 is to be formed is provided.

（Ｅ）　　めっき法により、第３Ｅ図に示すように、フ
ォトレジスト３３の開口部に、選択的にＡｕ。(E) By plating, Au is selectively applied to the openings of the photoresist 33, as shown in FIG. 3E.

Ｃｕ、はんだなどからなるバンプ電極２７を形成する。A bump electrode 27 made of Cu, solder, or the like is formed.

バンプ電極２７の高さは、通常、３０〜１００μｍ程度
である。The height of the bump electrode 27 is usually about 30 to 100 μm.

（Ｆ）　　フォトレジスト３３を除去した後、Ｃｒおよ
びＣｕからなる第１および第２のバンプ下地金属２８．
２９を、バンプ電極２７の下部のみを残してエツチング
により除去する。これによって、第１図に示す半導体装
置が得られる。(F) After removing the photoresist 33, first and second bump base metals 28. made of Cr and Cu are removed.
29 is removed by etching leaving only the lower part of the bump electrode 27. As a result, the semiconductor device shown in FIG. 1 is obtained.

［他の実施例コ （ａ）　　上記実施例では、積層構造の配線３０の材質
がＡＱあるいはＡｆｌ−Ｓｉ合金膜である場合について
述べたが、ＡＱ、を主成分とした他のアルミ合金膜を採
用することもできる。[Other Embodiments (a) In the above embodiments, the case where the material of the wiring 30 of the laminated structure is AQ or Afl-Si alloy film is described. It can also be adopted.

（ｂ）　　配線３０のアルミ膜の結晶粒成長を抑制する
方法として、ＡＱ、あるいはＡ１１ｊ−８ｊ合金膜中に
、銅（Ｃｕ）、チタン（Ｔｉ）、ボロン（Ｂ）、マグネ
シウム（Ｍｇ）、　　ジルコニウム（Ｚ　ｒ）等の元素
を添加したアルミ合金膜を用いる方法を採用してもよい
。但し、これらのアルミ合金膜は、活性領域２２の接合
リークを引き起こす、オーミック接触抵抗が増加する、
配線抵抗が増加する、エレクトロマイグレーション耐性
が劣化するなど、それぞれの添加元素により短所を持っ
ている。(b) As a method of suppressing crystal grain growth in the aluminum film of the wiring 30, copper (Cu), titanium (Ti), boron (B), magnesium (Mg), and zirconium are added to the AQ or A11j-8j alloy film. A method using an aluminum alloy film to which an element such as (Zr) is added may also be adopted. However, these aluminum alloy films cause junction leakage in the active region 22, increase ohmic contact resistance,
Each additive element has its own disadvantages, such as increased wiring resistance and decreased electromigration resistance.

そこで、この問題を解決するために、配線３０を積層構
造とし、第１の層３１としてＡｆＬ、Ａｕ−３ｊ合金な
ど通常用いられている結晶粒径の大きなアルミあるいは
アルミ合金膜を用い、第２の層３２として銅（Ｃｕ）、
チタン（Ｔｉ）、ボロン（Ｂ）、マグネシウム（Ｍｇ）
、　　ジルコニウム（Ｚｒ）などの元素を添加した結晶
粒径の小さなアルミ合金膜を用いる。こうすれば、半導
体基板２１や活性領域２２と直接に接するのは従来のア
ルミあるいはアルミ合金膜であるので、接合リークとか
オーミック接触不良のような弊害の発生を防止できる。Therefore, in order to solve this problem, the wiring 30 has a laminated structure, the first layer 31 is made of aluminum or aluminum alloy film with a commonly used large crystal grain size such as AfL, Au-3j alloy, etc. copper (Cu) as the layer 32;
Titanium (Ti), boron (B), magnesium (Mg)
, an aluminum alloy film with small crystal grain size to which elements such as zirconium (Zr) are added is used. In this way, since the conventional aluminum or aluminum alloy film is in direct contact with the semiconductor substrate 21 and the active region 22, problems such as junction leakage and ohmic contact failure can be prevented from occurring.

また、配線抵抗やエレクトロマイグレーション耐性も従
来と同等の性能を維持できる。In addition, wiring resistance and electromigration resistance can maintain the same performance as conventional ones.

さらに、第１のバンプ下地金属２８と接する第２の層３
２の結晶粒径は平均粒径で２μｍ以下と小さくなるので
、この界面での付着強度を増すことができ、剥離問題を
解消できる。Furthermore, the second layer 3 in contact with the first bump base metal 28
Since the average grain size of No. 2 is as small as 2 μm or less, the adhesion strength at this interface can be increased and the peeling problem can be solved.

通常、結晶粒径の小さな第２の層３２の膜厚は、０．１
μｍ以上あればよい。また、銅（Ｃｕ）。Usually, the thickness of the second layer 32 with a small crystal grain size is 0.1
It is sufficient if it is at least μm. Also, copper (Cu).

チタン（Ｔｉ）、ボロン（Ｂ）、マグネシウム（Ｍｇ）
、　　ジルコニウム（Ｚ「）などの添加量は、第１のバ
ンプ下地金属２８を堆積する時点での第２の層３２の平
均結晶粒径が２μｍ以下となるのに十分な量であればよ
い。したがって、添加元素により多少差はあるが、通常
これらの元素の総量で０．１ｗｔ％以上添加する。但し
、１．　０ｗｔ％以上添加すると、エツチング（特にド
ライエツチング）が難しくなるので好ましくない。Titanium (Ti), boron (B), magnesium (Mg)
The addition amount of zirconium (Z''), etc. may be an amount sufficient to make the average crystal grain size of the second layer 32 at the time of depositing the first bump base metal 28 to be 2 μm or less. Therefore, although there are some differences depending on the added elements, the total amount of these elements is usually added at 0.1 wt% or more.However, adding 1.0 wt% or more is not preferable because etching (particularly dry etching) becomes difficult.

この実施例における、結晶粒径の異なる積層構造の配線
３０を形成する方法を以下に説明する。A method of forming the wiring 30 having a laminated structure with different crystal grain sizes in this example will be described below.

たとえば、スパッタ法を用いる場合には第５図に示すよ
うな薄膜形成装置を用いる。第５図において、第４図に
相当する部分には同一符号が付されている。但し、第５
図の装置では、陽極（基板ホルダ）５３が図示しない駆
動機構によって回転駆動されるターンテーブルとなって
いる。また、第５図の装置では、第４図の装置のように
Ｎ２などの反応性ガスを導入する経路は設けられていな
い。For example, when using the sputtering method, a thin film forming apparatus as shown in FIG. 5 is used. In FIG. 5, parts corresponding to those in FIG. 4 are given the same reference numerals. However, the fifth
In the illustrated apparatus, the anode (substrate holder) 53 is a turntable that is rotationally driven by a drive mechanism (not shown). Further, in the apparatus shown in FIG. 5, unlike the apparatus shown in FIG. 4, a path for introducing a reactive gas such as N2 is not provided.

さらに、第５図では１対の陰極（ＡｆＬターゲット）５
２ａ、および陰極（ＡＱ−Ｃｕターゲット）５２ｂが設
けられ、それに対応して１対の高電圧電源５４ａ、５４
ｂが設けられている。Furthermore, in FIG. 5, a pair of cathodes (AfL targets) 5
2a, and a cathode (AQ-Cu target) 52b, and correspondingly a pair of high voltage power supplies 54a, 54.
b is provided.

この実施例の場合の膜形成方法は、まず、真空容器５１
内を高真空ポンプユニット５つを用いて、１０−’Ｔｏ
ｒｒ台の高真空領域まで排気する。In the film forming method in this embodiment, first, the vacuum vessel 51
Using five high vacuum pump units inside, 10-'To
Evacuate to high vacuum area of rr level.

次に、Ａ「ガス導入バルブ５６を開き、真空容器５１内
にＡｒガスを導入する。さらに、一方の陰極５２ａ（Ａ
ｌｌターゲット）と陽極５３との間に高電圧を印加して
気体放電６１を発生させ、スパッタ法により半導体基板
６０上に第１の層３１を堆積する。Next, the A gas introduction valve 56 is opened to introduce Ar gas into the vacuum container 51.Furthermore, one cathode 52a (A
A high voltage is applied between the anode 53 and the anode 53 to generate a gas discharge 61, and the first layer 31 is deposited on the semiconductor substrate 60 by sputtering.

次に、陽極５４を回転させ、他方の陰極５２ｂ（Ａｌｌ
−Ｃｕターゲット）の真下に半導体基板６０を置く。陰
極５２ｂと陽極５３との間に高電圧を印加し、第２の層
３２を連続的に堆積する。Next, the anode 54 is rotated, and the other cathode 52b (All
A semiconductor substrate 60 is placed directly under the -Cu target). A high voltage is applied between the cathode 52b and the anode 53, and the second layer 32 is continuously deposited.

このようにして形成された積層構造の配線３０に４００
〜５００℃の熱処理を施す。このとき、第１の層３１で
は、容易に結晶粒が成長し、平均結晶粒径が２μｍ以」
二となる。これに対し、銅（Ｃｕ）などの不純物を含む
第２の層３２では、含有された不純物元素が結晶粒界に
偏析し、結晶粒界の移動を妨げる。その結果、結晶粒の
成長が抑制され、平均結晶粒径は２μｍ以下となる。こ
れによって、配線３０上にバンプ電極２７を形成した場
合に、配線３０と第１のバンプ下地金属２８との間の付
着力は高くなり、剥離問題の発生を防止できる。The wiring 30 of the laminated structure formed in this way has 400
Heat treatment at ~500°C. At this time, crystal grains easily grow in the first layer 31, and the average crystal grain size is 2 μm or more.
It becomes two. On the other hand, in the second layer 32 containing impurities such as copper (Cu), the contained impurity elements segregate at grain boundaries and prevent movement of the grain boundaries. As a result, the growth of crystal grains is suppressed, and the average crystal grain size becomes 2 μm or less. As a result, when the bump electrode 27 is formed on the wiring 30, the adhesion between the wiring 30 and the first bump base metal 28 is increased, and the problem of peeling can be prevented.

（ｃ）　　上記実施例では、結晶粒界の小さな第２のｗ
Ｉ３２と接する第１のバンプ下地金属２８として、Ｃｒ
膜を用いた場合を示したが、チタン（Ｔｉ）、バナジウ
ム（Ｖ）、モリブデン（Ｍｏ）、タングステン（Ｗ）、
ニクロム（Ｎ　ｉ　Ｃｒ）あるいは、これらの元素を含
む化合物などを用いてもよい。(c) In the above embodiment, the second w with small grain boundaries
Cr is used as the first bump base metal 28 in contact with I32.
Although the case using a film is shown, titanium (Ti), vanadium (V), molybdenum (Mo), tungsten (W),
Nichrome (N i Cr) or a compound containing these elements may also be used.

（ｄ）　　配線３０として、３層以上の積層構造を採用
してもよい。(d) As the wiring 30, a laminated structure of three or more layers may be adopted.

［発明の効果］ この発明によれば、配線を積層構造とし、そのバンプ電
極側の層の結晶粒径を他の層よりも小さく設定したこと
から、従来の配線の性能を低下させることなく、配線と
バンプ電極との間の付研力を増すことができるようにな
る。したがって、この発明によれば、苛酷な条件下でも
高い信頼性をａする半導体装置を得ることができるよう
になる。[Effects of the Invention] According to the present invention, the wiring has a laminated structure, and the crystal grain size of the layer on the bump electrode side is set smaller than that of other layers, so that the performance of the conventional wiring is not reduced. It becomes possible to increase the polishing force between the wiring and the bump electrode. Therefore, according to the present invention, it is possible to obtain a semiconductor device that has high reliability even under severe conditions.

【図面の簡単な説明】 第１図は、この発明の一実施例による半導体装置を示す
縦断面部分図である。第２図は、アルミ膜の平均結晶粒
径と剥離発生率との関係を示すグラフである。第３八図
ないし第３Ｆ図は、半導体装置の製造工程を示す縦断面
部分図である。第４図は、半導体装置の製造の際に使用
する薄膜形成装置の概略図である。第５図は、薄膜形成
装置の他の例を示す概略図である。第６図は、従来例に
よる半導体装置の縦断面部分図である。第７図は、第６
図の■−■断面部分図である。 ２１は半導体基板、２２は活性領域、２７はバンプ電極
、３０は配線、３１は第１の層、３２は第２の層である
。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial vertical cross-sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a graph showing the relationship between the average crystal grain size of the aluminum film and the rate of peeling. FIGS. 38 to 3F are vertical cross-sectional partial views showing the manufacturing process of the semiconductor device. FIG. 4 is a schematic diagram of a thin film forming apparatus used in manufacturing semiconductor devices. FIG. 5 is a schematic diagram showing another example of the thin film forming apparatus. FIG. 6 is a partial vertical cross-sectional view of a conventional semiconductor device. Figure 7 shows the 6th
It is a partial cross-sectional view taken along ■-■ of the figure. 21 is a semiconductor substrate, 22 is an active region, 27 is a bump electrode, 30 is a wiring, 31 is a first layer, and 32 is a second layer.

Claims (4)

【特許請求の範囲】[Claims] （１）活性領域を有する半導体基板と、 外部接続のためのバンプ電極と、 前記活性領域と前記バンプ電極とを電気的に接続するア
ルミあるいはアルミ合金からなる配線とを含む半導体装
置であって、 前記配線は積層構造であり、そのバンプ電極側の層の結
晶粒径が他の層よりも小さく設定されていることを特徴
とする半導体装置。(1) A semiconductor device including a semiconductor substrate having an active region, a bump electrode for external connection, and a wiring made of aluminum or aluminum alloy that electrically connects the active region and the bump electrode, A semiconductor device characterized in that the wiring has a laminated structure, and the crystal grain size of the layer on the bump electrode side is set smaller than that of the other layers. （２）前記配線と接するバンプ電極の下地金属が、クロ
ム（Ｃｒ）、チタン（Ｔｉ）、バナジウム（Ｖ）、モリ
ブデン（Ｍｏ）、タングステン（Ｗ）、ニクロム（Ｎｉ
Ｃｒ）あるいはこれらの元素を含む化合物のいずれかで
ある特許請求の範囲第１項記載の半導体装置。(2) The underlying metal of the bump electrode in contact with the wiring is chromium (Cr), titanium (Ti), vanadium (V), molybdenum (Mo), tungsten (W), nichrome (Ni).
2. The semiconductor device according to claim 1, which is either Cr) or a compound containing these elements. （３）前記配線のバンプ電極側の層として、窒素（Ｎ＿
２）、酸素（Ｏ＿２）、水素（Ｈ＿２）、水（Ｈ＿２Ｏ
）の１群から選ばれた少なくとも１つの反応性ガスを混
入した膜を用いた特許請求の範囲第１項記載の半導体装
置。(3) Nitrogen (N_
2), oxygen (O_2), hydrogen (H_2), water (H_2O
2. The semiconductor device according to claim 1, wherein the semiconductor device uses a film mixed with at least one reactive gas selected from the group consisting of: （４）前記配線のバンプ電極側の層として、銅（Ｃｕ）
、チタン（Ｔｉ）、ボロン（Ｂ）、マグネシウム（Ｍｇ
）、ジルコニウム（Ｚｒ）の１群から選ばれた少なくと
も１つの元素を含むアルミ合金膜を用いた特許請求の範
囲第１項記載の半導体装置。(4) Copper (Cu) is used as the layer on the bump electrode side of the wiring.
, titanium (Ti), boron (B), magnesium (Mg
), zirconium (Zr), and an aluminum alloy film containing at least one element selected from the group consisting of zirconium (Zr).
JP62250351A 1987-10-02 1987-10-02 Semiconductor device Pending JPH0193149A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62250351A JPH0193149A (en) 1987-10-02 1987-10-02 Semiconductor device
DE3830131A DE3830131A1 (en) 1987-10-02 1988-09-05 Flip-chip semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62250351A JPH0193149A (en) 1987-10-02 1987-10-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0193149A true JPH0193149A (en) 1989-04-12

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ID=17206624

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JPH0193149A (en)
DE (1) DE3830131A1 (en)

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JP2005322834A (en) * 2004-05-11 2005-11-17 Ricoh Co Ltd Pattern-shaped body and manufacturing method thereof
JP2007110012A (en) * 2005-10-17 2007-04-26 Ngk Insulators Ltd Dielectric device and method of manufacturing same
JP2008114795A (en) * 2006-11-07 2008-05-22 Mazda Motor Corp Vehicle structure provided with curtain airbag device

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IL106892A0 (en) * 1993-09-02 1993-12-28 Pierre Badehi Methods and apparatus for producing integrated circuit devices
IL108359A (en) * 1994-01-17 2001-04-30 Shellcase Ltd Method and apparatus for producing integrated circuit devices
IL110261A0 (en) * 1994-07-10 1994-10-21 Schellcase Ltd Packaged integrated circuit

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JPS6288342A (en) * 1985-10-15 1987-04-22 Fujitsu Ltd Structure of laminated-layer reinforced type wiring layer and manufacture thereof

Cited By (4)

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Publication number Priority date Publication date Assignee Title
JP2005322834A (en) * 2004-05-11 2005-11-17 Ricoh Co Ltd Pattern-shaped body and manufacturing method thereof
JP4484578B2 (en) * 2004-05-11 2010-06-16 株式会社リコー Pattern shape body and method for manufacturing the same
JP2007110012A (en) * 2005-10-17 2007-04-26 Ngk Insulators Ltd Dielectric device and method of manufacturing same
JP2008114795A (en) * 2006-11-07 2008-05-22 Mazda Motor Corp Vehicle structure provided with curtain airbag device

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DE3830131A1 (en) 1989-04-20

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