JPS6271281A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To reduce surface oxidation of high melting point metal by forming the surface of a gate electrode of at least 20-layer gate electrode having a high melting point metal silicide. CONSTITUTION:After WSi and then W and WSi are continuously accumulated on the entire surface by a sputtering unit on a semi-insulating GaAs substrate, WSi/W/WSi metal films of the first layer wirings 11 are patterned by a dry etching method. Then, after an SiO2 film is accumulated by a CVD method on the entire surface as an interlayer insulting film, the SiO2 film is opened with diluted fluoric acid on the first layer wirings. Then, the laminated film of Ti, Pt, Au is formed as the second layer wirings by a lifting off method using a resist. Thus, the surface of a gate electrode is formed in a high melting point metal silicide to reduce the oxidation of the gate electrode surface.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to
-■Relating to a compound semiconductor device.

(Prior technology) Schottky barrier field effect transistor (MESF)
gallium arsenide (GaAs), especially gallium arsenide (GaAs
) is excellent in high-speed performance and has been increasingly used as a semiconductor element for ultra-high frequencies in recent years.

FIG. 2 is a schematic cross-sectional view of an element showing an example of a conventionally well-known CfaAs MESFET. In this structure, Ga
As for improving the performance of 8B'ET, for example, in 1983.
Digest of I. Nis.C. Technical Papers published in 1880C1 igesLof
As shown on page 218 of Technical Papers), the source and drain regions are ()a
High concentration impurity region 5 having the same conductivity type as As active layer 4
It is formed as. In FIG. 2, l is a gate electrode, 2.3 is an ohmic electrode, and 6 is a semi-insulating GaAs
It is a board.

In the MESFET having the structure shown in FIG. 2 shown above, the series parasitic resistance between the source and drain is significantly reduced by the presence of this heavily doped impurity region 5, so high mutual conductance and low on-resistance are achieved, and the FET High-speed operation is possible.

The above-mentioned high concentration impurity region 5 can be formed by performing ion implantation using the gate 1 as a mask, and then performing heat treatment (annealing) at about 800C to activate the ion implanted impurity. In this case, since the gate electrode 1 is annealed in the GaAs operating liquid 4, the gate electrode material can withstand this annealing.
Heat resistance is required to ensure stable Schottky bonding properties even after annealing. Furthermore, since this heat-resistant gate electrode material is also used for internal wiring in integrated circuits, it is required to have low resistance in order to reduce wiring delay time.

At present, tungsten, tungsten silicide (WSi), tungsten oxide (WN), and the like are being tried as heat-resistant gate electrode materials. Of these, W8i has a resistivity of 1 after annealing at 800°C.
It is as high as 00 μΩ·1 or more, making it difficult to increase the speed of GaAs integrated circuits. Thus, for example, patent application no.
As shown in No. 35342, a heat-resistant gate electrode having a two-layer structure in which a refractory metal is formed on a refractory all-polar silicide has been proposed. In this case, a high melting point metal such as W has a resistivity of 1 compared to a high melting point metal silicide such as ~3i.
Since it is several orders of magnitude lower, the gate resistance can be reduced.

(Problems to be Solved by the Invention) When the surface of the gate electrode is formed of a high-melting point metal, such as the above-mentioned two-layer structure gate electrode in which W is laminated on W or WSi as the heat-resistant gate electrode material, FET manufacturing process after gate electrode formation, for example, the first step using the gate electrode
When performing a process at 200°C or higher, such as the deposition of 5IO2, etc., to form an insulating film between the eyebrows of the upper layer wiring electrode and the second layer wiring electrode, the surface of the high melting point metal of the first layer wiring may be oxidized. I understand. Therefore, the second layer wiring (for example, Ti-
It has become clear that in the contact portion where Au) and the first layer wiring are electrically connected, a high resistance layer exists at the contact interface between the two, and the desired FET% and IC% cannot be obtained.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor device that reduces surface oxidation of a high melting point metal.

(Means for Solving the Problems) The present invention provides a compound semiconductor device including a compound semiconductor field effect transistor having a high melting point all-polar gate electrode.
The present invention is constructed as a compound semiconductor device characterized by at least a two-layer gate electrode structure having a high melting point metal silicide on the surface of the gate electrode. By making the surface of the gate electrode a high melting point metal silicide, it is possible to reduce oxidation of the gate electrode surface.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. Figures 1 (a) to (C1) are plan views of device patterns shown in the order of steps to explain an embodiment of the present invention.

First, a semi-insulating GaAs substrate 6 is prepared, and a sputtering device is used to coat the substrate with WSilOOOOλ, followed by W, and then the first layer arrangement '#A]l is VvSi /W/VvS.
The i metal film was patterned as shown in FIG. 1(a) by a dry ethosinking method using eb' and 02.

Next, as an interlayer insulating film, a film of 40% Sin was deposited using the CVD method.
After depositing 500 OA over the entire surface at 0°C, as shown in Fig. 1(b), the thickness of Sin on the first layer interconnection was reduced to 2 μm using dilute hydrofluoric acid.
It opened at the corner.

Next, as the second layer wiring, rTi 1000λ, Pt100
A laminated film of 5,000 λAu layers was formed as shown in FIG. 1(C) by a lift-off method using a resist.

In addition to the above, a metal film formed by depositing 1000 λ of WSi followed by 3000 λ of WSi was also fabricated as a conventional one-layer wiring.

The contact resistance was determined by excluding the resistance of the wiring from the resistance between the bats at both ends of the formed second layer wiring. When the conventional structure is used as the first layer wiring, the contact resistance is 430Ω・μ, and when the structure of the present invention is used, the contact resistance is 23Ω・μ.
A result as low as ltm was obtained.

(Effects of the Invention) As described above in detail, according to the present invention, a semiconductor device can be obtained that can suppress oxidation of the heat-resistant gate electrode surface and reduce the contact resistance at the interface between the gate electrode and the second layer electrode.

[Brief explanation of drawings]

FIG. 1 (aj to (CJ) is a pattern plan view of an element shown in order of process to explain an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of a conventional GaAs MESFET. 1... ...Heat-resistant gate electrode, 11... High melting point metal silicide/High melting point gold maple/High melting point gold maple silicide 2.3... Source, drain electrode, 4...
...GaAs active layer, 5...High concentration impurity region, 6...Semi-insulating (JaAs substrate,
7... Interlayer insulating film opening, 8... Second
Layer wiring electrode.

Claims (1)

[Claims] (1) A compound semiconductor device including a compound semiconductor field effect transistor having a high melting point metal gate electrode, characterized by a gate electrode structure of at least two layers including a high melting point metal silicide on the surface of the gate electrode.