JPS60132375A - Schottky barrier gate field effect transistor - Google Patents
Schottky barrier gate field effect transistorInfo
- Publication number
- JPS60132375A JPS60132375A JP23990183A JP23990183A JPS60132375A JP S60132375 A JPS60132375 A JP S60132375A JP 23990183 A JP23990183 A JP 23990183A JP 23990183 A JP23990183 A JP 23990183A JP S60132375 A JPS60132375 A JP S60132375A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- schottky barrier
- effect transistor
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004888 barrier function Effects 0.000 title claims abstract description 16
- 230000005669 field effect Effects 0.000 title claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 18
- 239000000203 mixture Substances 0.000 claims abstract description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 150000002739 metals Chemical class 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 241000218645 Cedrus Species 0.000 description 1
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000002576 ketones Chemical class 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はショットキーバリアゲ−ト型電界効果トランジ
スタに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a Schottky barrier gate field effect transistor.
（従来例の構成とその問題点）
ＧａＡａよりなる電界効果型トランジスタ（以下ＦＥＴ
と記す。）は従来のＳｉを素材とするＦＥＴに比べ、優
れた高周波特性を有するＦＥＴとして注目されている。(Conventional structure and its problems) Field effect transistor (hereinafter referred to as FET) made of GaAa
It is written as ) is attracting attention as an FET with superior high frequency characteristics compared to conventional FETs made of Si.
中でもＧａＡｓショットキーパリアケ゛−卜型Ｆ Ｅ
Ｔ （ＧａＡｓ Ｍ Ｅ Ｓ Ｆ Ｅ Ｔ ）は高速性
と低消費電力性に優れており、ロジックＩＣ，メモリな
ど種々の応用分野で研究が進められている。ＧａＡｓＦ
ＥＴでさらに高速化を進めるだめ、イオン注入によるセ
ルファライン構造を持つＦＥＴの開発が進められている
。このセルファライン法はシリコンプロセスでは一般的
に用いられているが、ＧａＡｓではイオン注入後のアニ
ール工程での高温熱処理時に、基板のＧａＡｓとＡｔや
Ｃｒ −Ｐｔ −Ａｕなどのグー汁金属材料が反応して
しまい、ショットキー・マリアを保つことができなくな
る。現在熱処理によって界面の変性しない材料として、
Ｗ 、 ＷＳｉｘ＋Ｗ−ＡｔＴａＳｉ ＋ ＴａＷ−８
ｉ など種々の合金が開発されＸ ｘ
つつある。しかし騨型ＧａＡｓ ＯシックＩＣなどに使
つエンハンスメントＷＦ Ｅ Ｔノショソトキーノクリ
ア材料として必要な条件は熱特性以外に（１）・り＋７
７障壁φ８が高く、（２）比抵抗ρＳが低いことが必要
である。前記金属はいずれも熱特性は優れているが（１
） 、 （２） ｋ兼ねている材料は見出されていない
。Among them, GaAs Schottky array type F E
T (GaAs MESFET) is excellent in high speed and low power consumption, and is being studied in various application fields such as logic ICs and memories. GaAsF
In order to further increase the speed of ET, development of FETs with a self-line structure using ion implantation is underway. This self-line method is commonly used in silicon processes, but in the case of GaAs, during high-temperature heat treatment in the annealing process after ion implantation, the GaAs of the substrate and gooey metal materials such as At and Cr-Pt-Au react. As a result, it becomes impossible to maintain Schottky Maria. Currently, as a material whose interface does not change due to heat treatment,
W, WSix+W-AtTaSi+TaW-8
Various alloys such as X x are being developed. However, in addition to thermal properties, the necessary conditions for an enhancement WFET clear material used in gate-shaped GaAs O-thick ICs, etc. are (1) +7
7 barrier φ8 is required to be high, and (2) specific resistance ρS is required to be low. All of the above metals have excellent thermal properties (1
), (2) No material has been found that also serves as k.
上記材料のうちバリア障壁φ８が０．８ｅＶと高いＷＳ
ｉ は比抵抗ρ８が１５０Ω−αと高く、逆に比抵抗
が４０Ω−釧と低いＴ ａＷ−Ｓ ｉ ｘはｙＺ Ｉ）
ア障壁も０、６５ ｅＶと低い。その他の材料はいずれ
の特性も劣っている。Among the above materials, WS has a high barrier barrier φ8 of 0.8 eV
i has a high specific resistance ρ8 of 150Ω-α, and conversely, a low specific resistance of 40Ω-Six is yZ I)
The barrier is also low at 0.65 eV. Other materials are inferior in both properties.
エンハンスメントをＧａＡｓ Ｆ ’Ｅ Ｔの特性、動
作を安定にし、高歩留シ、高速ＩＣｉ実現し得る・？
リア障壁が高く、比抵抗の低いショットキーツマリア材
料が強く望まれている。Is it possible to enhance the characteristics and operation of GaAs F'ET and realize high yield and high speed ICi?
Schottky's Maria materials with high rear barrier and low resistivity are highly desired.
（発明の目的）
本発明はかかる要求を満たし、・マリア障壁が高く、比
抵抗の低いショットキー・マリア材料を用いた電界効果
トランジスタを提供するものである。(Objectives of the Invention) The present invention satisfies these requirements and provides a field effect transistor using a Schottky Maria material with a high Maria barrier and low resistivity.
（発明の構成）
本発明による電界効果型トランジスタはＧａＡｓ’ｉ活
性層とし、ショットキー・々リアｆ−ト電極として、Ｔ
ａＸＷｙＳｉｌ−ｘ−ｙ（０≦Ｘ≦１，０≦ｙ≦１）お
よび前記材料とは異なる組成を持つＴａｖＷ２Ｓｔ１−
ｖ−２（ｏ≦Ｖ≦１，０≦２≦１）の多層膜から構成さ
れている。(Structure of the Invention) The field effect transistor according to the present invention has a GaAs'i active layer and a Schottky rear f-electrode.
aXWySil-x-y (0≦X≦1, 0≦y≦1) and TavW2St1- with a composition different from the above material.
It is composed of a multilayer film of v-2 (o≦V≦1, 0≦2≦1).
（実施例の説明）
以下実施例に基づいて本発明を具体的に説明する。本発
明による一実施例のＧａＡｓＭＥＳＦＥＴ断面図を図に
示す。(Description of Examples) The present invention will be specifically described below based on Examples. A cross-sectional view of a GaAs MESFET according to an embodiment of the present invention is shown in the figure.
半絶縁性ＧａＡｓ基板１０上の活性層ｎ −ＧａＡｓ
１１上にケ９−トメタルとしてＷＳｉｏ、６層１２とＴ
ａ０．２０Ｗ０．７Ｏ８１０，１０層１３を順に付着せ
しめる。Active layer n-GaAs on semi-insulating GaAs substrate 10
WSio as a ketone metal on 11, 6 layers 12 and T
A0.20W0.7O810,10 layers 13 are deposited in sequence.
ＴａＯ，２０Ｗ０．７０Ｓｉ’０．１０１３およびＷＳ
ｉ、６１２はいずれも８００℃のアニール工程でＧａＡ
ｓとのショットキー特性が崩れることは無く、それぞれ
Ｏ，６５ｅｖ。TaO, 20W0.70Si'0.1013 and WS
i, 612 are both made of GaA in an 800°C annealing process.
The Schottky characteristics with s did not collapse, and the values were O and 65ev, respectively.
０．８ｅＶのバリア障壁を有する。エンハンスメント型
ＦＥＴの動作マージンを考えた時０．８ｅＶのＷＳｉｏ
、６の方が望ましいが、動作スぎ−ドを左右するシート
抵抗はＴａｏ、２ｏＷｏ、７ｏＳｌｏ、１ｏが４０μΩ
−ｍ。It has a barrier barrier of 0.8 eV. Considering the operating margin of enhancement type FET, WSio of 0.8eV
, 6 are more desirable, but the sheet resistance that influences the operating speed is 40 μΩ for Tao, 2oWo, 7oSlo, and 1o.
-m.
ＷＳｔ、、６が１５０μΩ−ｍと３．５倍の違いがある
。本発明で示すように、ダート電極を多層構造とし、第
１層のＷＳｉ、６１２を０．０１μｍ、第１層のＴａｏ
、２ｏＷｏ、７ｏＳ’ｏ、１ｏ １３ ｔ”−０，４μ
ｍとすることでショットキーバリア障壁はＷＳｔｏ、６
１２とＧａＡｓとの接触でＯ，８ｅＶとなシ、シート抵
抗は４２μΩ−ｍとＴａ０．２０Ｗ０．７０Ｓｉ０．１
０のシート抵抗の寄与によシ低く押さえることができる
。本実施例ではＷＳｉ、６１２、Ｔａｏ、２ｏＷｏ、ｚ
ｏｓ １ ｏ、、ｏ １３はＲＦスノｅツタ法で順に形
成した。スパッタ時の圧力はＡｒ雰囲気下で５Ｘ１０
ｔ、ｏｒｒ＋スパッタ出力はＷＳｌｏ、６１２は１００
Ｗ 、Ｔａ ｏ 、２０Ｗｏ 、ｙｏＳｌ ｏ 、１ｏ
ｌ ３は３００Ｗとし、それぞれ３分および３０分のス
パッタリングを行なった。ホトエツチング法とプラズマ
エツチング法によシダート電極の形状加工を行なりた後
、ＡｕＧｅ／Ａｕｉ蒸着し、リフトオフによシソ−スミ
極１４、ドレイン電極工５とする。このようにケ９−ト
電極のショットキー障壁が０．８Ｖと高く、シート抵抗
が４２μΩ−ｍと低いＭＥｓＦＥＴで、Ｎ −ｏｆｆ特
性の動作マージンが大きく、遅延速度も１５ ｐｓと高
速の素子が得られた。WSt, , 6 is 150 μΩ-m, which is a 3.5 times difference. As shown in the present invention, the dart electrode has a multilayer structure, the first layer is WSi, 612 is 0.01 μm thick, and the first layer is Tao.
, 2oWo, 7oS'o, 1o 13 t"-0,4μ
By setting m, the Schottky barrier becomes WSto, 6
The contact between No. 12 and GaAs is O, 8 eV, and the sheet resistance is 42 μΩ-m, Ta0.20W0.70Si0.1
The sheet resistance can be kept low due to the contribution of the sheet resistance of 0. In this example, WSi, 612, Tao, 2oWo, z
os 1 o, , o 13 were formed in order by the RF snow e-vine method. The pressure during sputtering was 5X10 under Ar atmosphere.
t, orr + sputter output is WSlo, 612 is 100
W, Tao, 20Wo, yoSlo, 1o
l3 was set to 300 W, and sputtering was performed for 3 minutes and 30 minutes, respectively. After shaping the cedar electrode by photo-etching and plasma etching, AuGe/Aui is deposited, and a bottom electrode 14 and a drain electrode 5 are formed by lift-off. In this way, the MEsFET has a high gate electrode Schottky barrier of 0.8 V and a low sheet resistance of 42 μΩ-m, has a large operating margin in the N-off characteristic, and has a high-speed delay speed of 15 ps. Obtained.
以上実施例’！ｉ−６げて本発明を具体的に説明したが
、本発明のＷ ＋ ’Ｔａ ＊ ＳｔＯ比はｗｓｉｏ、
６＋Ｔａ０．２０ＷＯ，７Ｏ８１０，１０に限らすＴ
ａ ＸＷｙｓ ｒ １− ｘ −ｙ （０≦Ｘ≦１゜０
≦ｙ≦１）のすべての組成で可能である。Above are examples! Although the present invention was specifically explained using i-6, the W+'Ta*StO ratio of the present invention is wsio,
6+Ta0.20WO, 7O810, T limited to 10
a XWys r 1- x -y (0≦X≦1゜0
All compositions with ≦y≦1) are possible.
（発明の効果）
以上述べたようにゲート電極としてＴａ ＋ Ｗ ＋Ｓ
ｔの組み合わせよりなる２層構造を採用することにより
、動作マージンが大きく、高速なＭＥＳＦＥＴが得られ
た。(Effect of the invention) As described above, Ta + W + S as the gate electrode
By adopting a two-layer structure consisting of a combination of t, a high-speed MESFET with a large operating margin was obtained.
図は本発明の一実施例であるＧａＡｓＭＥＳＦＥＴを示
す断面図である。
１Ｏ・・・半絶縁性ＧａＡｇ基板、１１・・・活性層
ｎ−ＧａＡｓ １２ ＝−ＷＳｉ 、１３−−− Ｔａ
、２ｏＷ、７ｏＳｉ、１（、ｓｏ、６
エ４・・・ソース電極、１５・・・ドレイン電極。The figure is a sectional view showing a GaAs MESFET that is an embodiment of the present invention. 1O... Semi-insulating GaAg substrate, 11... Active layer
n-GaAs 12 =-WSi, 13--- Ta
,2oW,7oSi,1(,so,6 E4...source electrode, 15...drain electrode.
Claims (1)
ｙＳ ｉ 、−ｘ−ｙ（０＜：ｘ＜：１，０くｙ＜：１
）よシなる第一の合金層と、前記第一の合金層と異な
る組成のＴａｖＷ２Ｓ ｉ 、 −ｖ−ｚ（０くｖく１
，０くｚく１）よシなる第二の合金層との二層構造を有
することを特徴とするショットキーバリアゲート型電界
効果トランジスタ。The active layer is made of GaAs, and the dart electrode is TaXW.
yS i , -x-y(0<:x<:1, 0kuy<:1
) with a different first alloy layer and TavW2S i , -v-z (0 x v x 1) with a different composition from the first alloy layer.
,0kuzku1) A Schottky barrier gate field effect transistor characterized by having a two-layer structure with a second alloy layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23990183A JPS60132375A (en) | 1983-12-21 | 1983-12-21 | Schottky barrier gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23990183A JPS60132375A (en) | 1983-12-21 | 1983-12-21 | Schottky barrier gate field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60132375A true JPS60132375A (en) | 1985-07-15 |
Family
ID=17051537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23990183A Pending JPS60132375A (en) | 1983-12-21 | 1983-12-21 | Schottky barrier gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60132375A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6271281A (en) * | 1985-09-24 | 1987-04-01 | Nec Corp | Compound semiconductor device |
| JPS62131452U (en) * | 1986-02-13 | 1987-08-19 | ||
| US4923823A (en) * | 1987-09-30 | 1990-05-08 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating a self aligned semiconductor device |
| US5631479A (en) * | 1995-04-26 | 1997-05-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with laminated refractory metal schottky barrier gate electrode |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57128071A (en) * | 1981-01-30 | 1982-08-09 | Fujitsu Ltd | Field-effect type semiconductor device and manufacture thereof |
-
1983
- 1983-12-21 JP JP23990183A patent/JPS60132375A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57128071A (en) * | 1981-01-30 | 1982-08-09 | Fujitsu Ltd | Field-effect type semiconductor device and manufacture thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6271281A (en) * | 1985-09-24 | 1987-04-01 | Nec Corp | Compound semiconductor device |
| JPS62131452U (en) * | 1986-02-13 | 1987-08-19 | ||
| US4923823A (en) * | 1987-09-30 | 1990-05-08 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating a self aligned semiconductor device |
| US5631479A (en) * | 1995-04-26 | 1997-05-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with laminated refractory metal schottky barrier gate electrode |
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