JPS60147164A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce plane-shaped superposition among source-drain diffusion regions and gate electrode, and to miniaturize a semiconductor device and increase the speed of the semiconductor device by implanting the ions of an impurity for forming the source-drain diffusion regions into a semiconductor base body and executing isotropic etching. CONSTITUTION:The surface of a single crystal silicon base body 1 is thermally oxidized, a gate oxide film 2 is formed, and a gate electrode 3 is shaped through patterning. A polycrystalline silicon film 5 is etched through an anisotropic strong reactive-ion- etching method using a CCl4 group etching gas. The ions of boron as a P type conduction type impurity are implanted. The surface of the base body coated with the gate electrode 3 and side wall 6 is masked at that time, and boron is implanted only into regions on the outsides of the masked surface of the base body while penetrating an silicon nitride film 4 and the silicon oxide film 3 to form a source region 7 and a drain region 8. The side walls 6 consisting of polycrystalline silicon are removed through etching by a hydrofluoric acid-nitric acid group etching liquid. The silicon nitride film 4 is removed through etching by hot nitric acid. An silicon oxide film 9 containing phosphorus is deposited on the whole surface of the base body for protecting an element, and thermally treated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an MO8 field effect transistor.

(Prior art) Currently, as an M08 device, silicon gate MO8)
Transistors are commonly used.

A silicon gate MOS transistor has a gate electrode made of polycrystalline silicon, and can form source/drain diffusion regions in self-alignment with the polycrystalline silicon gate electrode.
It has various advantages such as being suitable for higher integration and higher speed devices.

A summary of the conventional method for manufacturing a silicon gate MOS transistor will be explained below. First, as shown in Figure 1,
- Gate insulating film 2 on the surface of the conductive single crystal silicon substrate 1
is formed, and a polycrystalline silicon film is grown on the gate insulating film 2. Next, the polycrystalline silicon film is patterned into a desired gate electrode shape, and using the polycrystalline silicon gate electrode 3 as a mask, impurities of the conductivity type opposite to that of the base are ion-implanted into the Nd silicon base. A source region 7 and a drain region 8 are formed. Next, heat treatment was performed to activate the implanted impurities, the transistor was covered with an insulating film, and contact holes were formed on the gate electrode, source region, and drain region. Form gate, source and drain electrode terminals (not shown).

Such conventional manufacturing methods are very commonly used and have contributed to the development of MOS devices.

However, as transistors have been miniaturized in order to achieve higher integration and higher performance of MOS devices, several disadvantages have arisen in transistors manufactured using conventional manufacturing methods. One is the limit of miniaturization of the length of the gate electrode in the channel direction (hereinafter referred to as gate length). In Figure 1! 9 indicates the protrusion of impurities that form the source and drain into the channel, and this is due to the heat treatment for activating the impurities and the heat treatment during other manufacturing processes, when the ions are initially implanted. This is caused by thermal diffusion from the distribution state of . Therefore, the effective channel length of the transistor is the gate length minus twice l. The effective channel length must be set to a size that does not cause punch-through between the source and drain, so the minimum gate length is longer than the minimum effective channel length! , which is disadvantageous in terms of miniaturization.

Another disadvantage is that the source/drain impurities protrude toward the channel. As transistors become smaller, gate 1! A planar curved area between the pole and the source/drain region! The capacitive coupling formed in the transistor cannot be ignored compared to the capacitance of other parts, and becomes a major obstacle to increasing the switching speed of the transistor.

In order to eliminate the above-mentioned disadvantages, there is a need for a method for manufacturing a transistor having a structure in which the 1-line portion l between the gate electrode and the source/drain is as small as possible or undesirably undesirable.

(Object of the Invention) Since MO transistors manufactured by the prior art have the above-mentioned disadvantages, an object of the present invention is to
It is an object of the present invention to provide a method for easily manufacturing a MOS transistor having a structure suitable for miniaturization and speeding up, with a small planar overlap between a drain diffusion region and a gate electrode.

(Structures of the Invention) MO8) The object of the present invention is achieved by including at least one of the following steps after patterning the gate electrode in manufacturing a transistor. That is, the etching in the step of depositing a thin film of the first material so as to cover the entire surface of the semiconductor substrate and the subsequent etching step has selectivity with respect to the first material. depositing a film made of a second material thicker than the first film, and then anisotropic etching to leave the second film only on the side surfaces of the gate electrode; Next, using the flI wall made of the first material and the second material left on the gate electrode and its side surface as a mask, the first material film 1i1 is penetrated. C1 A step of ion-implanting impurities for forming source and drain diffusion regions into the half-barrel body substrate, and then a step of removing the sidewall made of the second feather material by isotropic etching, and then an equal step of and etching away the first tung metal film by directional etching.

(Example) A first embodiment of the present invention will be described using the drawings.

In the following examples, P-channel silicon group)
MO8) A method for manufacturing a transistor will be described.

First, as shown in FIG. 2, the surface of a single-crystal silicon substrate 1 doped with an NW conductivity type impurity is thermally oxidized to form a 300 mm thick gate oxide film 2. Next, a polycrystalline silicon film was deposited to a thickness of 500 OA, doped with phosphorus, and
After imparting Sakai conductivity, it is patterned into a desired shape to form the gate electrode 3.

Next, as shown in FIG.
A polycrystalline silicon film 5 having a thickness of ^ is deposited by a normal vapor phase growth method.

Next, as shown in FIG. 4, the polycrystalline silicon film 5 is etched by a highly anisotropic reactive ion etching method using a CCl4-based etching gas.
At this time, on the side surface of the gate electrode 3, the polycrystalline silicon film 5t;f: Since the substantial thickness in the vertical direction is also thicker in other areas, etching was performed to remove a film thickness of 5000A. It remains as a side wall 6 afterwards. side wall 6
Although the width W varies somewhat depending on the amount of etching, in this example, it could be set to about 0.3 μm. At this time, the silicon nitride film 4 is left almost unetched, and the silicon substrate 1 and the gate electrode 3 made of polycrystalline silicon and silicon can be protected from damage caused by etching.

Next, as shown in Fig. 5, boron, which is a P-type 4-round impurity, was heated at 5
Only ions are implanted. At this time, the substrate surface 1 surrounded by the gate electrode 3 and sidewalls 6 is masked, and boron is poured into only the outer region through the silicon nitride film 4 and silicon oxide @3, and the source region 7 and A drain region 8 is formed.

Next, as shown in FIG. 6, the side walls 6 of the polycrystalline silicon are etched away using a VC, hydrofluoric acid-nitric acid based etching solution. At this time, the silicon nitride [4ii] polycrystalline silicon gate electrode is prevented from being etched. Next, the silicon oxide film 4 is removed by etching with hot phosphoric acid.

Next, as shown in FIG. 1, a silicon oxide film 9t-1 containing phosphorus is deposited over the entire surface of the substrate for protection of the device using the usual vapor phase growth method. Thereafter, heat treatment is performed in an oxidizing atmosphere at 900° C. to densify the silicon oxide film 9 and to activate the boron introduced as source/drain impurities. As a result of this heat treatment, boron, which is an impurity in the source and drain, is re-diffused and spread, and the vertical depth is approximately 0.
It also spreads to the same extent in the lateral direction with n, -* of 4 μm, resulting in a structure in which the ends of the source/drain diffusion regions and the ends of the gate electrode 3 almost coincide. The subsequent contact opening and metal wiring forming steps can be carried out by any method, and therefore their explanation will be omitted.

As mentioned above, P produced by the method shown in this example
The channel type MO8) transistor has an ideal structure in which there is almost no planar overlap between the gate electrode and the source/drain, which is a drawback of conventional manufacturing methods. This is because in the conventional method, the source/drain impurities are introduced at the position where they contact the end of the gate electrode, and re-diffusion by heat treatment begins from there, whereas in the improved present invention, the impurities are introduced and then This is because the method uses a method in which the temperature reaches the end of the gate electrode as a result of the temperature spread by re-diffusion caused by the heat treatment. In addition, in this example, the position where the source/drain impurity is initially introduced is determined by the thickness of the silicon nitride film and polycrystalline silicon film deposited after the gate electrode is patterned. Consistently determined.

Although the present invention has been described above based on Examples, the present invention is not limited thereto. For example, in the above embodiment, P channel type MO8? As described above, the method for manufacturing a transistor is to make the substrate P-type and replace the source/drain diffusion impurities with N-type conductivity type arsenic, phosphorus, etc.
This is a method for manufacturing an N-channel MOS transistor. Further, in the above embodiment, a combination of a silicon nitride film and a polycrystalline silicon film was used as a deposited film for forming sidewalls.
[It is also possible to use a combination of materials such as nitride film and aluminum of type 211 that can provide a sufficient difference in etching rate in the etching process for wall formation. Further, the film thickness and the like can be changed depending on the purpose. Furthermore, it is also possible to add other steps to this embodiment without departing from the gist of the present invention.

A second example in which other steps are added to the first example will be described below. 5 o
ke V (boron with D acceleration energy lXl0/c
Only J is kidnapped. The following steps are similar to those in the first embodiment to manufacture a P-channel MOS transistor. FIG. 8 shows the cross-sectional structure of the transistor according to the second embodiment manufactured in this manner. Here, the previously ion-implanted low concentration boron diffusion region 10 of 1×10/cnt is replaced by the high concentration source region 7. The drain region 8 and the channel region of the transistor are reliably connected to prevent a so-called offset structure in which the source/drain is separated from the channel. Here, if the impurity concentration is about the same as this boron diffusion region, lateral diffusion due to heat treatment during the process can be ignored. By adding this step, there is no need to worry about making the transistor an offset gate, and the degree of freedom in selecting the thickness of the sidewall forming material film and heat treatment conditions increases.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a MOS transistor used to explain the conventional method, FIGS. 2 to 7 are cross-sectional views shown in the order of steps to explain the first embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view of a MOS transistor shown to explain a second embodiment of the invention. i-=゛° single crystal silicon substrate, 2... gate oxide film, 3... gate electrode, 4... silicon oxide film, 5... Polycrystalline silicon film, 6°
゛°°°Polycrystalline silicon side 1k, 7.8...
Source/drain diffusion region, 9---°-silicon oxide film, 10°゛°"°°low concentration source/7 drain diffusion region. 71θ2-710 etc.

Claims (1)

[Claims] A step of forming a gate electrode on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, a step of depositing a thin film made of a first material on the surface including the gate electrode, and etching in a subsequent etching step. depositing a film of a second material that is selective with the first material;
etching away the second material film by anisotropic etching, leaving only the side surface portions of the gate electrode; A step of ion-implanting impurities for forming source and drain diffusion regions into the semiconductor substrate through the first material film using the sidewall made of the second material left in the step as a mask, etc. A method for manufacturing a semiconductor device, comprising at least the steps of removing the side wall made of the second material by anisotropic etching, and removing the first material film by isotropic etching.