JPS60144821A - Electronic disk device - Google Patents

Electronic disk device

Info

Publication number
JPS60144821A
JPS60144821A JP59001217A JP121784A JPS60144821A JP S60144821 A JPS60144821 A JP S60144821A JP 59001217 A JP59001217 A JP 59001217A JP 121784 A JP121784 A JP 121784A JP S60144821 A JPS60144821 A JP S60144821A
Authority
JP
Japan
Prior art keywords
disk
circuit
information
control
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59001217A
Other languages
Japanese (ja)
Inventor
Yasuhisa Watanabe
渡邊 康久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59001217A priority Critical patent/JPS60144821A/en
Publication of JPS60144821A publication Critical patent/JPS60144821A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To allow information to be written double and to improve its reliability by providing two sets of disk control parts and electronic disk parts and performing simultaneous writing operation in write mode, and switching one set to the other in case of incorrectable reading operation. CONSTITUTION:A control part switching circuit 5 once receiving an instruction from a channel sends an instruction to control circuits 11 and 21 of disk control parts 1 and 2. The circuits 11 and 21 decode the instruction and when the instruction is a write instruction, address information on a necessary disk is received from the channel and converted into a memory address, which is sent out to write/read circuits 31 and 41 through an electronic disk switch circuit 12 or 22 together with write information, thereby writing the information simultaneously. Error correction codes read by the circuits 31 and 41 at the same time are used to detect whether an error occurs or not in read mode, and if there is an incorrectable error, it is reported to control parts 1 and 2. At this time, the circuit 5 selects the control part 1, so it is switched to the side of the control part 2.

Description

【発明の詳細な説明】 発明の属する技術分野 本発明は、データ処理装置におけるディスク装置に関す
るものであり、特に、高信頼性の電子ディヌク装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a disk device in a data processing device, and more particularly to a highly reliable electronic Dinuk device.

従来技術の説明 従来、この種のデータ処理装置は高速大容量の外部記憶
装置として磁気ディスク装置を使用してきたが、磁気デ
ィスク装置に記憶した情報が非常に重要な場合には信頼
性を高めるために情報の二重書を行ってきた。即ち、二
台の磁気ディスク装置に同じ情報を書込み、一台の磁気
ディスク装置からの情報が正しく読出せなかった時にも
う一台の磁気ディスクから読出す様に、通常ソフトウェ
アにより制御されていた。従って、この様に情報の二重
書を行う場合にIfim気ディスク装置が二台必要なだ
けでなく、書込時に同じ処理を別々の装置に二度行うた
めに大幅な性能低下が避けられなかった。
Description of the Prior Art Conventionally, this type of data processing device has used a magnetic disk device as a high-speed, large-capacity external storage device, but when the information stored in the magnetic disk device is extremely important, it is necessary to use a magnetic disk device to improve reliability. We have been duplicating information. That is, the same information is written to two magnetic disk drives, and when information cannot be read correctly from one magnetic disk drive, it is normally controlled by software so that it is read from the other magnetic disk drive. Therefore, when performing double writing of information in this way, not only are two Ifim disk devices required, but the same process is performed twice on different devices at the time of writing, which inevitably causes a significant drop in performance. Ta.

発明の目的 本発8Aは従来の上記事情に鑑みてなされたものであり
、従って本発明の目的は、半導体メモリや磁気バブル等
で構成される電子ディスク部とこれを制御するディスク
制御部の組を二つ組込み、該二組のディスク制御部を通
して電子ディスク部に同時に情報の書込を行い、読出し
時に一組のディスク制御部と電子ディスク部を選択し、
正しく読出せなかったときに別な組のディスク制御部と
電子ディスク部を選択して情報の読出しを行える構成を
とることにIジ、上記欠点を除去し、性能低下を招くこ
となく情報の二重書を行い得る高信頼度の新規なディス
ク装置を提供することにある。
Object of the Invention The present invention 8A has been made in view of the above-mentioned conventional circumstances, and therefore, the object of the present invention is to provide a combination of an electronic disk section composed of a semiconductor memory, a magnetic bubble, etc., and a disk control section that controls the electronic disk section. , write information simultaneously to the electronic disk unit through the two sets of disk control units, select one set of the disk control unit and the electronic disk unit at the time of reading,
By adopting a configuration that allows information to be read by selecting a different set of disk control unit and electronic disk unit when the data cannot be read correctly, the above-mentioned drawbacks can be removed and information can be read out without deteriorating performance. An object of the present invention is to provide a highly reliable new disk device that can perform overwriting.

発明の構成 上記目的を達成する為に、本発明に係る電子ディスク装
@は、メモリ回路と書込時に該メモリ回路に情報の書込
を制御するとともにエラー訂正情報を付加する機能をも
ち、しかも読出時に前記メモリ回路に書込まnた情報の
胱出しを制御すると共に読出情報のエラー検出、訂正機
能をもつ書込読出回路とから構成される二つの電子ディ
スク部と、チャネルからの命令を解読しディヌク情報の
アドレスをメモリアドレスに変換する制御回路と該制御
回路からの切替指示により前記二つの電子ディスク部と
の接続を切替える電子ディスク切替回路とから構成さn
る二つのディスク制御部と、該二つのディスク制御部が
同時に同じ動作をする様に同期を制御する同期化回路と
、前記二つのディヌク制御部のエラーを検出するエラー
検出回路と、該エラー検出回路からの切替指示により前
記二つのディスク制御部とチャネルとの接続を切替える
制御部切替回路とを具備して構成される。
Structure of the Invention In order to achieve the above object, an electronic disk drive according to the present invention has a memory circuit and a function of controlling writing of information to the memory circuit at the time of writing and adding error correction information. Two electronic disk units consisting of a write/read circuit that controls the output of the information written in the memory circuit at the time of reading and also has error detection and correction functions for the read information, and deciphers commands from the channel. and an electronic disk switching circuit that switches the connection with the two electronic disk units according to a switching instruction from the control circuit.
two disk control units, a synchronization circuit that controls synchronization so that the two disk control units perform the same operation at the same time, an error detection circuit that detects an error in the two Dinuk control units, and the error detection circuit. The device is configured to include a control section switching circuit that switches the connection between the two disk control sections and the channel in response to a switching instruction from the circuit.

次に本発明をその好ましい一実施例について図面を参照
して詳細に説明する。
Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

第1図は本発明の一実施例を示すブロック構成図である
FIG. 1 is a block diagram showing one embodiment of the present invention.

図中、参照番号1及び2はディスク制御部を示し、該デ
ィスク制御部1及び2はそれぞれ制御回路11.21及
び電子ディヌク切替回路12.22から構成される。
In the figure, reference numbers 1 and 2 indicate disk control units, and the disk control units 1 and 2 are each comprised of a control circuit 11.21 and an electronic Dinuk switching circuit 12.22.

3及び4G−j、電子ディスク部でおり、そnぞれ書込
、読出回路31.41及びメモリ回路32.42から構
成される。
3 and 4G-j are electronic disk units, each consisting of a write/read circuit 31.41 and a memory circuit 32.42.

5F1制御部切替回路を示し、該制御部切替回路5けチ
ャネルと信号線101で接続され、制御回路11及び2
1とそれぞれ信号線102及び103−で接続さnる。
5F1 shows a control unit switching circuit, which is connected to the five channels of the control unit switching circuit by a signal line 101, and is connected to the control circuits 11 and 2.
1 through signal lines 102 and 103-, respectively.

制御回路11及び211I′i電子ディスク切替回路ν
及び22とそれぞれ信号線105及び106で接続され
、更にそnぞれ切替指示信号線114及び115で接続
さnる。 ゛ 書込、読出回路31は、電子ディヌク切替回路12及び
ηと信号線107で接続され、更にメモリ回路部と信号
線109で接続される。同様に、書込、読出回路41け
、電子ディスク切替回路12及び22と信号線108で
接続され、更にメモリ回路42と信号線110で接続さ
れる。
Control circuit 11 and 211I′i electronic disk switching circuit ν
and 22 by signal lines 105 and 106, respectively, and further connected by switching instruction signal lines 114 and 115, respectively. The write/read circuit 31 is connected to the electronic digital switching circuit 12 and η via a signal line 107, and further connected to the memory circuit section via a signal line 109. Similarly, the write/read circuit 41 is connected to the electronic disk switching circuits 12 and 22 by a signal line 108, and further connected to the memory circuit 42 by a signal line 110.

6は同期化回路を示し、該同期化回路6は信号線104
により制御回路11及び21と接続される〇7けエラー
検出“回路を示し、該エラー検出回路7′は、制御回路
11と信号線用で、制御回路21と “□゛信号線11
2でそnぞれ接続され、制御部切替回路5と信号線11
3で接続される。
6 indicates a synchronization circuit, and the synchronization circuit 6 is connected to the signal line 104.
The error detection circuit 7' is connected to the control circuits 11 and 21, and the error detection circuit 7' is for the control circuit 11 and the signal line.
2 are connected respectively to the control section switching circuit 5 and the signal line 11.
Connected by 3.

次に本発明の動作を順を追って説明する。Next, the operation of the present invention will be explained step by step.

ディスク制御部1及び2は、同期化回路6により同じリ
セット信号と同じクロック信号が与えられ、全く同じ動
作をする様制御されている。今、ディスク制御部1を主
デイスク制御部、ディスク制御部2を副デイスク制御部
とし、又電子ディスク部3を主電子ディスク部、電子デ
ィスク部4を副電子デイヌタ部とする。制御部切替回路
5は、通常主デイスク制御部1側を選択し、チャネルか
らの受取情報のみを副ディヌク制御部2へ送ることが出
来るものとする。
The disk controllers 1 and 2 are given the same reset signal and the same clock signal by the synchronization circuit 6, and are controlled to operate in exactly the same way. Now, the disk control section 1 is assumed to be a main disk control section, the disk control section 2 is assumed to be a sub-disk control section, the electronic disk section 3 is assumed to be a main electronic disk section, and the electronic disk section 4 is assumed to be a sub-electronic denulter section. It is assumed that the control section switching circuit 5 normally selects the main disk control section 1 side and can send only the received information from the channel to the sub-dinuk control section 2.

該制御部切替回路5は、チャネルから命令を受取ると、
ディスク制御部1及び2の制御回路11及び21に該命
令を送出する0制御回路11及び21は、該命令を受取
ると、これを解読し、書込命令であれば、チャネルから
必要なディスクのアドレス情報即ちシリンダ番号、トラ
ンク番号、しコード番号等を受取り、これを予め決めら
nた変換方法でメモリアドレスに変換し、該メモリアド
レスをそ7tそれ電子ディスク切替回路12又は22を
通して書込、読出回路31及び41に送出し、続いてチ
ャネルから送られる書込情報を前記書込、読出回路31
及び41に順次送出する。このとき、王ディヌク制御部
1の電子ディスク切替回路12は主電子ディヌク部3を
選択し、副デイスク制御部2の電子ディスク切替回路2
2 HmJJ fi子ディスク部4を選択しているもの
とする。書込、読出回路31及び41 tl′i、受取
ったメモリアドレスによりそれぞnメモリ回路32及び
42をアドレスし、続いて受取った祐込情報をメモリ回
路32及び42に順次切込む。この時、同時にエラー訂
正符号を作成し、書込情報に付加して書込む。
When the control unit switching circuit 5 receives a command from the channel,
When the control circuits 11 and 21, which send the command to the control circuits 11 and 21 of the disk control units 1 and 2, receive the command, they decode it and, if it is a write command, send the required disk from the channel. Receive address information, such as cylinder number, trunk number, code number, etc., convert it into a memory address using a predetermined conversion method, and write the memory address through the electronic disk switching circuit 12 or 22; The write information sent from the channel is sent to the read circuits 31 and 41, and the write information sent from the channel is sent to the read circuit 31.
and 41 in sequence. At this time, the electronic disk switching circuit 12 of the king dinuk control section 1 selects the main electronic dinuk section 3, and the electronic disk switching circuit 12 of the sub disk control section 2 selects the main electronic dinuk section 3.
2 HmJJ fi child disk section 4 is selected. The write and read circuits 31 and 41 tl'i address the n memory circuits 32 and 42, respectively, using the received memory address, and then sequentially insert the received write information into the memory circuits 32 and 42. At this time, an error correction code is simultaneously created and added to the write information and written.

制御回路11及び21がチャネルからの読出命令を受取
ると、書込時と同様にチャネルから必ahディヌクのア
ドレス情報を受取り、これをメモリアドレスに変換し、
該メモリアドレスをそれぞれ書込、読出回路31及び4
1に送出する。該書込、読出回路31及び41ハ、受取
ったメモリアドレスによりそれぞれメモリ回路32及び
42をアドレスし、情報を銃出し、電子ディスク切替回
路12及び22にそnぞれ送出する。この時、前記書込
、読出回路31及び41は、同時に読出されたエラー訂
正符号によりエラーの有無を検査し、訂正可能エラーが
あればエラー情報を訂正し、訂正不能エラーがあればそ
の旨をそれぞnディヌク制御部1及び2に通知する。デ
ィヌク制御部1及び2はそれぞれ受取った読出情報を制
御部切替回路5に送るが、該制御部切替回路5はいま主
ディヌク制御部1を選択しているためにディヌク制御部
1からの読出情報をチャネルに送出する0この時、訂正
不能エラーが畳込、読出回路31から通知されると、制
御回路11は、再試行動作を行い、再び同じ情報を読出
して再度訂正不能エラーを受取ると再試行動作をくり返
充再試行回数を予め規定しておき、該規定回数に達した
とき、訂正不能読出エラーの発生したことをチャネルを
通してソフトウェアに通知すると共に、゛エラー検出回
路7を通して制御部切替回路5を副デイスク制御部選択
側に切替えさせる。
When the control circuits 11 and 21 receive a read command from the channel, they receive the necessary address information from the channel in the same way as when writing, convert it into a memory address,
Write and read circuits 31 and 4 respectively write the memory address.
Send to 1. The write and read circuits 31 and 41 address the memory circuits 32 and 42, respectively, with the received memory address, output information, and send it to the electronic disk switching circuits 12 and 22, respectively. At this time, the write and read circuits 31 and 41 check the presence or absence of an error using the error correction code read out at the same time, correct the error information if there is a correctable error, and indicate that if there is an uncorrectable error. Notification is made to the nDinuku control units 1 and 2, respectively. The Dinuk control units 1 and 2 each send the received read information to the control unit switching circuit 5, but since the control unit switching circuit 5 is currently selecting the main Dinuk control unit 1, the read information from the Dinuk control unit 1 is sent to the control unit switching circuit 5. At this time, when an uncorrectable error is notified from the convolution/readout circuit 31, the control circuit 11 performs a retry operation, reads the same information again, and if it receives an uncorrectable error again, the control circuit 11 performs a retry operation. The number of times the trial operation is repeated and retried is predetermined, and when the predetermined number of retries is reached, the occurrence of an uncorrectable read error is notified to the software through the channel, and the controller is switched through the error detection circuit 7. The circuit 5 is switched to the sub disk control section selection side.

一般に、前記訂正不能読出エラーの通知を受けたソフト
ウェアは再試行を行うが、前記制御部切替回路5tI′
i副ディスク制御部2を選択しており、該副デイスク制
御部2は副電子ティヌク部4を選択しているために、ソ
フトウェアによる再試行に1って副電子ディスク部4か
らの正しい読出し情報をチャネルへ送出することができ
る。
Generally, the software that receives the notification of the uncorrectable read error makes a retry, but the control section switching circuit 5tI'
Since the i secondary disk control unit 2 is selected and the secondary disk control unit 2 selects the secondary electronic tinook unit 4, correct read information from the secondary electronic disk unit 4 is not obtained even after a retry by the software. can be sent to the channel.

以上の説明では、訂正不能読出エラー検出時に主デイス
ク制御部と主′電子ディスク部の系を副デイスク制御部
と副電子ディスク部の系に切替える方式であるが、主デ
イスク制御部にて訂正不能読出エラー検出による再試行
が前記規定回数に達した時に、電子ディスク切替回路を
副電子ディスク部選択に切替えることにより、制御部切
替回路にIるディ7り制御部の切替をすることなく、正
しい情報をチャネルに送出する方式をとることも可能で
ある。
In the above explanation, when an uncorrectable read error is detected, the system of the main disk control unit and the main electronic disk unit is switched to the system of the sub disk control unit and the sub electronic disk unit, but the error cannot be corrected by the main disk control unit. When the number of retries due to read error detection reaches the predetermined number, the electronic disk switching circuit is switched to the sub electronic disk section selection. It is also possible to send information to a channel.

又、前記説明では、電子ディスク部からの訂正不能読出
エラーに対する切替機能について述べたが、主デイスク
制御部の障害によ−り■込、読出し動作が行えない場合
に於いても、エラー検出回路を通して制御部切替回路を
副ディヌク制御部側へ切替えることにより、上位装置か
らの動作が可能となる。
In addition, in the above explanation, the switching function for uncorrectable read errors from the electronic disk unit was described, but even in the case that loading and reading operations cannot be performed due to a failure in the main disk control unit, the error detection circuit By switching the control section switching circuit to the sub-Dinuk control section side through the control section, operation from the host device becomes possible.

発明の効果 本発明は、以上説明したように、ディスク制御部と電子
ティヌク部の組を二つもち岩込時に同時に同じ情報を書
込ませ、訂正不能読出エラー検出時にディスク制御部と
電子ディスク部の組を切替えて、再試行できる構成をと
ることにより、性能低下を招かずに情報の二重書をする
ことができ、高い信頼性をもつことができるという効果
がsb
Effects of the Invention As explained above, the present invention has two sets of the disk control section and the electronic disk section, writes the same information simultaneously at the time of writing, and when an uncorrectable read error is detected, the disk control section and the electronic disk section By adopting a configuration that allows retry by switching the set of

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック構成図である
。 1.2・・・ディスク制御部、3.4・・・電子ディス
ク蔀、5・・・制御部切替回路、6・・・同期化回路、
7・・・エラー検出回路、11.21・・・制御回路、
12.22・・・電子ディスク部切替回路、31.41
・・・書込、読出回路、32.42・・・メモリ回路 特許出願人 日不厖気株式会社 代 理 人 弁理士 熊谷雄太部
FIG. 1 is a block diagram showing one embodiment of the present invention. 1.2...Disk control unit, 3.4...Electronic disk cover, 5...Control unit switching circuit, 6...Synchronization circuit,
7...Error detection circuit, 11.21...Control circuit,
12.22...Electronic disk section switching circuit, 31.41
...Writing, reading circuit, 32.42...Memory circuit Patent applicant: Nichifu Kuuki Co., Ltd. Representative: Patent attorney Yutabe Kumagai

Claims (1)

【特許請求の範囲】[Claims] メモリ回路と書込時に該メモリ回路に情報の1゜込を制
御するとともにエラー訂正情報を付加する機能をもち且
つ読出時に前記メモリ回路に書込まnた情報の読出しを
制御するとともに読出情報のエラー検出、訂正機能をも
つ書込、読出回路とから構成される二つの電子ディスク
部と、チャネルからの命令を解読しディスク情報のアド
レスをメモリアドレスに変換する制御回路と該制御回路
からの切替指示にIり前記二つの電子ディスク部との接
続を切替える電子ディスク切替回路とから構成される二
つのディスク制御部と、該二つノティスク制御部が同時
に同じ動作をする様に同期を制御する同期化回路と、前
記二つのディヌク制御部のエラーを検出するエラー検出
回路と、該エラー検出回路からの切替指示にxg前記二
つのディスク制御部とチャネルとの接続を切替える制御
部切替回路とを具備することを特徴とした電子ディスク
装置。
It has a function of controlling the input of information into the memory circuit when writing to the memory circuit and adding error correction information, and when reading, it controls the reading of the information written to the memory circuit and corrects errors in the read information. Two electronic disk units consisting of write and read circuits with detection and correction functions, a control circuit that decodes commands from the channel and converts disk information addresses into memory addresses, and switching instructions from the control circuit. and a synchronization control unit that controls synchronization so that the two notisque control units perform the same operation at the same time. an error detection circuit that detects an error in the two disc control units; and a control unit switching circuit that switches the connection between the two disk control units and the channel in response to a switching instruction from the error detection circuit. An electronic disk device characterized by:
JP59001217A 1984-01-06 1984-01-06 Electronic disk device Pending JPS60144821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59001217A JPS60144821A (en) 1984-01-06 1984-01-06 Electronic disk device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59001217A JPS60144821A (en) 1984-01-06 1984-01-06 Electronic disk device

Publications (1)

Publication Number Publication Date
JPS60144821A true JPS60144821A (en) 1985-07-31

Family

ID=11495295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59001217A Pending JPS60144821A (en) 1984-01-06 1984-01-06 Electronic disk device

Country Status (1)

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JP (1) JPS60144821A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6115227A (en) * 1984-06-29 1986-01-23 Fujitsu Ltd Backup system of data file
JPH0675804A (en) * 1992-07-08 1994-03-18 Internatl Business Mach Corp <Ibm> Memory control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6115227A (en) * 1984-06-29 1986-01-23 Fujitsu Ltd Backup system of data file
JPH0675804A (en) * 1992-07-08 1994-03-18 Internatl Business Mach Corp <Ibm> Memory control system

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