JPS6014461A - Complementary insulated gate field-effect transistor - Google Patents

Abstract

PURPOSE:To operate the titled transistor at the normal supply voltage even at a short channel length as well as to prevent generation of a latchup phenomenon by a method wherein an N type drain region and a P type drain region, having the maximum impurity density of impurity diffusion region within the specified range respectively, are provided and a part of each drain region is connected to a high melting point metal or its silicide layer. CONSTITUTION:The titled transistor has an N type drain region having the maximum impurity density of an impurity diffusion region 10<18>-10<20>cm<-3> or thereabout and a P type drain region having the maximum impurity density of 10<17>-10<19>cm<-3> or thereabout, and it is constituted in such a manner that at least a part of said drain regions is connected to a high melting point metal or its metal silicide layer. After ions have been implanted, an activation and a heat treatment are performed on the implanted ions, and an N conductive type source 4 and drain 5 are formed. The quantity of arsenic ion is set in such a manner that the impurity density on the surface of said source 4 and drain 5 will be finally formed at 3X10<18>cm<-3> when channel length is 0.5mum or above and at 1-10<18>cm<-3> when channel length is 0.3mum or below. Also, the condition of heat treatment is controlled in such a manner that the junction depth of the source 4 and the drain diffusion layer 5 will be finally formed at 0.25mum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a complementary insulated gate field effect transistor (hereinafter referred to as CMO3 transistor).
The present invention relates to a high-voltage ultra-fine CMOS transistor that can operate with a 5V power supply even with a gate length of m or less.

[Background of the invention]

CMOS is P-channel MOS (hereinafter referred to as PMOS)
In this structure, an N-channel MOS (hereinafter referred to as NMOS) is formed as a pair on the same chip.

Figure 1 shows a conventional CMO with a gate length of 2 μm or more.
It is a cross-sectional structure diagram of S.

In FIG. 1, 1 is an N conductivity type semiconductor substrate, and 2 is a P conductivity type diffusion layer region formed in the semiconductor substrate 1, which is called a well. 3 is a field oxide film, and 4 and 5 are NMOS source and drain diffusion layer regions formed in the well 2, which have n conductivity type and have a maximum impurity concentration of 1.
020 cm-3 or more. 6 and 7 are PMO
The S source and drain diffusion layer regions have P conductivity type and have a maximum impurity concentration of 1019 cm-3 or more. 8 and 9 are a gate insulating film and a gate electrode, respectively. 10 and 11 are a protective insulating film and a source or drain electrode, respectively.

A CMOS transistor having a conventional structure having such a structure of impurity concentration in the drain diffusion layer has various drawbacks as the device becomes smaller.

(1) As the breakdown voltage reducing element between the source and drain becomes smaller, the channel length decreases.
Punch-through pressure decreases. Although the punch-through breakdown voltage can be improved by increasing the substrate concentration, increasing the substrate concentration conversely reduces the avalanche breakdown voltage. In an extremely small NMOS with a channel length of 0.3 μm or less, the source-drain breakdown voltage is extremely low to 2V or less, and therefore cannot operate at a normal power supply voltage of 5V.

Note that when the substrate concentration is increased to improve the punch-through breakdown voltage, the channel conductance gm decreases, so the high-speed operation characteristics obtained by miniaturization of insulated gate field effect transistors (hereinafter simply referred to as transistors) are inhibited. Ru.

(ii) Transistor destruction due to latch-up The biggest drawback of CMOS transistors having a conventional structure is destruction of the transistor due to thyristor operation called latch-up. This latch-up phenomenon becomes particularly noticeable as CMOS transistors become smaller. In other words, in a CMOS transistor in which the distance between NMOS and PMOS is shortened, NM
OS drain 5, well 2, semiconductor substrate 1, and P
A parasitic thyristor having an NPNP structure is formed between the source 6 or drain 7 of the MOS. The above-mentioned thyristor starts operating when triggered by the application of an overvoltage, the occurrence of an internal transient overvoltage during normal switch operation, or the induction of minority carriers due to irradiation with light or radiation.
It becomes impossible to suppress the thyristor operation until the power supply is stopped. Based on this thyristor operation, an excessive current flows into the CMOS transistor, destroying the transistor.

The above-mentioned thyristor operation is caused by the shrinking of the gap between well 2 and PMOS as CMOS transistors become smaller, resulting in parasitic PNP bipolar transistors and parasitic NPN bipolar transistors.
The product of the current gain factors of each bipolar transistor is 1
It is known that this occurs due to the increase in size.

A method has been proposed to prevent thyristor operation by reducing the current gain factor product in each of the above parasitic bipolar transistors. That is, a CMOS in which the source 6 and drain 7 of the conventional structure PMOS shown in FIG. 1, which are formed by P+N junctions, are replaced with Schottky junctions.
The transistor structure was presented at the 1982 International Society of Electronics Engineers (
International-al, Electron D
evices Meeting) on page 462 of the proceedings. The above “Solution of CMOS latch-up phenomenon by Schottky barrier PMOS (CMOS la
tch-up clearance using
In the report entitled "Schottkybarrier PMOS", the current gain factor of a parasitic PNP bipolar transistor is compared to that of a conventional structure with a P+N junction, by taking advantage of the fact that the minority carrier injection efficiency in a Schottky junction is extremely small compared to that of a P+N junction. 1/ compared to things
By lowering the value to 100 or less, the latch-up phenomenon is solved.

Although the latch-up phenomenon can be prevented in the above CMOS transistor in which the source and drain junctions are formed using Schottky junctions instead of P+N junctions,
There are drawbacks specific to Schottky junctions. In other words, transistors using Schottky junctions have a large drain junction leakage current, non-linear output and no ohmic characteristics, and low transfer conductance, making it difficult to secure sufficient current and There are various drawbacks such as inability to operate.

The above-mentioned drawbacks based on the Schottky junction have been solved by the "Lightly doped Schottky transistor" which was proposed later.
kyMOSFET)” (1
(Refer to Proceedings of the International Society of Electronic Devices, 982, p. 466).

In other words, in the above-mentioned Schottky transistor, if a Schottky junction is formed on the drain region with a low impurity distribution, the leakage current of the drain junction can be reduced, and the transfer conductance is also lower than that of a PMOS with a normal structure.
can be approached to that of

However, the method of configuring a CMOS transistor using a structure combining a low impurity concentration drain diffusion layer and a Schottky junction also has the following drawbacks. That is,
The above document “CMOS latch-up climi
nation using schottky bar
NM
The current gain factor of a parasitic NPN bipolar transistor in the case where the source and drain junctions of the OS are formed by Schottky junctions is compared to the current gain factor of a parasitic NPN bipolar transistor in a conventional structure in which the drain junction is formed by an N+P junction. In other words, it becomes up to 10 times larger. Based on this, regardless of the presence or absence of a drain diffusion layer with a low impurity concentration, a CMOS transistor in which PMOS and NMOS are formed using a Schottky junction, the source and drain junctions of the PMOS are formed using a Schottky junction, Each NMOS junction has a drawback in that latch-up phenomenon is more likely to occur than a CMOS transistor formed by a normal N+P junction.

According to the above two documents regarding prevention of latch-up by Schottky junction, a PMOS in which a Schottky barrier is formed on each surface of the source region and drain region having a low impurity concentration distribution, and a source diffusion layer having a normal high impurity concentration , and an NMOS in which a drain diffusion layer is formed.
In combination with this, it is most desirable to configure a CMOS transistor from the viewpoint of latch-up prevention.

However, the conclusions obtained from the above two documents and their combination are valid only from the perspective of preventing latch-up of CMOS transistors, and are applicable only to CMOS transistors.
NMOS and PMO due to miniaturization of S transistors
No solution has been proposed for the above-mentioned drawback regarding the decrease in breakdown voltage of S.

In particular, the two above-mentioned documents do not mention anything about ultra-fine CMOS transistors with a channel length of 0.5 μm or less, and are completely powerless against the above-mentioned drawbacks.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a CMOS transistor which can eliminate the above-mentioned conventional drawbacks, operate at a normal power supply voltage even with an extremely short channel length, and prevent latch-up phenomena.

[Summary of the invention]

In order to achieve the above object, the complementary insulated gate field effect transistor of the present invention has an N-type drain region with an impurity diffusion region having a maximum impurity concentration of about 1018 to 1020 cm-3, and an N-type drain region with a maximum impurity concentration of about 1017 to 1019 cm.
It is characterized in that it has a P-type drain region of about -3, and that at least a part of each of the drain regions is connected to a high melting point metal or a silicide layer of the metal.

[Embodiments of the invention]

The present invention is based on the results of an analysis of the high impurity concentration region in the drain diffusion layer, going back to its physical roots without being bound by conventional wisdom, that is,
In transistors having various drain diffusion layer concentrations, when a silicide layer of a refractory metal is formed on the surface of the drain diffusion layer, the drain diffusion layer is formed with N conductivity type impurities such as phosphorus (P) and elemental (As). There is a phenomenon in which the impurity concentration on the surface of the drain diffusion layer becomes high at a depth of about 10 nm only when That is, in NMOS, the surface impurity concentration of the drain diffusion layer is 1×10c.
It has been found that when the thickness is m-3 or more, good ohmic characteristics can be obtained between the silicide layer and the semiconductor surface, and no problems arise in the characteristics as an NMOS.

A drain diffusion layer in a typical transistor has a high impurity concentration region of 1020 cm -3 or more near the surface of a semiconductor substrate, and has an impurity concentration distribution that attenuates in a Gaussian distribution or an error function distribution toward the inside of the substrate. When a voltage is applied to the above normal drain diffusion layer and the applied electric field is analyzed as a function of the depth, that is, the impurity concentration, it is 1020 cm.
It has been found that only an extremely weak electric field is applied in a high impurity concentration region of −3 or higher. This fact shows that the presence of high impurity concentrations is rather harmful from the viewpoint of increasing the breakdown voltage of ultra-fine transistors, and it is clear that it is desirable for the maximum impurity concentration of the drain diffusion layer to be 1019 cm-3 or less. did. The role of the above-mentioned high impurity concentration region of 1020 cm-3 or more in the transistor is to reduce the diffusion layer resistance and ensure good ohmic contact with the wiring metal. The ohmic contact can be replaced by a structure of a drain diffusion layer having a surface impurity concentration of 1×10 18 cm −3 or more and a silicide layer on the diffusion layer. It is known that the former role mentioned above, that is, reduction of source and drain diffusion resistances, can be achieved by silicidation of the surfaces of the source and drain diffusion layers. In formation, silicidation has a remarkable effect of reducing resistance.

Therefore, the CMOS transistor of the present invention develops the concept based on the above analysis results, and replaces the high impurity concentration region of the drain diffusion layer with a thin silicide layer connected to the drain diffusion layer through ohmic contact. This method utilizes the results of analytically determining the optimal conditions regarding impurity concentration. The above-mentioned optimal conditions are particularly aimed at increasing the breakdown voltage of ultra-fine transistors with gate lengths of 0.5 μm or less,
and optimal conditions regarding latch-up prevention.

FIGS. 2 and 3 are diagrams showing the analysis results according to the present invention, respectively, and represent curves of the source-drain breakdown voltage and the maximum substrate current as a function of the surface impurity concentration of the drain diffusion layer.

In FIG. 2, as the source-drain breakdown voltage, the avalanche breakdown voltage is shown by a dotted line, and the punch-through breakdown voltage is shown by a solid line. Each breakdown voltage is determined as a function of channel length.

In FIG. 2, the avalanche voltage is related to PMOS, and the NMOS values generally tend to be 0.5-1 (V) lower than the illustrated curve. Regarding the punch-through breakdown voltage, no difference is seen between the respective values of PMOS and NMOS.

A newly clarified fact from Figure 2 is that in a transistor with a channel length of 0.5 μm or more, if the surface impurity concentration of the drain diffusion layer is set to 3 × 1018 cm-3, a transistor with the same size of normal structure It is possible to realize a breakdown voltage of 10 V or more, which is approximately twice the source/drain breakdown voltage of the transistor. Also, the channel length is 0
．． In transistors with a length of 4 μm or less, there is an optimum drain diffusion layer surface impurity concentration depending on the channel length, and in a transistor with a channel length of 0.3 μm, the drain diffusion layer surface impurity concentration is approximately 1×1013c.
If it is set to m-3, the source/drain breakdown voltage can be improved to about 7V. In a PMOS transistor with a channel length of 0.2 μm, the channel length is 5×1017 cm−
If the drain surface impurity concentration is set to 3, a breakdown voltage of about 5V will be obtained.

Next, in Fig. 3, the substrate current, in which minority carriers induced by the drain current flow toward the substrate, is calculated as a function of the gate voltage, and the maximum value, that is, the maximum substrate current, is determined by the impurity concentration on the surface of the drain diffusion layer. It is analyzed as a function of .

In Figure 3, the channel length is 1.0μm and the channel width is 10μm.
Regarding the transistor No. m, the junction depth of the source and drain diffusion layers is used as a parameter, and the drain voltage is 5V.

A newly revealed fact from Figure 3 is that although it depends somewhat on the drain junction depth, the surface concentration of the drain diffusion layer can be reduced by 10
If it is set to 17 to 1018 cm-3, the substrate current can be improved by an order of magnitude compared to that of a normal structure.
This can be expected to prevent latch-up phenomena.

If a silicide layer is formed on the drain diffusion layer with the optimum surface impurity concentration for latch-up resistance, ohmic contact cannot be obtained and a Schottky barrier is formed.

In the present invention, based on the new analysis results obtained from FIGS. 2 and 3 and the two references mentioned above, we have created an ultra-fine CM with unprecedented high voltage resistance and latch-up resistance.
Realized an OS transistor.

That is, in the CMOS transistor of the present invention,
The PMOS is formed with a Schottky barrier drain junction based on the above two documents, while the NMOS is formed with a 1018 Schottky barrier based on the new analysis results obtained from Fig. 2.
A drain junction is formed by combining a diffusion layer with a surface impurity concentration of cm-3 or higher and a silicide layer with ohmic contact.

This not only improves latch-up resistance but also improves PMO
It becomes possible to further optimize the surface impurity concentration of each source/drain diffusion layer of S and NMOS from the viewpoint of increasing the breakdown voltage of an ultrafine CMOS transistor of 0.5 μm or less.

FIG. 4, FIG. 5, and FIG. 6 respectively show the first embodiment of the present invention.
FIG. 3 is a cross-sectional structural diagram of the manufacturing process of a CMOS transistor showing an example of the invention.

In Figures 4 to 6, 1 is n conductivity type specific resistance 0.4Ω
A P conductivity type well 2 having a junction depth of 2 μm and a surface impurity concentration of 1×10 16 cm −3 is formed at a predetermined position on this substrate 1 using a known boron diffusion method. Next, using known element isolation technology, 0.5
After selectively forming a μm thick field oxide film 3,
A clean gate oxide film 8 having a thickness of 20 nm is formed by exposing the semiconductor surface of the active region. After that, about 0.4
A silicon thin film with a thickness of μm is formed on the gate oxide film 8, and P
A high concentration of phosphorus is diffused into the silicon thin film by thermal diffusion using OCl3 as a diffusion source. Next, the surface of the silicon thin film is thermally oxidized to form a 0.2 μm thick silicon oxide film on the silicon thin film. Thereafter, the silicon oxide film and the silicon thin film are simultaneously etched according to a desired circuit configuration by photolithography, and the gate protection insulating film 12 and
and gate electrode 9 are left respectively. The width of the gate electrode 9 after photoetching, that is, the channel width, is 1.0, 0.5, 0.3, 0.2, and 0.1.
It was conducted under 5 conditions of μm.

After the above photoetching, tetraethoxysilane (Si(OC)
0.3μm by chemical vapor phase reaction using 2H5)4)
A silicon oxide film having a thickness of .

When the deposited film is etched in a direction perpendicular to the semiconductor substrate surface by reactive sputter etching and the silicon oxide deposited film deposited on the flat portion is removed, only the sidewall portions of the gate electrode 9 and the field oxide film 3 are etched. A silicon oxide deposited film 13 is left behind. Next, a 0.8 μm thick photoresist film is applied to the gate oxide film 8 in the area excluding the well 2.
Arsenic ions are left on top and arsenic ions are implanted under the condition of acceleration energy of 70 KeV. The above ion implantation is performed into the well region 2 through the gate oxide film 8 under conditions such that the maximum impurity concentration is achieved at the surface of the semiconductor substrate. On the other hand, the implanted ions are blocked in areas other than the well region 2 by the photoresist film, and are not implanted into the semiconductor substrate 1. After the above ion implantation, the remaining photoresist film is removed, and the implanted ions are activated.
A heat treatment is performed to form a source 4 and a drain 5 of N conductivity type (see FIG. 4).

The surface impurity concentration of each of the source/drain diffusion layers 4 and 5 is 3×10 18 cm −3 when the channel length is 0.5 μm or more, and 1 when the channel length is 0.3 μm or less.
The amount of arsenic ions is set so that the size of the arsenic ion is finally formed at x1018 cm-3. Further, the above heat treatment conditions are controlled so that the junction depth of the above source 4 and drain diffusion layer 5 is finally 0.25 μm. After the above heat treatment, only the well 2 region is covered with a 0.8 μm thick photoresist film, and boron ions are implanted at an acceleration energy of 70 KcV. By the above ion implantation, well 2
Boron was implanted into the semiconductor substrate 1 through the gate oxide film 8 in other regions, and the maximum impurity concentration was at the surface of the semiconductor substrate 1. In the well region 2, ion implantation is blocked by the photoresist film and is not implanted into the semiconductor substrate 1. After the above ion implantation, the remaining photoresist film is removed, and then the implanted boron ions are activated by heat treatment to form the P conductivity type source 6 and drain 7 (see FIG. 5). . The surface impurity concentration of each of the source 6 and drain 7 diffusion layers was finally determined under three conditions: 3×1017
The amount of boron to be implanted is set to be 1×10 18 cm −3 and 3×10 18 cm −3 . Also, source 6,
And the junction depth of the drain 7 diffusion layer is finally 0.2
The above heat treatment conditions are controlled so that the thickness becomes 5 μm. After the above heat treatment, the gate oxide film exposed on the semiconductor substrate 1 is removed, and then platinum (platinum) having a film thickness of 50 nm (
Pt) was deposited on the entire surface by sputtering, and then 450
Heat treatment at ℃. source diffusion layer regions 4 and 6 in which the surface of the semiconductor substrate 1 is exposed due to the above-described low-temperature heat treatment;
A platinum silicide (PtSi) layer 14 is formed on each surface of drain diffusion layer regions 5 and 7 in a self-aligned manner.

In the above heat treatment, platinum (Pt
) does not react, so the silicide layer 14 is not formed. After the above low-temperature heat treatment, platinum (Pt) is completely coated with aqua regia.
etching. Platinum silicide (PtSi) is not removed by aqua regia and remains only on source diffusion layers 4 and 6 and drain diffusion layers 5 and 7 in a self-aligned manner.

At this point, the concentration of impurities immediately below the platinum silicide (PtSi) layer 14 in the source 4 and drain 5 regions of the N conductivity type is lower than the surface impurity concentration before the formation of the platinum silicide layer.
A precipitated layer about 10 mm thick with an order of magnitude higher impurity concentration is formed in a self-aligned manner with respect to the platinum silicide (PtSi) layer 14. After forming the platinum silicide layer 14, monosilane (
Approximately 50
A silicon oxide film 10 with a thickness of 0 nm is deposited over the entire surface, and portions of the silicon oxide film 10 that will form contact holes on the sources 4 and 6, the drains 5 and 7, and on the gate electrode 9 are selectively etched by photolithography. to be removed. After the selective removal of the silicon oxide film 10 described above, the titanium (Ti)
) and tungsten (W) are simultaneously sputtered to deposit a TiW film 15 on the entire surface. Thereafter, the photoresist film is removed, but since the TiW film on the photoresist film is also removed at the same time in this step, the TiW film 15 is selectively left only in the area where the silicon oxide film 10 has been removed. Ru. Finally, wiring 11 made of aluminum (Al) is formed according to the desired circuit configuration (the sixth
(see figure).

Note that the TiW film 15 is necessary to prevent reaction between the aluminum wiring 11 and the silicide layer 14.

Next, regarding the CMOS transistor manufactured by the above manufacturing process, the withstand voltage between the source and drain was first measured, and the following results were obtained. In other words, a PMOS in which the surface impurity concentration in the source 6 and drain 7 diffusion layers of P conductivity type is set to 3 x 1017 cm-3 exhibits Schottky characteristics, but the channel length is 0.2 μ.
It was possible to obtain a breakdown voltage of about 5V for the transistor with a voltage of m or more. This value is more than twice the breakdown voltage of a transistor with a conventional structure in which the P conductivity type drain surface impurity concentration is 10<16>cm<-3> or more. P conductivity type drain surface impurity concentration set to 1 x 1018 cm-3
MOS exhibits transistor characteristics based on a P+N contact, and its source-drain breakdown voltage is 6.5 to 7 V in a transistor with a channel length of 0.3 μm or more. This value is 1.6 compared to the previous value.
This shows that high voltage resistance has been achieved. Furthermore, even in a PMOS in which the P conductivity type drain surface impurity concentration is set to 3 x 1018 cm-8,
Although the transistor characteristics are based on a P+N junction, the breakdown voltage between the source and drain was approximately 12V in a transistor with a channel length of 0.5 μm or more. This value is more than 2V higher than the conventional value, which means that a high breakdown voltage has been achieved.

In an NMOS in which the surface impurity concentration in the N conductivity type source 4 and drain 5 diffusion layers is set to 3×10 18 , a transistor with a channel length of 0.5 μm or more has a source-drain breakdown voltage of approximately 10 V. Ta. This value is approximately twice the previous value,
This means that the voltage resistance has been increased.

Even in the NMOS in which the drain surface impurity concentration was set to 1×10 18 cm −3 , good ohmic characteristics were ensured between the source 4 and drain 5 and the silicide layer 14, and transistor characteristics based on a P+N junction were obtained. The source-drain breakdown voltage depends on the channel length, and is approximately 6V for a transistor with a channel length of 0.3 μm.
, it was about 3V for a 0.2 μm transistor. These values are more than twice as high as the source-drain breakdown voltage of an NMOS having a conventional structure.

NM in CMOS transistor based on this example
The source-drain breakdown voltages of the OS and PMOS agree very well with the analysis results shown in FIG. 2, proving the validity of the above analysis. That is, according to this embodiment, the source-drain breakdown voltage of an ultra-fine CMOS transistor having a channel length of 0.5 μm or less is
This can be improved by more than twice compared to the conventional method. Specifically, in a CMOS transistor with a channel length of 0.5 μm or more, the surface impurity concentration of each source/drain diffusion layer of NMOS and PMOS is set to 3×1018c.
m-3, when the channel length is 0.3 μm, the above impurity temperature is set to 1×10 cm-3, and the transistor is set based on this example. A CMOS transistor can be obtained. Moreover, when the channel length is 0.2 μm,
If the surface impurity concentration of the PMOS source/drain diffusion layer is set to 3 x 1017 cm-3, and the surface impurity concentration of the NMOS is set to 1 x 1018 cm-3, and a transistor is completed based on this example, the source - An ultra-fine CMOS transistor with a drain-to-drain breakdown voltage of 3V can be obtained. In the above transistor, PMOS
Although a Schottky barrier is formed between the source 6 and drain 7 and the silicide layer 14, this does not pose a problem in terms of characteristics. Rather, this Schottky barrier has the function of improving latch-up resistance.

Next, the CM manufactured by the manufacturing process shown in this example
The latch-up resistance characteristics of OS transistors will be evaluated. The latch-up resistance characteristics are measured as follows. That is, a parasitic NP with the drain 5 of the NMOS as the emitter, the well 2 as the base, and the semiconductor substrate 1 as the collector.
The product βN·βP of the current gain factor βN of the N transistor and the current gain factor βP of the parasitic PNP transistor having the source 6 of the PMOS as the emitter, the semiconductor substrate 1 as the base, and the well 2 as the collector was measured. In this measurement, a voltage of 5V is applied between the base and collector, and a voltage of 10-6 to 10-
βN·βP was determined as a function of emitter current in the range of 2A.

As a result, the impurity concentration on each drain surface of PMOS and NMOS was 3 × 1018 cm-3, and the channel length was 0.5
μm CMOS transistor, each drain surface impurity concentration is 1×1018 cm-3, channel length is 0.5 μm
m CMOS transistor, the above drain surface impurity concentration is 1 x 1018 cm-3, and the channel length is 0.3 μ.
Each βN· in a CMOS transistor with m and a PMOS drain surface impurity concentration of 3×1017 cm−3, an NMOS drain surface impurity concentration of 1×1018 cm−3, and a channel length of 0.2 μm.
The maximum value of βP product was 10-2 to 10-4 in all cases. The above value is the condition β under which latch-up can occur.
The value of the βN·βP product in a CMOS transistor that does not satisfy N·βP>1 and in which the PMOS drain is a Schottky junction and the NMOS drain is a normal high impurity concentration N+P junction is approximately 10-2. The value is the same or lower. From the above results, in a CMOS transistor in which the PMOS drain diffusion layer is set to a low impurity concentration, N
This means that the optimum condition for the impurity concentration on the drain surface of the MOS can be set depending on the desired channel length.

Next, in the CMOS transistor according to this example,
CMOS transistors with a channel length of 0.2 to 1.0 μm with NMOS and PMOS drain surface impurity concentrations set to 5 x 1018 to 1020 cm-3 were also manufactured at the same time, and their source-drain breakdown voltage and latch-up resistance characteristics were measured. did. Although the source-drain breakdown voltage of the CMOS transistor was improved by up to several volts over the conventional value, and the βN·βP product was less than 1, the characteristics were slightly inferior compared to the results described above.

7 and 8 show a second embodiment of the present invention.
FIG. 3 is a cross-sectional structural diagram of a manufacturing process of a MOS transistor.

In the first embodiment shown in FIG. 4, the silicon oxide deposited film 13 is left only on the sidewalls of the gate electrode 9 and the field oxide film 3 in a self-aligned manner, and then the exposed gate oxide film is removed. Remove completely. Next, a chemical vapor phase reaction between dichlorosilane (SiH2Cl2) and hydrochloric acid (Hcl) is performed at a temperature of 775°C, and a polycrystalline or amorphous silicon thin film 16 with a thickness of 0.3 μm is formed on the surface of the well 2. and is selectively deposited on the surface of the semiconductor substrate 1 which maintains N conductivity type (see FIG. 7). The conditions for forming the silicon deposited film were as follows: 200 cc of dichlorosilane, 6 cc of hydrochloric acid.
Under the condition of 0 cc, the deposition rate is 10 nm/min. Under these conditions, a silicon nitride film (Si3
N4) is selectively deposited only on the silicon substrate, and also at the boundary with the sidewall insulating film 13.
A flat shape without unevenness called facets can be obtained.

After the deposition of the silicon thin film 16, a photoresist film is selectively formed and boron ion implantation is performed so that the ion implantation is performed only on the silicon thin film portion over the well 2 region. The amount of boron implanted is
The impurity concentration in the well 2 is set to match the impurity concentration on the surface of the well 2.

The implant energy is 25 KeV. After that, the photoresist film used as a mask for ion implantation is removed, and then a high temperature short time heat treatment is performed at 1150° C. for 15 seconds to activate the implanted ions and make the silicon thin film 16 into a single crystal. . The impurity diffusion coefficient in the polycrystalline or non-quality silicon thin film 16 is as follows:
The diffusion coefficient is 10 to 20 times larger than the diffusion coefficient in single crystal silicon.

Therefore, the boron implanted into the silicon thin film 16 on the well 2 by the above-described one-time heat treatment is distributed almost uniformly in the depth direction within the silicon thin film 16. After the heat treatment, N conductivity type source 4 and drain 5 and P conductivity type source 6 and drain 7 are formed according to the first embodiment described above. The silicon thin film 16 has already been made into a single crystal by the above-described short-time high-temperature heat treatment. Therefore, the formation conditions for each source and drain above are as follows:
This is carried out under the same conditions as in the first embodiment.

The subsequent steps are also carried out by CM in accordance with the first embodiment described above.
An OS transistor is manufactured (see FIG. 8 above).

The CMOS transistor based on the second embodiment shown in FIG. 8 has the same dimensions as the CMOS transistor based on the first embodiment described above, and when comparing the source-drain breakdown voltage of the two, it was found that the channel length x 1018 cm -3
, source and drain surface impurity concentration 1×1018c
The CMOS transistor of the second example under the condition of m-3 had a breakdown voltage of 7V, which was higher by about 1V. In addition, the channel length is 0.2 μm, and the impurity concentration on the back side of the drains of NMOS and PMOS is 1×1018 cm−3, respectively.
The breakdown voltage of the CMOS transistor of the second embodiment configured under the conditions of Got the value. The above values are based on the source and
This means that the breakdown voltage is more than three times higher than the drain-to-drain breakdown voltage.

In the CMOS transistor based on the second embodiment, the current gain factor product βN and βP for the parasitic bipolar transistor was measured for various channel lengths and source/drain surface impurity concentrations, but none of the It was reduced to 2/3 to 1/2 compared to the measured value of the CMOS transistor based on the first embodiment described above. In this way, the CMOS based on the second embodiment
The transistor has improved source-drain breakdown voltage and latch-up resistance compared to the CMOS transistor based on the first embodiment, because the source and drain junctions are disposed within the semiconductor thin film 16. This is thought to be due to a decrease in the junction area and an increase in the effective channel length.

9 and 10 are a cross-sectional structural diagram of a CMOS transistor showing a third embodiment of the present invention, and a diagram of impurity concentration distribution in the depth direction in an N-based drain diffusion region.

In the second embodiment shown in FIG. 7, after a polycrystalline or amorphous silicon thin film 16 is deposited on the semiconductor substrate 1 in a self-aligned manner, ions are formed only in the silicon thin film portion over the well region 2. A photoresist film is left on the surface of the other areas for implantation. Thereafter, arsenic ions are implanted into the silicon thin film portion above the well region 2, and then the remaining photoresist film is removed.

Next, the well region 2 is covered with a photoresist film, and ions are implanted only into the silicon thin film portion on the semiconductor substrate 1 having N conductivity type other than the well region 2.
The photoresist film is left again. Thereafter, boron ions are implanted, and the photoresist film is completely removed again to expose the surface of the silicon thin film 16. In this state, a single-hour high-temperature heat treatment is performed at 1100° C. for 30 seconds. Even when heat treatment is performed under the above conditions, the silicon thin film 16 is not made into a single crystal, but maintains a polycrystalline or amorphous state. Since the diffusion coefficient of impurities in the polycrystalline or amorphous silicon thin film 16 is extremely large as described above, arsenic and boron are removed in the silicon thin film 16 by a single-hour heat treatment under the above conditions. A nearly uniform concentration distribution is achieved at high speed. However, the diffusion coefficient of each impurity in the semiconductor substrate 1 is relatively small, and the impurities were only diffused into the semiconductor substrate 1 by about 20 nm by the above-mentioned short-time heat treatment.

In this way, by ion implantation of arsenic and boron followed by short-time heat treatment, N conductivity type source 4 and drain 5, and P conductivity type source 4 and drain 5 are formed in the silicon thin film 16, well 2, and N conductivity type semiconductor substrate 1, respectively. A source 6 and a drain 7 are formed. After that, each of the above sources 4 and 6
and platinum silicide (PtSi) on drains 5 and 7.
The CMOS transistor shown in FIG. 9 can be manufactured by forming the layer 14 in a self-aligned manner according to the first embodiment described above and performing the subsequent steps according to the first embodiment.

The impurity concentration distribution of the N conductivity type source 4 and drain 5 of the CMOS transistor according to the third embodiment is as shown in FIG. B. It is separated into C. That is, an approximately 10 nm thick impurity precipitation region A immediately below the silicide layer 14 A uniform distribution region B inside the silicon thin film 16
, and a steep concentration distribution region C having a junction depth of about 20 nm in the well 2. In the P conductivity type source 6 and drain 7, the presence of the impurity precipitation region A was not observed.

In the CMOS transistor based on the third embodiment, the uniformly distributed concentration in the silicon thin film 16 is NM
For OS: 1 x 1018cm-3, 3 x 1018c
m-3, 1019 cm-3, 5 x 1019 cm-3, and for PMOS, 1 x 1017 cm-3,
3 x 1017 cm-3, 1 x 1018 cm-3, 3 x 1
For each value of 018 cm-3 and 5 × 1018 cm-3,
The transistors were fabricated by setting the arsenic or boron ion implant dosage to be final. Also, regarding the channel length, 0.1, 0.2, 0.3,
Transistors were fabricated for each case of 0.5 and 10 μm. Regarding the various CMOS transistors mentioned above, the source-drain breakdown voltage and parasitic bipolar
The product βN·βP of each current gain factor of the transistor was measured. The uniformly distributed impurity concentration in the NMOS drain 7 is 10
In the case of 19 cm<-3> or more, the above-mentioned improvement in characteristics was not observed much. However, the above uniformly distributed impurity concentration is 101
When the impurity concentration was set at a low impurity concentration of 7 to 1019 cm-3, the improvement in the source-drain breakdown voltage was particularly remarkable. Uniformly distributed impurity concentration in the drain is 1×10
For 18 cm, the channel length is 0.1 and 0.2
The source-drain voltage in each μm CMOS transistor reached 4.5 and 8 V, respectively. Although these values are significantly improved compared to the CMOS transistor based on the second embodiment, this effect was relatively more pronounced when the channel length was short. P
The uniformly distributed impurity concentration in the drain 5 of the MOS is 1
Even when the gate length is set to less than 017 to 1018 cm-3 and the gate length is 0.1 μm, the source-drain breakdown voltage is improved by several volts compared to the second embodiment, and the value is 5V. The above has been reached.

The difference in this effect between the third embodiment and the second embodiment is that the low impurity concentration region where the maximum drain electric field is applied is
In the case of the third embodiment, as shown in FIG. 10, it is formed almost uniformly within the silicon thin film 16, and it is thought that this makes the electric field dispersion effect more pronounced.

The impurity concentration distribution shown in FIG.
This structure is unique to cases where the crystalline structure is formed of polycrystalline or amorphous material, and it is thought that this structure is extremely effective in improving the source-drain breakdown voltage of ultra-fine CMOS transistors.

Further, regarding the parasitic bipolar transistor product βN and βP of the ultra-fine CMOS transistor based on the third embodiment, there was almost no difference from that of the second embodiment, and the latch-up phenomenon was negligible.

Although the first to third embodiments have been described above, the effects obtained by these are obtained by improving the regions corresponding to the source and drain in the conventional structure, and are not achieved by increasing the concentration of the semiconductor substrate 1 to achieve high breakdown voltage. It is not a measure of change.

Therefore, a decrease in mobility due to an increase in semiconductor substrate concentration is not caused, and high-speed operation is not impaired.

In the present invention, since a high melting point metal or its silicide layer is formed on the source and drain, ultrafine CMOS
Transistors can also maintain a low sheet resistance of several Ω/hole, ensuring high-speed operation.

In each of the first to third examples, the maximum impurity concentration of the source and drain diffusion layers is 1 x 1017 cm-
Although the case of 3 or more has been described, this is based on the analysis results shown in FIG. 2, that is, the analysis results for a gate length of 0.1 μm. A value of 0.1 μm is the minimum gate length that can be achieved. In addition, the above impurity concentration (1×101
7 cm-3) or less, and when the present invention is applied, the third
As can be inferred from the figure, this results in an increase in substrate current and drain leakage current.

Further, in each of the first to third embodiments, a platinum silicide (Pt.Si) layer was formed on the source/drain diffusion layer in a self-aligned manner, but this is just an example.
t. Mo. instead of Si layer. W. Pd. N. Ti. Ta
．． Nb. Cr. A high melting point metal such as Pr or its silicide film can be used. Further, in each of the examples, a method using a high-temperature electric furnace was described as the short-time heat treatment, but this step can also be performed by other methods such as a lamp heating method, laser or electron beam irradiation method. Furthermore, in each embodiment, the case where a P-conductivity type well is used has been described, but conversely, the present invention can also be applied to a CMOS transistor having a structure in which an N-conductivity type well is formed in a P-conductivity type semiconductor substrate. Can be applied.

〔Effect of the invention〕

As explained above, according to the present invention, even with an extremely short channel length of 0.2 μm, it can be operated with a normal power supply of 5V and the latch-up phenomenon can be prevented, so that high-speed operation is not impaired. It is possible to realize ultra-fine CMOS transistors.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional structure diagram of a conventional CMOS transistor, Figs. 2 and 3 are for explaining the principle of the present invention, and Fig. 4 is a diagram showing analysis results regarding source-drain breakdown voltage and maximum substrate current. , FIG. 5 and FIG. 6 are cross-sectional views of the manufacturing process of a CMOS transistor showing the first embodiment of the present invention, and FIGS. 7 and 8 are cross-sectional views of the manufacturing process of a CMOS transistor showing the second embodiment of the invention. 9 and 10 are cross-sectional views of a CMOS transistor showing a third embodiment of the present invention, and diagrams showing the impurity concentration distribution in the depth direction. 1: Silicon substrate, 2: Well region, 3: Feed oxide film, 8: Gate oxide film, 9: Gate electrode 12: Gate protection insulating film, 13: Silicon oxide deposited film, 4.6: Source, 5.7: Drain, 14: Platinum silicide layer, 10
: Silicon oxide film, 15: TiW film, 11: Aluminum wiring, Patent applicant Hitachi, Ltd. Figure 1 Figure 5 UA Figure 2 Surface impurity concentration of drain diffusion layer (Cm-3) Figure 3
Figure 6: Surface roughness of drain diffusion layer (Cm-3°) Figure 6 Figure 7 Figure 8

Claims (4)

[Claims] (1) The impurity diffusion region has an N-type drain region whose maximum impurity concentration is about 1018 to 1020 cm-3 and a P-type drain region whose maximum impurity concentration is about 1017 to 1019 cm-3, and at least one of the above drain regions 1. A complementary insulated gate field effect transistor, characterized in that a portion is connected to a high melting point metal or a silicide layer of the metal. (2) A part of each of the drain regions is formed adjacent to a gate electrode formed on the surface of the semiconductor substrate with an insulating film interposed therebetween, and an insulating film formed on the side wall of the gate electrode. A complementary insulated gate field effect transistor according to claim 1, characterized in that: (3) The N-type drain region perpendicularly connects three impurity concentration distribution regions: the impurity precipitation region directly under the high melting point metal or its silicide layer, the almost uniform distribution region inside the silicon thin film, and the rapid acid concentration distribution region. 3. A complementary insulated gate field effect transistor according to claim 1 or 2, characterized in that the complementary insulated gate field effect transistor has a conductive structure in the direction shown in FIG. (4) A complementary insulated gate field effect according to claim 2 or 3, wherein a portion of each drain region is formed of a polycrystalline thin film or an amorphous thin film. transistor.