JP3122435B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device (hereinafter, referred to as BiMOS) in which a bipolar transistor and a MOS transistor are mixed.

[0002]

2. Description of the Related Art BiMOS technology is a high-speed and high-speed technology in which a logic gate combining a bipolar transistor capable of high-speed operation and a MOS transistor capable of high integration and low power consumption is formed on the same chip. This is a technology for realizing low power consumption LSI.

In manufacturing such a conventional BiMOS LSI, the gate electrodes of the NMOS and PMOS transistors are formed using the same N-type polysilicon. In addition, NPN is mainly used for the bipolar transistor, and its external base electrode cannot be formed of the same material as the gate electrode of the MOS transistor. Therefore, the gate electrode must be formed first, or the external base electrode must be formed first. Either of the two methods has been used.

[0004]

As described above, in the conventional manufacturing of a semiconductor device, the gate electrode of the NMOS and the gate electrode of the PMOS transistor are formed of the same N-type material. There was a problem that it was easily affected by the channel effect.

Also, an NMOS transistor and a PMOS
Since the gate electrode of the transistor is made of an N-type material and the external base electrode of the NPN bipolar transistor is made of a P-type material, these cannot be formed in one step, resulting in an increase in the number of steps.

The present invention has been made in view of such a problem, and an object of the present invention is to form an N-type gate electrode for an NMOS transistor and a P-type gate electrode for a PMOS transistor to form a short circuit. Make it less susceptible to channel effects and reduce the number of steps,
It is to provide a fine and high-performance semiconductor device.

[0007]

In order to achieve the above object, a semiconductor device according to a first aspect of the present invention provides a semiconductor device having a first voltage.
A PMOS transistor with an applied drain;
The gate connected to the gate of the PMOS transistor
NMOS transistor and PMOS transistor
A base connected to the source of the
NPN bipolar transistor with added collector
Connected to the source of the NMOS transistor.
Base, drain and front of the NMOS transistor
Connected to the emitter of the NPN bipolar transistor.
Emitter having a collector to which a second voltage is applied
A semiconductor device having a PNP bipolar transistor;
The gate electrode of the NMOS transistor is N-type
The gate electrode of the PMOS transistor is P-type.
You.

[0008]

[0009]

[0010]

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a BiMOS element using a semiconductor device of the present invention will be described with reference to the drawings.

1 (a) to 1 (e) and 2 (a) to 2 (a).
(C) is a sectional view showing a step of forming a BiMOS device according to one embodiment of the present invention.

First, in the step shown in FIG.
Semiconductor substrate 10 having a (100) crystal plane in a mold
An insulating film 11 is deposited thereon. Next, the buried collector region and the PMO are removed from the insulating film 11 by photolithography.
The portion to be the S element is removed, and the opening 12 is formed. Further, an N ⁺ -type buried collector layer (a layer that deepens the N well) 13 is formed by diffusing antimony (Sb) in a gas phase or a solid phase or by implanting arsenic (As) or Sb from the opening 12. It is formed in the substrate 10.

Next, in a step shown in FIG. 1B, the insulating film 11 is entirely removed, and boron (B) is supplied to the substrate 10 at an acceleration energy of 100 keV and a dose of 6 × 10 ¹² cm ^2.
Is ion-implanted over the entire surface of the substrate. As a result, a first low-concentration buried P-type region 9 for preventing punch-through is formed. Before forming the buried P-type region 9, 50
By forming the above oxide film on the entire surface of the substrate 10, contamination during ion implantation can be prevented. 850 ° C
By performing the above heat treatment, it is possible to recover damage to the substrate 10 due to the ion implantation and activate the implanted impurities.

Further, the first buried P-type region 9
, In this embodiment is injected into the whole surface, which may be selectively implanted, and as will be described later in the step of FIG. 1 (d), the leaking impurities from the N ⁺ -type region 13 In consideration of the above, the second high concentration buried P-type region 8
Can be implanted so as to be separated from the buried N ⁺ type region 13 by 2 μm or more.

Next, by epitaxial growth method,
1 × 10 phosphorus (P) as pure ¹⁶/ Cm^ThreeIncluding degree
An N-type epitaxial layer 14 is formed on the substrate 10.
The growth temperature at this time is, for example, 1130 ° C.
The thickness of the epitaxial layer 14 is 1.2 μm.
You.

Next, in the step shown in FIG. 1C, first, a mask (not shown) for ion implantation is formed by photolithography. Using this mask, P ions are implanted into the PMOS formation region of the N-type epitaxial layer 14 and the NPN bipolar element formation region at an acceleration energy of 160 keV and a dose of 5 × 10 ¹² / cm ² , and N-type Well region 15 is selectively formed. Then, using another mask, the NMOS element formation region and the PNP
100 ke in the bipolar transistor element formation region
B ions are implanted at an acceleration energy of V and a dose of 6 × 10 ¹² / cm ² to selectively form the P-type well region 16. N-type well region 15 and P-type well region 16
Will be substantially the same. The P-type well region 1
6 may be formed first, and then the N-type well region 15 may be formed.

Further, in the step shown in FIG.
A field oxide film 17 for separating the MOS transistors and the MOS transistor and the bipolar transistor is formed by a selective oxidation method. The thickness of field oxide film 17 is about 6000 °. Prior to formation of the field oxide film 17, an ion implantation region 18 for preventing field inversion is formed in a self-aligned manner. After the field oxide film 17 is formed,
B ions have an acceleration energy of 1 MeV and 1 × 10 ¹⁵ / c
At a dose of m ² , ions are selectively implanted into the region 8 where the PNP transistor is formed.

Subsequently, the thickness is set to 150 ° by a thermal oxidation method.
About a dummy gate oxide film 19 is formed on the entire surface. This
Thereafter, through the dummy gate oxide film 19, the PMOS
Transistor and NMOS transistor threshold matching
Ion implantation area for protection and punch-through prevention
20 and 21 are the N-type well region 15 and the P-type well region
It is formed on each of the 16 surfaces. The N-type well region
The channel ion implantation region 20 on the side of the 15
0 keV acceleration energy and 3 × 10¹²/ Cm ^TwoDo
And P ions are applied at 240 keV.
Fast energy and 2 × 10¹²/ Cm^TwoIon at a dose of
It is formed by injection.

The channel ion implantation region 21 on the side of the P-type well region 16 is formed by implanting B ions at an acceleration energy of 20 keV and a dose of 4 × 10 ¹² / cm ² .

Further, at this time, the NPN bipolar transistor
20 ke is formed in the region (shallow base) 52 for forming a resistor.
V acceleration energy and 1 × 10¹³/ Cm^TwoWith a dose of
BF _TwoWhile selectively ion-implanting
30 keV is applied to the polar formation region (shallow base) 51.
Acceleration energy and 1 × 10¹³/ Cm^TwoAs dose at the dose of
And the internal base by selective ion implantation
Reduce the resistance between the external base electrode outlets. This ion
The implantation may be performed after forming a gate oxide film described later.
No.

Further, P ions are applied to the N-type epitaxial layer 14 at an acceleration energy of 320 keV and 1 × 10 ^16.
/ Cm ² by ion implantation to form a deep (De) connected to the buried collector layer 13.
ep) N ⁺ type ion implantation region 22 is formed. Furthermore, B ions are accelerated at an acceleration energy of 320 keV and 1 × 1.
By implanting ions at a dose of 0 ¹⁶ / cm ² , a deep P ⁺ -type region 53 for extracting a collector electrode is formed in a part of a region where a PNP transistor is formed. The respective deep N ⁺ -type and P ⁺ -type regions may be formed before the channel ion implantation.

Further, in the step shown in FIG.
After the dummy gate oxide film 19 is entirely removed, a gate oxide film 23 having a thickness of about 50 to 120 ° is formed on the surface by an oxidation method. Note that the minimum value of the thickness of the gate oxide film 23 at this time is desirably 120 ° or less. Further, a first polycrystalline silicon layer 24 having a thickness of 50 to 500 ° is deposited thereon by CVD (chemical vapor deposition). The temperature at this time is a temperature of 610 ° C. or higher.
Further, the contact portion 54 with silicon substrate 10 is removed from first polycrystalline silicon layer 24 using a resist mask.

Subsequently, a corresponding portion of the gate oxide film 23 is formed.
Is also removed. The contact part 54 includes an NPN and a PN
External transistor extraction electrode contact of P transistor,
Further, it becomes a source / drain extraction electrode contact of the PMOS and NMOS transistors.

Further, in the step shown in FIG.
A second polycrystalline silicon layer 55 is deposited on the entire surface at a temperature of 600 ° C. or less at a temperature of 1000 to 3000 °. In addition, 600 ° C
Instead of using the following temperatures, hydrogen may be used as the carrier gas. Further, an N-type impurity is ion-implanted at a high concentration into a region where PNP and NMOS transistors are formed in second polycrystalline silicon layer 55. For example, As has an acceleration energy of 40 keV and 5 × 10 ¹⁵ / cm
Ions are implanted at a dose of ² . In addition, NPN, P
P-type impurities are ion-implanted at a high concentration into a region where a MOS transistor is formed. For example, BF ₂ is 40 keV
Ions are implanted at an acceleration energy of 5 × 10 ¹⁵ / cm ² .

Thereafter, a heat treatment at 900 ° C. for 10 minutes may be applied to activate the impurities implanted in the second polycrystalline silicon layer 55 and simultaneously diffuse the impurities into the semiconductor substrate. Further, a polycide structure is formed by depositing a silicide 56 such as MoSi ₂ on the entire surface by a sputtering method. Further, the impurity may be implanted after the MoSi ₂ is sputtered.

Further, in the step shown in FIG.
An SiO ₂ film 30 is deposited on the entire surface by CVD at about 2000 °. This SiO ₂ film 30 is made of NPN and P
It is also possible to form so as to remain only on the NP transistor region. Thereafter, the external base extraction electrode regions 58 and 59 of the PNP and NPN transistors, PMO
The polycide is patterned on the gate electrode regions 49 and 50 of the S and NMOS transistors, the source / drain extraction electrode regions 61 and 60, and the wiring formation region. At this time, the minimum value of the length of the gate electrode is 0.6 μm or less.

Thereafter, the patterned sidewalls of the polycrystalline silicon layer and the surface of the silicon substrate are oxidized by post-oxidation in an oxidizing atmosphere at 900 ° C. for 20 minutes to form a post-oxide film 33. At this point, the N ⁺ and P ⁺ regions for external electrode extraction, ie, the external base regions 27 and 5 of the NPN and PNP transistors
7. Source extraction regions 62 and 63 for PMOS and NMOS transistors are formed, respectively.

Further, As is added to the NMOS transistor region.
Are implanted with an acceleration energy of 60 keV and a dose of 5 × 10 ¹⁵ / cm ² , and the BF ₂ has an acceleration energy of 60 keV in the N ⁺ type source region 28 and the N ⁺ type drain region 29 and the PMOS region. 5 × 10 ¹⁵ / c
By ion implantation at m ² , P ⁺ -type source and drain regions 25 and 26 are formed in a self-aligned manner with respect to the gate electrode.

At the same time, As is ion-implanted with an acceleration energy of 60 keV and a dose of 3 × 10 ¹³ / cm ² , and B is implanted with an acceleration energy of 15 keV and 3 × 10 3 / cm ^2.
The ions are implanted at a dose of ¹³ / cm ² to form an N ⁻ type internal base 64 of the PNP transistor and a P ⁻ type internal base 34 of the NPN transistor, respectively.

Thereafter, in the step shown in FIG.
A 2000 ° SiO ₂ film 35 is deposited by the CVD method. Furthermore, NPN and PN from the SiO ₂ film 35
Portions (emitter openings) 41 and 42 serving as emitters of the P transistor are selectively etched. As a result, the emitter openings 41 and 42 and the external base extraction electrodes 59 and 58 can be formed in a self-aligned manner.

Thereafter, a third polycrystalline silicon layer is formed.
The emitter electrode 3 of the PNP transistor is deposited on the entire surface.
7. NPN transistor emitter electrode 40, NMOS
The source / drain extraction electrode 39 of the transistor, and
Source / drain extraction electrode 38 of PMOS transistor
Is formed. In this case, the LPCVD method is used.
However, the temperature during deposition should be 600 ° C or less
H as carrier gas _TwoIs used. The film thickness is
1000 to 4000 is appropriate.

Thereafter, B is added to the PNP transistor region.
However, As is ion-implanted into a region used as an NPN transistor and a low-resistance wiring at an acceleration energy of 60 keV and a dose of 1 × 10 ¹⁶ / cm ² . The non-implanted region can be used as a high resistance element or a TFT element. If a high-resistance element is not formed, silicide such as MoSi ₂ or a metal can be deposited over the entire surface of the third polycrystalline silicon layer by a sputtering method.

The silicide or metal material is made of at least one of Mo, W, Ti, Ta and Co.

Thereafter, the Si film is formed by a normal CVD method.
An interlayer insulating film 43 made of O ₂ , BPSG, or the like is formed. After a reflow process at 800 ° C. to 900 ° C. for 30 minutes to 1 hour, a contact hole 36 is formed, and an Al or AlCuSi alloy or Ti , T
Al or Al on the laminated structure of barrier metal such as iN
A CuSi alloy layer is deposited. Thereafter, a wiring pattern 47 made of, for example, aluminum is formed by patterning. After the reflow step, 1000
By performing a heat treatment at a temperature of from 1 ° C. to 1100 ° C. for from 5 seconds to 60 seconds, a good bipolar transistor can be formed by increasing the impurity concentration in the emitter region.

FIG. 3 (a) shows a PMOS transistor and N
FIG. 3B is a plan view of a conventional semiconductor device including a PN bipolar transistor, and FIG.
3A to 3C are plan views of the semiconductor device according to the present invention manufactured by the steps of FIG. In the figure, G is a gate electrode of a PMOS transistor, D is a drain, B is a base electrode of an NPN bipolar transistor, and E is an emitter electrode. As shown in FIG. 3A, a conventional semiconductor device requires a margin of, for example, a = 7.5 (μm) from the center of the gate electrode to the boundary of the active region in manufacturing. On the other hand, in the semiconductor device of the present invention, since the drain extraction electrode and the base extraction electrode are formed of the same material in one layer, this margin is unnecessary, and FIG.
As shown in (b), the distance can be reduced to a '= 5 (μm). As a result, the element density becomes about 67%.
To be reduced. Therefore, as shown in FIG. 4 below,
The technical idea of the present invention is more effectively applied to a circuit configuration in which a drain extraction electrode of a PMOS transistor and a base extraction electrode of a bipolar transistor are connected.

FIG. 4 is a diagram showing an example of a specific circuit configuration to which the present invention is applied. The semiconductor device includes: a PMOS transistor having a drain to which a first voltage (VDD) is applied; an NMOS transistor having a gate connected to the gate of the PMOS transistor;
A base connected to the source of the S transistor;
An NPN bipolar transistor having a collector to which a voltage (VDD) is applied, a base connected to the source of the NMOS transistor, an emitter connected to the drain of the NMOS transistor and the emitter of the NPN bipolar transistor, and a second voltage. And a PNP bipolar transistor having a collector to which (GND) is applied. The gate electrode of the NMOS transistor is N-type and the gate electrode of the PMOS transistor is P-type.

As described above, the CMOS transistor is formed by forming the gate electrode of the NMOS transistor with the N-type and the gate electrode of the PMOS transistor with the P-type.
Since the N bipolar transistor and the PNP bipolar transistor are combined, a variation in circuit design is increased, and a semiconductor device capable of operating at a lower voltage and at a higher speed can be obtained. In particular, when the present semiconductor device is configured as shown in FIG. 4, the circuit speed can be increased by about 10% at a low voltage.

In the device of the present invention, the drain capacitance C _drain generated between the drain extraction electrode of the PMOS transistor and its diffusion layer and the capacitance C _cb between the base and the collector are about 40% lower than those of the conventional device. , Which can increase the circuit speed by about 10%. Further, as shown in FIG. 2 (c), an oxide film remains even after the device is formed, and the offset structure is adopted, so that the IC
Manufacturing yield can be improved by about 20%.

FIG. 5 is a characteristic diagram comparing the gate lengths of the conventional semiconductor device and the semiconductor device of the present embodiment. In the present embodiment, since the P ⁺ type polycrystalline silicon layer is used instead of the N ⁺ type in forming the gate of the PMOS transistor, a PMOS transistor having a gate length of about 0.3 μm is formed as shown in FIG. Becomes possible.

As apparent from the embodiments described above, the present invention includes the following features.

The gate electrode of the NMOS transistor is N-type, and the gate electrode of the PMOS transistor is P-type. As a result, a surface channel is formed in each transistor, and the transistor is less likely to be adversely affected by the short channel effect.

The gate electrode of the PMOS transistor and the base extraction electrode of the NPN bipolar transistor are formed in the same layer. Thereby, the number of steps can be reduced.

The same type of polysilicon is used for the electrodes (including the gate electrode and the extraction electrode) of the MOS transistor and the base extraction electrode of the bipolar transistor.
One heat step is performed for the OS transistor, and two heat steps are performed for the bipolar transistor.

The base extraction electrode and the opening for the emitter extraction electrode have a self-aligned structure.

The gate electrode and the base take-out electrode have a laminated structure of silicide or metal and polycrystalline silicon.

The emitter extraction electrode has a laminated structure of silicide or metal and polycrystalline silicon.

The silicide or metal is Mo,
It is composed of at least one element selected from the group consisting of W, Ti, Ta, and Co.

The external base region of the bipolar transistor has an intermediate concentration between the external base extraction electrode concentration and the internal base region concentration.

The source / drain extraction electrode and the gate electrode of the MOS transistor are formed in the same layer.

The N ⁺ -type or P ⁺ -type source or drain region serving as a low-resistance region has a third
Formed by impurity diffusion from the polycrystalline silicon layer. N well region and P of NPN bipolar transistor
The concentration of the N-well region of the MOS transistor is substantially the same.

The P well region of the PNP bipolar transistor and the N well region of the NMOS transistor have substantially the same concentration.

The thickness of the first polycrystalline silicon layer is 500 ° or less.

The thickness of the second polycrystalline silicon layer is 1000 °
That is all.

The first polycrystalline silicon layer is formed at a temperature of 610 ° C. or higher, and the second polycrystalline silicon layer is formed at a temperature of 600 ° C. or lower.

During the formation of the second polycrystalline silicon layer, SiH
H ₂ can be used for the carrier gas of No. ₄ .

In the step of forming the third polycrystalline silicon layer serving as an emitter, H ₂ can be used as a carrier gas of SiH ₄ .

In the step of depositing the third polycrystalline silicon layer serving as an emitter, deposition is performed at a temperature of 600 ° C. or less.

A third polysilicon layer serving as an emitter is formed simultaneously with a high resistance element, a TFT element, or a low resistance wiring material.

The emitter electrode of the bipolar transistor and the source / drain extraction electrode of the MOS transistor are formed by the third polycrystalline silicon layer.

A high-concentration buried P ⁺ -type region is formed below the PNP bipolar transistor, and a low-concentration P-type region exists between this region and the buried N ⁺ -type region.

The maximum value of the voltage applied to at least one MOS transistor during operation is 3.5 V or less.

Further, according to the embodiment described above, the external base contact resistance, which was about 1 kΩ
It is possible to reduce the resistance to 0 Ω or less, and to reduce the emitter resistance from about 1 kΩ to 20 Ω. In addition, the characteristics of a conventional NPN bipolar transistor having a maximum threshold f _{Tmax of} 10 GHz can be set to 15 GHz or more. Further, the pattern area of the NPN transistor can be reduced to 1/10 or less, and the number of steps required to form a bipolar transistor having the same characteristics can be reduced by one.
/ 10 or less.

[0064]

According to the present invention, the surface channel is formed in each transistor by configuring the gate electrode of the NMOS transistor to be N-type and the gate electrode of the PMOS transistor to be P-type, thereby adversely affecting the short channel effect. Hard to receive. As a result, a fine and high-performance CMOS transistor can be formed.

Further, by combining such a CMOS transistor with an NPN bipolar transistor and a PNP bipolar transistor, a variety of circuit designs can be increased, and a semiconductor device capable of operating at a lower voltage and at a higher speed can be obtained. In particular, when the present semiconductor device is configured as shown in FIG.
It is possible to increase by 0%.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a front part of a step of forming a BiMOS element according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a rear part of a step of forming a BiMOS element according to one embodiment of the present invention.

FIG. 3A is a plan view of a conventional semiconductor device including a PMOS transistor and an NPN bipolar transistor, and FIG. 3B is a plan view of the embodiment shown in FIGS.
FIG. 14 is a plan view of the BiMOS element manufactured by the step of FIG.

FIG. 4 is a diagram showing an example of a specific circuit configuration to which the present invention is applied.

FIG. 5 is a characteristic diagram comparing gate lengths of a conventional semiconductor device and the semiconductor device of the present embodiment.

[Explanation of symbols]

8 high-concentration buried P-type region, 9 low-concentration buried P-type region, 10 silicon semiconductor substrate, 11 insulating film, 12
... opening, 13 ... buried collector layer, 14 ... N-type epitaxial layer, 15 ... N-type well region, 16 ... P-type well region, 17 ... field oxide film, 18 ... ion implantation region, 19 ... dummy gate oxide film, 20, 21 ... channel ion implantation region, 22 ... N ⁺ type ion implantation region, 23 ...
Gate oxide film, 24 first polycrystalline silicon layer, 25 P
⁺ Type source region, 26 ... P ⁺ type drain region, 27 ... external base region, 28 ... N ⁺ type source region, 29 ... N ⁺ type source region, 30 ... SiO ₂ film, 33 ... post oxide film, 34
... internal base region of NPN bipolar transistor, 3
5. SiO ₂ film, 36 contact hole, 37 PN
Emitter of P bipolar transistor, 38 ... PMOS
Source / drain extraction electrode of transistor, 39 ... PM
Source / drain extraction electrode of OS transistor, 40 ...
Emitter of NPN bipolar transistor, 41 ... NP
A region 42 to be an emitter of an N bipolar transistor, 42
... A region serving as an emitter of a PNP bipolar transistor, 43... An interlayer insulating film, 47.
... Shallow base of PNP bipolar transistor, 5
2. Shallow base of NPN bipolar transistor,
53: deep P ⁺ type region, 54: NPN bipolar transistor, external base electrode contact of PNP bipolar transistor, source / drain electrode contact of NMOS and PMOS transistor, 55: second polysilicon layer, 56: silicide, 57: PNP External base region of bipolar transistor, 58 ... External base extraction electrode of PNP bipolar transistor, 59 ... N
External base extraction electrode of PN bipolar transistor,
Reference numeral 60: a source / drain extraction electrode of an NMOS transistor; 61, a source / drain extraction electrode of a PMOS transistor; 62, a source extraction region of a PMOS transistor; 63, a source extraction region of an NMOS transistor;
64: internal base region of the PNP bipolar transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8249 H01L 27/06 H03K 19/01-19/082 H03K 19/092-19/096

Claims (1)

(57) [Claims] A PMOS transistor having a drain to which a first voltage is applied; an NMOS transistor having a gate connected to a gate of the PMOS transistor; a base connected to a source of the PMOS transistor; NP with voltage applied collector
An N bipolar transistor; a base connected to a source of the NMOS transistor; a drain of the NMOS transistor;
PN having an emitter connected to the emitter of the PN bipolar transistor and a collector to which a second voltage is applied
A semiconductor device comprising: a P bipolar transistor; and a gate electrode of the NMOS transistor is N-type, and a gate electrode of the PMOS transistor is P-type.