JPH0527266B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for manufacturing a complementary insulated gate field effect transistor (hereinafter referred to as a CMOS transistor), which can be operated with a 5V power supply even with a gate length of 0.5 μm or less. The present invention relates to a method for manufacturing ultra-fine CMOS transistors with high breakdown voltage.

[Background of the invention]

CMOS is a structure in which a P-channel MOS (hereinafter referred to as PMOS) and an N-channel MOS (hereinafter referred to as NMOS) are formed as a pair on the same chip.

FIG. 1 is a cross-sectional structural diagram of a conventional CMOS having a gate length of 2 μm or more.

In FIG. 1, 1 is an N conductivity type semiconductor substrate;
Reference numeral 2 denotes a P conductivity type diffusion layer region formed in the semiconductor substrate 1 and is called a well. 3 is a field oxide film, 4 and 5 are formed in well 2
In the NMOS source and drain diffusion layer regions, n
It has a conductivity type, and its maximum impurity concentration is 10 ²⁰ cm ^-3 or more. 6 and 7 are PMOS source and drain diffusion layer regions, which have P conductivity type;
Its maximum impurity concentration consists of 10 ¹⁹ cm ^-3 or more. 8 and 9 are a gate insulating film and a gate electrode, respectively. 10 and 11 are a protective insulating film and a source or drain electrode, respectively.

A CMOS transistor having a conventional structure having such a structure of impurity concentration in the drain diffusion layer has various drawbacks as the device becomes smaller.

(i) Decrease in breakdown voltage between source and drain As devices become smaller, the channel length decreases, resulting in a decrease in punch-through breakdown voltage. Although the punch-through breakdown voltage can be improved by increasing the substrate concentration, increasing the substrate concentration conversely reduces the avalanche breakdown voltage. Channel length is 0.3μm
The extremely small NMOS shown below has an extremely low source-drain breakdown voltage of 2V or less, making it impossible to operate with the normal power supply voltage of 5V.

Furthermore, in order to improve the punch-through voltage, increasing the substrate concentration will increase the channel conductance.
Since this is accompanied by a decrease in gm, the high-speed operation characteristics obtained by miniaturization of insulated gate field effect transistors (hereinafter simply referred to as transistors) are inhibited.

(ii) Destruction of transistors due to latch-up The biggest drawback of CMOS transistors with conventional structures is the destruction of transistors due to thyristor operation called latch-up. This latch-up phenomenon becomes particularly noticeable as CMOS transistors become smaller. In other words, in a CMOS transistor in which the distance between NMOS and PMOS is shortened, a parasitic thyristor having an NPNP structure is formed between the drain 5, well 2, semiconductor substrate 1 of NMOS, and source 6 or drain 7 of PMOS. Ru. The above thyristors start operating when triggered by the application of overvoltage, the occurrence of internal transient overvoltage during normal switch operation, or the induction of fractional carriers due to irradiation with light or radiation, and the thyristor continues to operate until the power supply is stopped. It becomes impossible to suppress. Based on this thyristor operation, excessive current can be
Because the current flows through the transistor, the transistor is destroyed.

The above thyristor operation is realized as the distance between well 2 and PMOS is reduced as CMOS transistors become smaller, and the product of the current gain factors of the parasitic PNP bipolar transistor and the parasitic NPN bipolar transistor becomes larger than 1. It is known that this occurs due to the

A method has been proposed to prevent thyristor operation by reducing the current gain factor product in each of the above parasitic bipolar transistors. In other words, a CMOS transistor structure in which the source 6 and drain 7 of the conventional structure PMOS shown in FIG. 1, which are formed by P ⁺ N junctions, are replaced with Schottky junctions was published in the Proceedings of the 1982 International Electron Devices Meeting. It is listed on page 462. As mentioned above, “CMOS latch-up elimination phenomenon using short key barrier PMOS”
Using the Schottky barrier PMOS), the paper takes advantage of the fact that the fractional carrier injection efficiency in a Schottky junction is extremely small compared to that in a P ⁺ N junction, and reduces the current gain factor of a parasitic PNP bipolar transistor to a P ⁺ N The latch-up phenomenon has been solved by reducing this to less than 1/100 compared to conventional structures using bonding.

The above method uses Schottky junctions to form source and drain junctions instead of P ⁺ N junctions.
Although the latch-up phenomenon can be prevented in CMOS transistors, there are drawbacks specific to Schottky junctions. In other words, in transistors using Schottky junctions, the drain junction leakage current is large, the output becomes non-linear and ohmic characteristics cannot be obtained, and the transfer conductance is low, making it difficult to secure sufficient current and There are various drawbacks such as inability to operate.

The above-mentioned drawbacks based on the Schottky junction were solved by the later proposed "Lightly doped Schottky transistor".
schottky MOSFET) (see Proceedings of the International Society for Electronic Devices, 1982, p. 466).In other words, in the above Schottky transistor, if a Schottky junction is formed on the drain region with a low impurity distribution, the drain Junction leakage current can be reduced, and transfer conductance can be made close to that of a PMOS with a normal structure.

However, the method of configuring a CMOS transistor using a structure combining a low impurity concentration drain diffusion layer and Schottky matching also has the following drawbacks. That is, the above-mentioned document “CMOS
latchup elimination using schottky barrier
As described in ``PMOS'', the current gain factor of a parasitic NPN bipolar transistor when the source and drain junctions of an NMOS are formed by a Schottky junction is the same as the current gain factor of a parasitic NPN bipolar transistor in which the drain junction is formed by an N ⁺ P junction. This is up to 10 times higher than the current gain factor of a parasitic NPN bipolar transistor in
CMOS transistors that form PMOS and NMOS have the disadvantage that the source and drain junctions of PMOS are formed by shot-key junctions, and each junction of NMOS is more prone to latch-up phenomenon than a CMOS transistor formed by a normal N ⁺ P junction. .

According to the above two documents regarding prevention of latch-up by a Schottky junction, there is a PMOS in which a Schottky barrier is formed on each surface of the source region and drain region with a low impurity concentration distribution, and a PMOS in which a Schottky barrier is formed on each surface of the source region and drain region with a normal high impurity concentration distribution. A CMOS transistor can be constructed by combining it with an NMOS on which a diffusion layer is formed.
This is the most desirable from the viewpoint of preventing latch-up.

However, the conclusions obtained from the above two documents and their combination are valid only from the viewpoint of preventing latch-up of CMOS transistors, and are not related to the decrease in breakdown voltage of NMOS and PMOS due to miniaturization of CMOS transistors. No solutions have been proposed for the shortcomings.

In particular, ultra-fine CMOS with a channel length of 0.5 μm or less
Regarding transistors, the above two documents do not contain any information and are completely powerless against the above-mentioned drawbacks.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the conventional technology, to operate with a normal power supply voltage even with an extremely short channel length, and to prevent the latch-up phenomenon.
The object of the present invention is to provide a method for manufacturing a CMOS transistor.

[Summary of the invention]

In order to achieve the above object, the method for manufacturing a complementary insulated gate field effect transistor of the present invention provides a P-type drain region of a P-channel MOS transistor into which boron is introduced and an impurity concentration of 10 ¹⁷ to 10 ¹⁹ cm ^-3 ; Arsenic is introduced into the N-channel MOS transistor with an impurity concentration of 10 ¹⁷ to 10 ¹⁹ cm ^-3.
a first step of forming a type drain region on a silicon semiconductor substrate; a second step of forming a high melting point metal on the P type drain region and the N type drain region; a third step of forming a silicide layer of the refractory metal on the P-type drain region and the N-type drain region by heat treatment;
During the process, a Schottky barrier is formed in the P-type drain region of the P-channel MOS transistor, while a Schottky barrier is formed directly under the silicide in the N-type drain region from approximately 1.0 cm higher than before the silicide is formed.
The present invention is characterized in that a precipitated layer with an impurity concentration of an order of magnitude higher than that of 10 ¹⁸ to 10 ²⁰ cm ^-3 is formed, and the precipitated layer forms an ohmic contact with the N-type drain region of the N-channel MOS transistor.

[Embodiments of the invention]

The present invention is based on the results of an analysis of the high impurity concentration region in the drain diffusion layer, going back to its physical basis without being bound by conventional wisdom. When a silicide layer of a high melting point metal is formed on the surface of the drain diffusion layer, only when the drain diffusion layer is formed with N conductivity type impurities such as phosphorus (P) and elemental (As), the surface of the drain diffusion layer is There is a phenomenon in which the impurity concentration becomes high at a depth of about 10 nm. That is,
In NMOS, if the surface impurity concentration of the drain diffusion layer is 1×10 ¹⁸ cm ^-3 or more, good ohmic characteristics can be obtained between the silicide layer and the semiconductor surface, and no problems will occur in the characteristics as NMOS. The facts were discovered.

A drain diffusion layer in a typical transistor has a high impurity concentration region of 10 ²⁰ cm ^-3 or more near the surface of a semiconductor substrate, and has an impurity concentration that attenuates in a Gaussian distribution or an error function distribution toward the inside of the substrate. By applying a voltage to the above-mentioned normal drain diffusion layer and analyzing the application limit as a function of depth, that is, impurity concentration, it was found that only an extremely weak electric field is applied in regions with high impurity concentration of 10 ²⁰ cm ^-3 or more. . This fact indicates that from the viewpoint of increasing the breakdown voltage of ultra-fine transistors, the presence of high impurity concentrations is rather harmful, and it is desirable that the maximum impurity concentration of the drain diffusion layer be 10 ¹⁹ cm ^-3 or less. There was found. The role of the high impurity concentration region of 10 ²⁰ cm ^-3 or more in the transistor is as follows:
The purpose of this is to reduce the resistance of the diffusion layer and ensure good ohmic contact with the wiring metal.The latter role, that is, good ohmic contact with the wiring metal, is
Replacement is possible with a structure of a drain diffusion layer having a surface impurity concentration of 10 ¹⁸ cm ^-3 or higher and a silicide layer on the diffusion layer. It is known that the former role mentioned above, that is, reducing the source and drain diffusion resistances, can be achieved by siliciding the surfaces of the source and drain diffusion layers, especially when forming extremely shallow junctions in ultrafine transistors. , the effect of reducing resistance by silicidation is remarkable.

Therefore, the CMOS transistor of the present invention develops the concept based on the above analysis results, and replaces the high impurity concentration region of the drain diffusion layer with a thin silicide layer connected to the drain diffusion layer through ohmic contact. This method utilizes the results of analytically determining the optimal conditions regarding impurity concentration. The above-mentioned optimum conditions are particularly optimum conditions for increasing the withstand voltage of an ultra-fine transistor having a gate length of 0.5 μm or less and for preventing latch-up.

FIGS. 2 and 3 are diagrams showing analysis results according to the present invention, respectively, and represent curves of source-drain breakdown voltage and maximum substrate current determined as a function of the surface impurity concentration of the drain diffusion layer.

In FIG. 2, as the source-drain breakdown voltage, the avalanche breakdown voltage is shown by a dotted line, and the punch-through breakdown voltage is shown by a solid line. Each breakdown voltage is determined as a function of channel length.

In FIG. 2, the avalanche breakdown voltage is for PMOS, and the NMOS values generally tend to be 0.5-1 (V) lower than the illustrated curve.
Regarding punch-through voltage, PMOS and NMOS
There is no difference between the values.

A newly revealed fact from Figure 2 is that in transistors with a channel length of 0.5 μm or more,
The surface impurity concentration of the drain diffusion layer is set to 3×10 ¹⁸ cm ^-3
If set to , it is possible to achieve a breakdown voltage of 10V or more, which is approximately twice the source-drain breakdown voltage of a transistor with the same size and normal structure. In addition, in transistors with a channel length of 0.4 μm or less, there is an optimum drain diffusion layer surface impurity concentration depending on the channel length, and in a transistor with a channel length of 0.3 μm, the drain diffusion layer surface impurity concentration is approximately By setting it to 1×10 ¹⁸ cm ^-3 , the source/drain breakdown voltage can be improved to about 7V. Channel length is 0.2μm
In a PMOS transistor, if the drain surface impurity concentration is set to 5×10 ¹⁷ cm ⁻³ , a breakdown voltage of approximately 5V can be obtained.

Next, in Figure 3, the substrate current flowing toward the substrate side of the fractional carrier induced by the drain current is determined as a function of the gate voltage, and the maximum value, that is, the maximum substrate current, is determined by the impurity concentration on the surface of the drain diffusion layer. It is analyzed as a function. In Figure 3, the channel length is 1.0 μm, and the channel width is 10 μm.
Regarding the transistor, the junction depth of the source and drain diffusion layers is taken as a parameter, and the drain voltage is 5V.

A new fact revealed from Figure 3 is that if the surface concentration of the drain diffusion layer is set to 10 ¹⁷ to 10 ¹⁸ cm ^-3 , the substrate current can be reduced to that of a normal structure, although it depends somewhat on the drain junction depth. This is an order-of-magnitude improvement, and is expected to prevent the latch-up phenomenon.

When a silicide layer is formed on a drain diffusion layer with an optimum surface impurity concentration for latch-up resistance, no ohmic contact is obtained and a Schottky barrier is formed.

In the present invention, based on the new analysis results obtained from FIGS. 2 and 3 and the two reference documents mentioned above, we have realized an ultra-fine CMOS transistor with unprecedented high breakdown voltage and latch-up resistance. That is, in the CMOS transistor of the present invention, the PMOS is formed by the drain junction of the Schottky barrier based on the above two documents;
For NMOS, the drain junction is formed by a combination of a diffusion layer with a surface impurity concentration of 10 ¹⁸ cm ^-3 or more and a silicide layer with ohmic contact, based on the new analysis results obtained from Figure 2. ing. This not only improves the latch-up resistance, but also reduces the surface impurity concentration of each source/drain diffusion layer of PMOS and NMOS from the viewpoint of increasing the breakdown voltage of ultra-fine CMOS transistors of 0.5 μm or less.
Further optimization becomes possible.

FIG. 4, FIG. 5, and FIG. 6 are cross-sectional structural views of the manufacturing process of a CMOS transistor showing the first embodiment of the present invention, respectively.

In Figures 4 to 6, 1 is n conductivity type specific resistance.
It is a silicon substrate of 0.4 Ω cm, and a P-conductivity type well 2 with a junction depth of 2 μm and a surface impurity concentration of 1×10 ¹⁶ cm ^-3 is formed at a predetermined position on this substrate 1 using a known boron diffusion method. do. Next, after selectively forming a field oxide film 3 with a thickness of 0.5 μm using a known device isolation technique, the semiconductor surface of the active region is exposed, and a clean gate oxide film 8 with a film thickness of 20 nm is formed. Form. Thereafter, a silicon thin film with a thickness of approximately 0.4 μm is formed on the gate oxide film 8, and phosphorus is diffused into the silicon thin film at a high concentration by thermal diffusion using POCl ₃ as a diffusion source. Next, the surface of the silicon thin film is thermally oxidized to form a 0.2 μm thick silicon oxide film on the silicon thin film. Thereafter, the silicon oxide film and the silicon thin film are simultaneously etched by photolithography to form a desired circuit configuration, leaving the gate protection insulating film 12 and the gate electrode 9, respectively. Note that the width of the gate electrode 9 after photoetching, that is, the channel width, is 1.0,
It was carried out under five conditions: 0.5, 0.3, 0.2 and 0.1 μm.

After the photo etching above, tetraethoxysilane (Si
(OC ₂ H ₅ ) ₄ ) by chemical vapor phase reaction using
A silicon oxide film having a thickness of m is deposited over the entire surface. When the deposited film is etched in a direction perpendicular to the surface of the semiconductor substrate by reactive sputter etching and the silicon oxide deposited film deposited on the flat areas is removed, silicon is etched only on the sidewalls of the gate electrode 9 and the field oxide film 3. Oxide deposited film 13
is left behind. Next, a 0.8 μm thick photoresist film is left on the gate oxide film 8 in the area excluding the well 2, and arsenic ions are implanted under the condition of acceleration energy of 70 KeV. The above ion implantation is
For the well region 2, the impurity concentration is applied via the gate oxide film 8, and the impurity concentration is the maximum at the surface of the semiconductor substrate. On the other hand, the implanted ions are blocked in areas other than the well region 2 by the photoresist film, and are not implanted into the semiconductor substrate 1. After the above-mentioned ion implantation, the remaining photoresist film is removed, and the implanted ions are activated and heat treated to form an N conductivity type source 4 and drain 5 (see FIG. 4).

The surface impurity concentration of each of the source/drain diffusion layers 4 and 5 is 3×10 ¹⁸ cm ⁻³ when the channel length is 0.5 μm or more, and 1×10 ¹⁸ cm −3 when the channel length is 0.3 μm or less ^. Set the amount of arsenic ions so that they are ^finally formed. Further, the above heat treatment conditions are controlled so that the junction depth of the above source 4 and drain diffusion layer 5 is finally 0.25 μm. After the above heat treatment, a photoresist film with a thickness of 0.8 μm is covered only on the well 2 region, and the boron is accelerated with energy.
Ion implantation is performed under 70KeV conditions. By the above ion implantation, boron was implanted into the semiconductor substrate 1 through the gate oxide film 8 in the region other than the well 2, and the maximum impurity concentration was at the surface of the semiconductor substrate 1. In the well region 2, ion implantation is blocked by the photoresist film and is not implanted into the semiconductor substrate 1. After the above ion implantation, the remaining photoresist film is removed, and then the implanted boron ions are activated by heat treatment to form the source 6 and drain 7 of P conductivity type (see FIG. 5). . The surface impurity concentration of each of the source 6 and drain 7 diffusion layers was finally determined under three conditions: 3×10 ¹⁷ cm
^-3 , 1×10 ¹⁸ cm ^-3 and 3×10 ¹⁸ the amount of boron to be injected is set. In addition, the final junction depth of the source 6 and drain 7 diffusion layers is 0.25 μm.
The above heat treatment conditions are controlled so that m.
After the above heat treatment, the gate oxide film exposed on the semiconductor substrate 1 is removed, and platinum (Pt) having a thickness of 50 nm is deposited on the entire surface by sputtering, followed by heat treatment at 450°C. . Through the above-described low-temperature heat treatment, a platinum silicide (PtSt) layer 14 is formed in a self-aligned manner on each surface of the source diffusion layer regions 4 and 6 and the drain diffusion layer regions 5 and 7, where the surface of the semiconductor substrate 1 is exposed. . In the above heat treatment, platinum (Pt) does not react on the field oxide film 3, the sidewall deposited oxide film 13, and the protective oxide film 12, so the silicide layer 14
is not formed. After the above-mentioned low-temperature heat treatment, platinum (Pt) is etched over the entire surface with aqua regia. Platinum silicide (PtSi) is not removed by aqua regia and remains in source diffusion layers 4 and 6 and drain diffusion layers 5 and 7.
It remains self-aligned only on top. At this point, directly under the platinum silicide (PtSi) layer 14 in the source 4 and drain 5 regions of N conductivity type, there is a precipitate approximately 10 nm thick with an impurity concentration one order of magnitude higher than the surface impurity concentration before formation of the platinum silicide layer. The layers are formed in a self-aligned manner to the platinum silicide (PtSi) layer 14. After forming the platinum silicide layer 14, a silicon oxide film 1 with a thickness of about 500 nm is formed by a chemical vapor phase reaction between monosilane (SiH ₄ ) and oxygen (O ₂ ).
0 is deposited on the entire surface of the silicon oxide film 10 in the portions forming the contact holes on the sources 4 and 6, the drains 5 and 7, and further on the gate electrode 9.
is selectively removed by photolithography. After the selective removal of the silicon oxide film 10 described above, a TiW film 15 is deposited on the entire surface by simultaneous sputtering of titanium (Ti) and tungsten (W) while leaving the photoresist film used in the above process. Thereafter, the photoresist film is removed, but since the TiW film on the photoresist film is removed at the same time in this step, the TiW film 15 is selectively left only in the area where the silicon oxide film 10 has been removed. Ru.
Finally, wiring 11 made of aluminum (Al) is formed according to the desired circuit configuration (see FIG. 6).

Note that the TiW film 15 is similar to the aluminum wiring 11.
This is necessary to prevent the reaction between the silicide layer 14 and the silicide layer 14.

Next, the product manufactured by the above manufacturing process is
First, we measured the breakdown voltage between the source and drain of a CMOS transistor and obtained the following results. That is, the surface impurity concentration in each diffusion layer of the P conductivity type source 6 and drain 7 is set to 3×
Although the PMOS set to 10 ¹⁷ cm ^-3 exhibits short-key characteristics, the breakdown voltage of transistors with channel lengths of 0.2 μm or more was able to obtain a value of about 5 V.
This value indicates that the P conductivity type drain surface impurity concentration is
This value is more than twice the breakdown voltage of a transistor with a conventional structure composed of 10 ¹⁹ cm ^{-3 or} more. The P conductivity type drain surface impurity concentration was set to 1×10 ¹⁸ cm ^-3
PMOS exhibits transistor characteristics based on a P ⁺ N contact, and its source-drain breakdown voltage is 6.5 to 7 V for transistors with a channel length of 0.3 μm or more. This value is 1.6 to 1.7 times higher than the conventional value, indicating that high voltage resistance has been achieved. Furthermore, the P conductivity type drain surface impurity concentration was set to 3×10 ¹⁸ cm ^-3.
PMOS also exhibits transistor characteristics based on a P ⁺ N junction, but its source-drain breakdown voltage is approximately 12V for transistors with a channel length of 0.5 μm or more. This value is more than 2V higher than the conventional value, meaning that high voltage resistance has been achieved.

The surface impurity concentration in each diffusion layer of the N conductivity type source 4 and drain 5 was set to 3×10 ¹⁸
In NMOS, a transistor with a channel length of 0.5 μm or more has a source-drain breakdown voltage of about 10V. This value is approximately twice as high as the conventional value, which means that the voltage resistance has been increased. Even in NMOS where the drain surface impurity concentration is set to 1×10 ¹⁸ cm ^-3 , good ohmic characteristics are ensured between the source 4 and drain 5 and the silicide layer 14, and the transistor characteristics based on the P ⁺ N junction are maintained. Obtained. Its source-drain breakdown voltage depends on the channel length, and the channel length
The voltage was approximately 6V for a 0.3μm transistor, and approximately 3V for a 0.2μm transistor. These values are more than twice as high as the source-drain breakdown voltage of an NMOS with a conventional structure.

The source-drain breakdown voltages of NMOS and PMOS in the CMOS transistor based on this example are in very good agreement with the analysis results shown in FIG. 2, which proves the validity of the above analysis. That is, according to this embodiment, the source-drain breakdown voltage of an ultra-fine CMOS transistor having a channel length of 0.5 μm or less can be improved by more than twice that of the conventional transistor. Specifically, for CMOS transistors with a channel length of 0.5 μm or more, the surface impurity concentration of each source/drain diffusion layer of NMOS and PMOS is set to 3×10 ¹⁸
cm ^-3 and when the channel length is 0.3 μm, the above impurity concentration is set to 1×10 ¹⁸ cm ^-3 and the transistor is completed based on this example.
It is possible to obtain 10V and 6V high voltage ultra-fine CMOS transistors. Also, the channel length is 0.2μ
In the case of m, the surface impurity concentration of the source/drain diffusion layer of PMOS is set to 3×10 ¹⁷ cm ^-3 and the surface impurity concentration of NMOS is set to 1×10 ¹⁸ cm ^-3 . If a transistor is completed based on this, it will be an ultra-fine transistor with a source-drain breakdown voltage of 3V.
You can get CMOS transistors. In the above transistor, between the source 6 and drain 7 of the PMOS and the silicide layer 14,
Although a Schottky barrier is formed, this does not pose a problem in terms of characteristics. Rather, this shot key barrier has the function of improving the latch-up resistance.

Next, the latch-up resistance characteristics of the CMOS transistor manufactured by the manufacturing process shown in this example will be evaluated. The latch-up resistance characteristics are measured as follows: That is, the current gain factor β _N of a parasitic NPN transistor in which the NMOS drain 5 is the emitter, the well 2 is the base, and the semiconductor substrate 1 is the collector, and the PMOS source 6 is the emitter, the semiconductor substrate 1 is the base, and the well 2 is the collector. The current gain factor β _P of the parasitic PNP transistor
The product β _N and β _P was measured. In this measurement ^{, a} voltage of 5 V is applied between base and collector, and β _N
β _P was calculated. As a result, we found a CMOS transistor with a drain surface impurity concentration of 3×10 ¹⁸ cm ^-3 and a channel length of 0.5 μm for MPOS and NMOS, and a CMOS transistor with a drain surface impurity concentration of 1×10 ¹⁸ cm ⁻³ and a channel length of 0.3 μm. CMOS transistors, and PMOS
The drain surface impurity concentration is 3×10 ¹⁷ cm ^-3 ,
The maximum values of each β _N and β _P product in a CMOS transistor with an NMOS surface impurity concentration of 1×10 ¹⁸ cm ^-3 and a channel length of 0.2 μm are both 10 ^-2 to 10 ^-4
It was hot. The above values do not satisfy the conditions β _N and β _P > 1 for latch-up to occur, and
The PMOS drain is connected to a Schottky junction.
β _N and β _P in a CMOS transistor in which the NMOS drain is configured with a normal high impurity concentration N ⁺ P junction
The value of the product is approximately equal to or less than 10 ^-2 .
From the above results, in a CMOS transistor in which the PMOS drain diffusion layer is set to a low impurity concentration, from the viewpoint of improving the source-drain breakdown voltage rather than from the viewpoint of latch-up resistance,
This means that the optimum condition for the impurity concentration on the drain surface of the NMOS can be set according to the desired channel length.

Next, in the CMOS transistor according to this example, a CMOS transistor with a channel length of 0.2 to 1.0 μm with each drain surface impurity concentration of NMOS and PMOS set to 5 × 10 ¹⁸ to 10 ²⁰ cm ^-3 was manufactured at the same time, and its source・Drain-to-drain breakdown voltage and latch-up resistance were measured. the above
The source-drain breakdown voltage of CMOS transistors has been improved by up to several volts over the conventional value, and β _N
Although the β _P product was also less than 1, the characteristics were slightly inferior compared to the above results.

FIGS. 7 and 8 are cross-sectional structural diagrams of the manufacturing process of a CMOS transistor showing a second embodiment of the present invention.

In the aforementioned first embodiment shown in FIG.
After leaving the silicon oxide deposited film 13 only on the sidewalls of the gate electrode 9 and the field oxide film 3 in a self-aligned manner, the exposed gate oxide film is completely removed. Next, a chemical vapor phase reaction between dichlorosilane (SiH ₂ Cl ₂ ) and hydrochloric acid (Hcl) is performed at a temperature of 775°C, and a polycrystalline or amorphous silicon thin film 16 with a thickness of 0.3 μm is formed on the surface of the well 2. and on the surface of the semiconductor substrate 1 that maintains N conductivity type (see FIG. 7). The formation conditions for the above silicon deposited film are dichlorosilane 200 c.c., hydrochloric acid 60 c.c.
Under cc conditions, the deposition rate is 10 nm/min. Under these conditions, unless a silicon nitride film (Si ₃ N ₄ ) is present on the surface to be deposited, it will be deposited selectively only on the silicon substrate, and even at the boundary with the sidewall insulating film 13 there will be unevenness called facets. It is possible to obtain a flat shape without

After the deposition of the silicon thin film 16, a photoresist film is selectively formed and boron ion implantation is performed so that the ion implantation is performed only in the silicon thin film portion over the well 2 region. The amount of boron implanted is set so that the impurity concentration in the silicon thin film 16 matches the impurity concentration on the surface of the well 2. The implant energy is 25 KeV. After that, the photoresist film used as a mask for ion implantation is removed, and then a high temperature short time heat treatment is performed at 1150°C for 15 seconds to activate the implanted ions and make the silicon thin film 16 into a single crystal. . The diffusion coefficient of impurities in the polycrystalline or amorphous silicon thin film 16 is 10 to 20% higher than that in single crystal silicon.
It is twice as large. Therefore, the boron implanted into the silicon thin film 16 on the well 2 by the above-described single-time heat treatment is distributed almost uniformly in the depth direction within the silicon thin film 16. After the heat treatment, N conductivity type source 4 and drain 5 and P conductivity type source 6 and drain 7 are formed in accordance with the first embodiment described above. The silicon thin film 16 has already been made into a single crystal by the above-described short-time high-temperature heat treatment. Therefore, the conditions for forming each source and drain described above are the same as in the first embodiment. In the subsequent steps, a CMOS transistor is manufactured in accordance with the first embodiment described above (see FIG. 8).

The CMOS transistor based on the second embodiment shown in FIG. 8 is based on the first embodiment described above.
It has the same dimensions as a CMOS transistor,
Comparing the source-drain breakdown voltages of both, the CMOS transistor of the second embodiment under the conditions of a channel length of 0.3 μm and a source and drain surface impurity concentration of 1×10 ¹⁸ cm ^-3 was higher by about 1 V.
A withstand voltage of 7V was obtained. In addition, the channel length is 0.2μm,
The withstand voltage of the CMOS transistor of the second embodiment was measured under the condition that the drain surface impurity concentration of NMOS and PMOS was 1×10 ¹⁸ cm ^-3 and 3×10 ¹⁷ cm ^-3 , respectively. Example CMOS
When comparing the breakdown voltage of the transistor, the former obtained a value of 5V, about 2V higher. The above value means that the breakdown voltage is more than three times higher than the source-drain breakdown voltage of a CMOS transistor based on a conventional structure. Based on the second example
In CMOS transistors, the product of current gain factors β _N and β _P for parasitic bipolar transistors
was measured for cases with various channel lengths and source/drain surface impurity concentrations, but all were based on the above-mentioned first example.
It was reduced to 2/3 to 1/2 compared to the measured value for CMOS transistors. As described above, the CMOS transistor based on the second embodiment has improved source-drain breakdown voltage and latch-up resistance characteristics compared to the CMOS transistor based on the first embodiment. This is considered to be because the bonding area was reduced and the effective channel length was increased due to the fact that the bonding area was placed within the semiconductor thin film 16.

9 and 10 are cross-sectional structural diagrams of a CMOS transistor showing a third embodiment of the present invention,
FIG. 3 is an impurity concentration distribution diagram in the depth direction in an N conductivity type drain diffusion region.

In the second embodiment shown in FIG. 7, after a polycrystalline or amorphous silicon thin film 16 is deposited on the semiconductor substrate 1 in a self-aligned manner, ions are deposited only on the silicon thin film portion above the well region 2. A photoresist film is left on the surface of the other areas for implantation. Thereafter, arsenic ions are implanted into the silicon thin film portion on the well region 2, and then the remaining photoresist film is removed.

Next, the well region 2 is covered with a photoresist film, and the photoresist film is left again so that ion implantation is performed only in the silicon thin film portion on the semiconductor substrate 1 having N conductivity type other than the well region 2. . After that, boron is ion implanted,
The photoresist film is completely removed again to expose the surface of the silicon thin film 16. In this state,
Perform single-hour high-temperature heat treatment at 1100℃ for 30 seconds. Even when heat treatment is performed under the above conditions, the silicon thin film 16 is not made into a single crystal, but maintains a polycrystalline or amorphous state. Since the diffusion coefficient of impurities in the polycrystalline or amorphous silicon thin film 16 is extremely large as described above, the silicon thin film 1 is
Arsenic and boron quickly become approximately uniform in concentration within 6. However, the diffusion coefficient of each impurity within the semiconductor substrate 1 is relatively small, and by the above-mentioned short-time heat treatment, the impurities were only diffused into the semiconductor substrate 1 by about 20 nm.

In this way, by ion implantation of arsenic and boron followed by short-time heat treatment, N conductivity type sources 4 and drains 5, and P conductivity type sources 4 and drains 5 are formed in the silicon thin film 16, well 2, and N conductivity type semiconductor substrate 1, respectively. A source 6 and a drain 7 are formed. After that, a platinum silicide (PtSi) layer 14 is formed on each of the sources 4 and 6 and the drains 5 and 7 in a self-aligned manner according to the first embodiment, and the subsequent steps are also the same as in the first embodiment. By carrying out the process based on this method, the CMOS transistor shown in FIG. 9 can be manufactured.

The impurity concentration distribution of the N-conductivity type source 4 and drain 5 of the CMOS transistor according to the third embodiment is divided into three regions ABC, as shown in FIG. That is, an impurity precipitation region A with a thickness of about 10 nm directly under the silicide layer 14, a uniform distribution region B inside the silicon thin film 16, and a well 2
This is a steep concentration distribution region C having a junction depth of about 20 nm within the region. In the P conductivity type source 6 and drain 7, the presence of the impurity precipitation region A was not observed.

In the CMOS transistor based on the third embodiment, the uniformly distributed concentration in the silicon thin film 16 is 1×10 ¹⁸ cm ^-3 and 3×
10 ¹⁸ cm ^-3 , 10 ¹⁹ cm ^-3 , 5×10 ¹⁹ cm ^-3 , and
Regarding PMOS, 1×10 ¹⁷ cm ^-3 , 3×10 ¹⁷ cm ^-3 ,
transistor by setting the arsenic or boron ion implantation dose to final values of 1×10 ¹⁸ cm ^-3 , 3×10 ¹⁸ cm ^-3 and 5×10 ¹⁸ cm ^-3 . was manufactured. Furthermore, transistors were manufactured with channel lengths of 0.1, 0.2, 0.3, 0.5, and 1.0 μm. Various of the above
For CMOS transistors, we measured the source-drain breakdown voltage and the product β _N and β _P of each current gain factor of the parasitic bipolar transistor. NMOS
The uniformly distributed impurity concentration in the drain 7 is 10 ¹⁹ cm ^-3
In the above cases, the improvement in the properties described above was not significantly observed. However, when the uniformly distributed impurity concentration was set at a low impurity concentration of 10 ¹⁷ to 10 ¹⁹ cm ^-3 , the improvement in the source-drain breakdown voltage was particularly remarkable. Uniformly distributed impurity concentration in the drain is 1
×10 ¹⁸ cm ^-3 with channel lengths of 0.1 and 0.2 μm
The source-drain breakdown voltage of each CMOS transistor reached 4.5 and 8V, respectively. Although these values are significantly improved compared to the case of the CMOS transistor based on the second embodiment, this effect was relatively more pronounced when the channel length was short. The uniformly distributed impurity concentration in the drain 5 in PMOS is 10 ¹⁷ to 10 ¹⁸ cm ^-3
Even when the gate length is set to less than 0.1μm and the gate length is 0.1 μm, the source-drain breakdown voltage is improved by several volts compared to the second embodiment, and the value is 5V.
The above has been reached.

The difference in this effect between the third embodiment and the second embodiment is that the low impurity concentration region to which the maximum drain electric field is applied is in the silicon thin film 16 in the third embodiment as shown in FIG. This is because they are formed almost uniformly, and it is thought that this makes the electric field dispersion effect more pronounced.

The impurity concentration distribution shown in FIG. 10 is unique when the silicon thin film 16 is formed of polycrystalline or amorphous material, and this structure is ultrafine.
It is believed that this will be extremely effective in improving the source-drain breakdown voltage of CMOS transistors.

Furthermore, regarding the parasitic bipolar transistor products β _N and β _P of the ultra-fine CMOS transistor based on the third embodiment, there was almost no difference from that of the second embodiment, and the latch-up phenomenon was negligible. .

Although the first to third embodiments have been described above, the effects obtained by these are obtained by improving the regions corresponding to the source and drain in the conventional structure, and are not achieved by increasing the concentration of the semiconductor substrate 1 to achieve high breakdown voltage. It is not a measure of change. Therefore, a decrease in mobility due to an increase in the concentration of the semiconductor substrate is not caused, and high-speed operation is not impaired.

In the present invention, since a high melting point metal or its silicide layer is formed on the source and drain,
Even ultra-fine CMOS transistors can maintain a low sheet resistance of several ohms per unit, ensuring high-speed operation.

In each of the first to third embodiments, the maximum impurity concentration of the source and drain diffusion layers is 1×
The case of 10 ¹⁷ cm ^-3 or more has been described, but this is based on the analysis results shown in FIG. 2, that is, the analysis results for a gate length of 0.1 μm. A value of 0.1 μm is the minimum gate length that can be achieved. Furthermore, if the present invention is applied below the above impurity concentration (1×10 ¹⁷ cm ^-3 ), as can be inferred from FIG. 3, an increase in substrate current and drain leakage current will be caused. Become.

Further, in each of the first to third embodiments, a platinum silicide (Pt.Si) layer was formed on the source/drain diffusion layer in a self-aligned manner, but this is just an example. Mo.W.Pd.N. instead of layer.
A high melting point metal such as Ti.Ta.Nb.Cr.Pr or a silicide film thereof can be used. Further, in each of the examples, a method using a high-temperature electric furnace was described as the short-time heat treatment, but this step can also be performed by other methods such as a lamp heating method, laser or electron beam irradiation method. Further, in each embodiment, the case where a P-conductivity type well is used has been described, but conversely, the present invention can also be applied to a CMOS transistor having a structure in which an N-conductivity type well is formed in a P-conductivity type semiconductor substrate. Can be applied.

〔Effect of the invention〕

As explained above, according to the present invention, 0.2 μm
Even with extremely short channel lengths, it can be operated with a normal 5V power supply and the latch-up phenomenon can be prevented, making it possible to realize ultra-fine CMOS transistors without sacrificing high-speed operation.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional structure diagram of a conventional CMOS transistor, Figs. 2 and 3 explain the principle of the present invention, and Fig. 4 shows analysis results regarding source-drain breakdown voltage and maximum substrate current. , FIGS. 5 and 6 show a first embodiment of the invention.
Cross-sectional diagram of CMOS transistor manufacturing process, No. 7
FIG. 8 shows a second embodiment of the present invention.
Cross-sectional diagram of CMOS transistor manufacturing process, No. 9
FIG. 10 shows a third embodiment of the present invention.
2 is a diagram showing a cross-sectional view of a CMOS transistor and an impurity concentration distribution in the depth direction. FIG. 1: Silicon substrate, 2: Well region, 3: Feed oxide film, 8: Gate oxide film, 9: Gate electrode, 12: Gate protection insulating film, 13: Silicon oxide deposited film, 4, 6: Source, 5, 7 :drain,
14: Platinum silicide layer, 10: Silicon oxide film, 15: TiW film, 11: Aluminum wiring.

Claims (1)

[Claims] 1 Boron is introduced into a P-type drain region of a P-channel MOS transistor with an impurity concentration of 10 ¹⁷ to 10 ¹⁹ cm ^-3 and arsenic is introduced and the impurity concentration is 10 ^{17 to 10 19 cm} -3.
A first step of forming an N-type drain region of an N-channel MOS transistor with an impurity concentration of 10 ¹⁹ cm ^-3 on a silicon semiconductor substrate, and forming a high melting point layer on the P-type drain region and on the N-type drain region. a second step of forming a metal; and a third step of forming a silicide layer of the refractory metal on the P-type drain region and the N-type drain region by heat-treating the refractory metal. and during the third step, the P channel
While a Schottky barrier is formed in the P-type drain region of the MOS transistor, a precipitated layer with an impurity concentration of 10 ¹⁸ to 10 ²⁰ cm ^-3 is formed directly under the silicide in the N-type drain region, which is about one order of magnitude higher than before the silicide is formed. The N
A method for manufacturing a complementary insulated gate field effect transistor, comprising forming an ohmic contact in the N-type drain region of a channel MOS transistor. 2 The above P channel MOS transistor and the above N
The channel length of a channel MOS transistor is
A method for manufacturing a complementary insulated gate field effect transistor according to claim 1, wherein the thickness is 0.5 μm or less. 3. The method of manufacturing a complementary insulated gate field effect transistor according to claim 1 or 2, wherein the deposited layer has a thickness of about 10 nm. 4. Each of the drain regions is formed adjacent to a gate electrode formed on the silicon semiconductor substrate with a gate insulating film interposed therebetween, and an insulating film formed on a side wall of the gate electrode. A method for manufacturing a complementary insulated gate field effect transistor according to any one of claims 1 to 3. 5. A complementary insulated gate electric field according to any one of claims 1 to 3, wherein a portion of each drain region is formed of a polycrystalline thin film or an amorphous thin film. Method of manufacturing effect transistors.