JPS6014355A - Debug device - Google Patents

Abstract

PURPOSE:To improve the debug processing efficiency for a specific module having plural lower modules by omitting the debug of lower modules and attaining the debug of only upper modules. CONSTITUTION:When a specific module of a program to be tested is debugged, the set address of a call instruction for lower modules is registered to a bit map memory 5. While the set address of a return instruction to upper modules is registered to a bit map memory 6. Then a real device 1 is operated and a real device CPU4 executes an address instruction coincident with the register data. Thus a reversible counter 9 is counted up and down when said address instruction is equal to a call instruction and to a return instruction respectively. In such a way, the operation of the CPU4 is stopped when the counter 9 is reset to its start point and switched to a CPU14 for execution of debug processing. With use of such a means, the debug is omitted for lower modules. This improves the debug processing efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to debugging for testing computer programs. Break point (Break Point) in the module of
We propose a new method for interrupting program progress by setting .

<Background of the Invention> In recent years, operating programs for computer systems have been structured into a series of programs by dividing them into a plurality of modules according to the content of work, etc., and connecting the modules hierarchically through call instructions.

Generally, debugging is carried out by progressing the program under test one instruction at a time, but in the case of this type of structured program, if a call instruction is set in the module being debugged, the debugging target or lower module will be transferred. Usually, a lower module often plays a component role of its upper module, and in such cases, debugging of the lower module is omitted and only the upper module is targeted for debugging.

However, at present, no effective method has been established for easily and quickly carrying out such abbreviation processing, which reduces the effectiveness of the depacking process by 2V.

<Objective of the Invention> The present invention provides a method for omitting debugging of a lower module for a specific module having a plurality of lower modules.
An object of the present invention is to provide a new depacking device that easily debugs and installs only the "-" module, thereby improving debugging processing efficiency.

<Configuration and Effects of the Invention> In order to achieve objective 1 above, in the present invention, an address where a call instruction to call a lower module is set for the registration means and a return instruction to return to the -1- module is set. For example, when the address of an executed instruction matches the registered data related to the call instruction setting address, when the counting means is incremented, or when it matches the registered data related to the return instruction setting address. , the counting means performs a town count, and when the count returns to the counting start point (3), this is set as a break point and the progress of the program is stopped by the stop control means.

According to the present invention, when debugging a specific module, even if the program progresses to a lower module, debugging of the lower module can be easily omitted, and the module The present invention achieves excellent effects such as being able to debug only the debugging process and improving debugging processing efficiency.

<Description of Embodiments> FIG. 1 shows an example of a circuit configuration in which a debugging device 2 of the present invention is connected to a machine 1 (hereinafter referred to as an actual machine) employing a computer system.

The actual device 1 includes a memory 3 in which a program to be tested is stored, and an actual CPU 4 (Cen.
tral Processing Uni[).

The program to be tested is constructed by hierarchically connecting a plurality of modules, and FIG. 2 shows an example of the structure of a program program (4) as a hierarchical diagram. Each block in FIG. 2 represents a module, and the topmost module P has three
modules P,, P2. P3 is combined, lower module P1 has a lower module "+1", and similarly lower module P2 has module P21!P2
21 P23 are connected to each other, and the lower module P22 has two lowest modules P22-1 . ,
P2□-2 are connected to each other. Each module with a ``1'' relationship has a call (
CALL ) instruction and a RETURN instruction set in the lower module, respectively, and are connected via the 31st)! In the example shown in J, the address b1. l)2. Lower module Pl+ in b3
The call instruction that calls the beginning of P2 + P3 also calls address 1) 11 of module P1 and module P
2 addresses h2+, ')22, 1)23, lower module P11 and module P2+ +
The call instruction that calls the beginning of P22 + P23 further calls the address of module P22 "'-' l b22-"
2, the lowest module "22-", T'22
A call instruction to call the beginning of -2 is set for each,
Also, excluding the lowest module P (the final address of each module a+1 a2+ "3) aII +a21 +
a22 + a231 a22-11 "22 2 has a return command to return to the -" module, respectively.

The illustrated debug device 2 has a pair of bit map memories 5 and 6 for individually registering the set address of the call instruction and the set address of the return instruction, each bit map memory 5 and 6. The output of gate circuit 7,
Count-up terminal C (J
and countdown terminal CD. For example, in the program examples shown in FIGS. 2 and 3,
When the module Pl is to be debugged, the lower module PI+ is called, and data "1" is written to the area of the bitmap memory 5 corresponding to the squall instruction setting at1/sbl+, and data "0" is written to the other areas. Set each.

Also, a take "1" is set in the area of the hitmap memory 6 corresponding to the return command setting address "all" to the upper module P, and data "0" is set in the other areas. As a result, when the call instruction at address b]1 is executed, the pin map memory 5 becomes logic "1".
The counter 9 inversely counts up by sending out the matching output. On the other hand, when the return instruction at address all is executed, the bitmap memory 6 sends out a matching output of logic "]j, and the reversible counter 9 counts down. This reversible counter 9 is normally preset to data "0". As a result, the reversible counter 9 starts counting with rOJ as the starting point, and when the count returns to the starting point as a result of the up-count and count-down operations, it outputs the break point detection signal 1 from the carry terminal CO. . A breakpoint is set by this detection signal i, the break control circuit is activated, and the actual CPU
4 to stop the program from proceeding.

In the figure, multiplexers 1, , and 12 are circuits that connect the actual CPU 4 and the CPU 1.4 of the debugging device 2 to the bitmap memories 5 and 6, respectively, and the timing control circuit 13 connects the gate circuit 7 to the bitmap memories 5 and 6, respectively.
, 8 is a circuit that controls the gate opening/closing operation of the gates. Also CI
'U14.14, decodes and executes the debugging program stored in the memory 15, and controls each iFt+ operation of the bitmap memories 5, 6, reversible counter 9, and multiplexers 1.1 and 1.2 via the control circuit 16. At the same time, it controls the operation of various input devices used for depacking processing, such as the display 17 and the key input device [418].

However, when depacking a specific module in the program under test, in steps 21 and 22 of FIG. The setting addresses of the return commands to be returned are registered in the bitmap memory 6, respectively. Next, in step 23, the reversible counter 9 is preset to, for example, data "0", and then in the next step 24, the multiplexer], ],
1. Switch 2 to the real CPU 4 side and run the real CPU 4. Then, when the real CPU 4 executes an instruction with an address that matches the registered data, if the instruction is a call instruction, the reversible counter 9 will be In the case of an up count, on the other hand, in the case of a return instruction, the reversible counter 9 counts down (step 25).As a result, when the contents of the reversible counter 9 return to the starting point, the reversible counter 9 outputs a break point detection signal i. , the determination in step 26 is °'
Y Ii S ” and the execution of the program by the actual CPU 4 is stopped (step 27). After that,
multiplexer 11.12 to CPU1 of debug device 2
4 side, the module program is advanced one instruction at a time, and debug processing is continued.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a debugging device according to the present invention, FIG. 2 is a hierarchical diagram showing an example of the program structure, FIG. 3 is a diagram explaining the program structure and addresses, and FIG. 4 is similar to FIG. 1. The operating element 1111+(of the circuit shown in FIG. 1) is flowchart 1.
Reversible counter 10...Break control circuit patent applicant Tateishi Electric Co., Ltd.

Claims (1)

[Claims] In a program configured by hierarchically connecting multiple modules via call instructions, register the address where the call instruction that calls the lower module is set and the address where the return instruction that returns to the upper module is set. a counting means that performs up-counting and down-counting operations based on the comparison result between the address of the executed instruction and each registered content; and execution of a program when the content of the counting means returns to the counting starting point. A debugging device comprising a stop control means for stopping the debugging device.