JPS60143024A - Follow-up comparison type a-d converter - Google Patents

Abstract

PURPOSE:To quicken the A/D converting speed while keeping the safety against noise by changing mutual connection of plural counters where total bit number is a data bit number D by means of a switch. CONSTITUTION:In throwing a switch SW31 to the position of contact (b) and switches SW32-3n to the position of contact (a) in a controller CT7 at first, only the counter 21 of the most significant digit is connected to a clock oscillator 6 and the other counters 22-2n are connected in cascade and connected to earth, then the counter 21 follows an input signal as to the high-order D/n bit. The required time is 2D</n>t. In throwing the SW31 to the position of contact (a) and the SW32 to the position of contact (b) in the CT7 next, and the SW33-3n are kept as before. Then the counters 21, 22 follow the input signal. The CT7 connects the counters 23-2n sequentially to the counters 21, 22 one by one and the connected counters are connected to an oscillator 6 so as to attain follow-up. The total required time of D-bit is 2D</n>.t.n.

Description

[Detailed description of the invention] The present invention relates to a follow-up comparison type A-D converter.

Conventionally, in my summer converter, which has a number of data bits, a counter with the same number of bits as data bits &D performs an operation that follows the input signal, so 2D counting is required, and the clock pulse period yt and A time of 2 D and t is required. For example, if l; JD'i16 and the total clock pulse frequency is IMHz, it will be 65556 microseconds.

- If a successive approximation type A-D converter is used, in the case of D bits, it will only take D, Q) ji counts or jQD-t time, which in the above example is 16 microseconds, resulting in high-speed conversion. However, if a single bit makes a mistake, it cannot be restored, and this counting error may be caused by noise, so it is inconvenient to be reliable.

In the present invention, a tracking comparison type A having safety against noise is provided.
- Its purpose was to increase the conversion speed in the D converter, and the data pinto II 1. D's tracking comparison type A
- switch means for changing the interconnection of the plurality of counters whose total number of bits is equal to the number of data points and the plurality of counters in the D converter; and a controller for operating the switch. First, the topmost counter performs an operation that follows the input signal, and then the lowermost counter performs an operation that follows the input signal. The main feature is that the counters are connected one by one, and each time the top counter and the lower counters connected to the top counter perform a follow-up operation.

Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

In the drawing, (1) is a D-A converter with the number of data bits, (2+) is the most significant counter with D/n (n: plural) bits, and (2tJ...(2nJ) is the sequentially lower D/A converter.
/ An n-bit counter, with clock input terminals U and D for up-counting and down-counting, respectively, and the counter (21)...(2n+
The clock pulse input terminals U and D of 1) are connected to the switch (3).
1) AN for up counting by (3n-+)
connected to the clock oscillator (6) via the D gate 14+ and the down-counting All ID gate (5);
Or the lower counter (22)...(2nJ) and the lower counter (22)...(2nJ)
A switch (Sn
) is connected to the clock oscillator (6) via the AND gate (X4) for up counting and the AND gate (5) for down counting. - Connected to ground. (71 is the switch (5,]...
(3nJ quick-closing control unit) A controller consisting of an OPU and other devices, which performs the following operations, (81U comparator, whose input terminal is connected to the input signal terminal (9), and the other input terminals are connected to the D-A converter. (1), and its output terminal was connected to the AND gate for up-counting (4) via the trench 7jNOT gate [lOJl: +51 VC of the AND gate for down-counting.

Note that a conductor switch or the like is used as the switch (3,) to (5nJ).

Next, its operation will be explained.

The controller 171 first connects one switch (52) to (5) to the fixed contact a side of the switch (3sJ"t).
It operates to close to the side. Thus, only the topmost counter (217) is connected to the clock oscillator (6).
The other counters (22) to (2n) are connected in cascade and one end is connected to ground, so that the topmost counter 1 (2+JU) follows the input signal by 1 for the upper D/rt bit and 7n. The time required for C is D/n, which is 2 -2t'''c.Next, the controller (7) host (7ch (3I) is set to the fixed/fixed contact aOJfJ, and the switch (3□) is set to all fixed contacts. The other switches C3s) to (5nJ vf-・unloading force) close the top counter (2,) and the next lower counter (22). ) is connected to the clock oscillator (6), so the counters (21) and (22) or the upper two
One operation following the input signal is performed for D/'n bits. This required time is 2 D/n since the tracking operation has already been completed for the most significant D/n bit VC.
・It is t. After this, the controller (7) sequentially changes the counters (23) to (2n) one by one to the counters (2,) (
22), and the counter (2,) (22J (2 leads...) is connected to the clock oscillator (6), so 3D/n
, . . . n All follow-up operations are performed for D/n bits. The time required for each D/n is 2.t'''C, and the time required for all D focusing is 2D/''-'t,n.

Assuming that it is the same as the conventional example described above (D=16 bits, clock pulse total IMHz, and n=4), the required time is 64 microseconds, which is extremely short compared to 65,536 seconds in the conventional example.

In the above embodiment, n counters (2,) to (2n
Although all JFjf are D/n bits, counters with different numbers of bits may be used.

In this way, according to the present invention 1!11, n is a tracking comparison type A-D converter with a number of data bits, a plurality of counters whose total number of bits is the number of data bits D'''C, and a plurality of counters whose total number of bits is the number of data bits D'''C; a switch means for changing the interconnection of the counters; and a controller for operating the switch means;
First, the topmost counter performs an operation that follows the input signal, and then successively connects the lower O counters one by one to the topmost counter, and each time connects the topmost counter to this one. The lower count is a follow-up operation lol? 'r', it has the effect of increasing the fc and tt conversion speed while maintaining safety against noise that the follow-up comparison type has.

[Brief explanation of the drawing]

The drawing shows a block IJ k 71 of one embodiment of the present invention.
'f. (1)...D-A converter (21) to (2n)...Counter (31) to (rogen...switch +a (51...A N D gate (6) ... Clock oscillator +71 ... Controller (8) ... Comparator (9) ... Input signal terminal 2 people procedure amendment form 111' sum 54 December 17 Mr. Commissioner of the Japan Patent Office 1, Indication of the case Patent Application No. 248484 of 1982, 2 Name of the invention Follow-up comparison type A-D converter 3, Relationship with the person making the amendment case In particular, 1 application filed by Tokyo Sokki Co., Ltd. Research Institute 4, Agent 5, Amendment Order No. 114” (Volunteer) ++/’Japanese Year Month 1”

Claims (1)

[Claims] In a data bit @, D follow-up comparison type A-D converter, a plurality of counters whose total number of bits is the data bit @D and the plurality of counters are interconnected to be changed. A switch means and a controller for fully operating the switch are provided. First, the highest counter follows the input signal and performs all fc operations, and then the lower counters are connected one by one to the highest counter. , a follow-up comparison type A-D converter characterized in that the NVC-connected NVC lower counters perform a follow-up operation each time.