JPS60140595A - Semiconductor input circuit - Google Patents

Abstract

PURPOSE:To allow the titled circuit to execute stable and high-speed operation for an input signal by providing a circuit which controls the second control signal to keep the electric potential high level for the prescribed time when the first control signal changes from the low level to the high level. CONSTITUTION:A latch signal phi10 is connected to the gate of a transistor Q1 which adds an input signal and a control signal phi1 is connected to the drain of a charge transistor Q30 of a dynamic circuit. When the control signal phi1 is activated and it rises from the low level to the high level, the latch signal phi10 rises furthermore from the initial high electric potential. At the same time, the input impedance of the input transistor Q1 decreases, the input is transmitted to the gate of a transistor Q3 at a high speed, the transistor Q3 generates the input signal and the inversion auxiliary signal as the output voltage at a high speed when the input signal changes from the high level to the low level, and vice versa. As a result, a data input circuit with stability and a high speed can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor input circuit that is used in a dynamic memory or the like and writes data at high speed.

The present invention is particularly applicable to MOS (Metal Oxide 8
i1icon )) It is assumed that it is composed of transistors.

Note that although an N-channel type MO8 (N-MOS) transistor is explained here, a P-channel type M
This can be similarly achieved using an O8 (P-MOS) transistor.

In general, dynamic type M using MOS transistors
OS memory has become the mainstream semiconductor memory, achieving high density and high speed through short channels, and the basic operations of this memory include fill operation and read operation. In order to speed up this read operation, various sense amplifier circuits have been devised and contribute to speeding up the read operation, but it is also necessary to speed up the write operation.

(Prior Art) FIG. 1 shows a data input circuit used in a conventional dynamic memory. In the figure, MOS transistor Q
+, Qs, Qs-Qs constitute an inverter type dynamic circuit, and input signal DATA from terminal 1
This circuit outputs the positive and complementary signals of the input signal to contacts Nl and N2 while amplifying the level of IN. This input circuit is driven by a control signal φhφ2 as an activation signal supplied by a start signal and a latch signal φ3 generated by this signal φ1.

FIG. 2 is a waveform diagram illustrating the operation of FIG. 1. Normally, a TTL level input signal is supplied to a dynamic memory to perform a write operation. That is,
The input signal is amplified, a positive signal and a complementary signal are generated at the same time, and the signals are transmitted to the inside of the memory, and the sense amplifier for reading the digit line is driven to provide a storage signal to the memory cell.

In order to perform this write operation at high speed, it is necessary to drive the data input circuit, which is the first input stage, at high speed.

FIG. 3 is a circuit diagram of a portion of FIG. 1 where the latch signal φ3 is formed from the control signal φ1 and its inverted signal jl. In the figure, Q21 to Qly are MOS transistors, c
ll c, is a capacitor, transistor Q'+t
+Qgg and capacitor CI are bootstrap circuit, transistor (hs -Q47 and capacitor C2
constitutes a delay circuit (DL). The operation of this circuit is as follows: First, when the control signal φl is at a low level, the lease (N4) of the transistor Qha is not at the power supply (Vcc) level, and the DL times the signal at the contact N5 of the delay circuit is at a low level. Since the transistor Qhs controlled by the double signal is turned off, the level of the contact N6, that is, the latch signal φ
3 is the power supply Vcc to Vt ((drain-source voltage)
It has become a high level that has only fallen. Next, the control signal φ1
When becomes high level at time t1, contact N4 becomes low level and transistor Q24 turns off, but output contact N6 becomes high level 7 because transistor h5 is also off.
0-Taing Repel is retained. Here, contact N, oA
, the L signal gradually rises to a high level due to the load on the delay circuit, but the time t when it exceeds the vte level of the transistor Q25
, transistor Q25 turns on and drops the level (φ3) of output contact N6 to ground. Is this DL signal level V? The value of the capacitor C2 may be determined so that the time required to latch the input signal is set as the time required to latch the input signal.

In this data input circuit, 1) it is necessary to set the input signal earlier than the data input circuit activation signal φ1;

In other words, since the input signal is a start signal, it means that the activation signal φl is delayed by this amount, which is contradictory to speeding up the write operation, and 2) for speeding up. Input MO8) It is necessary to increase the size of the transistor Q1 to lower the input impedance, which causes the problem of increasing the area of the circuit and increasing the input capacitance.

(Object of the Invention) An object of the present invention is to solve these problems and provide a semiconductor input circuit that operates stably and at high speed in response to input signals.

(Configuration of the Invention) The configuration of the present invention includes a load transistor whose drain or gate is supplied with a first control signal for activating the transistor, and an inverter transistor whose drain is connected to the source of the load transistor and whose source is grounded. ,
A source or drain is connected to the gate of this inverter transistor, an input signal is supplied to the drain or source, and a second control signal synchronized with the first control signal is supplied to the gate.
In the semiconductor input circuit having an inverter-type dynamic circuit including a decoupling transistor to which a control signal is supplied, when the first control signal changes from a low level to a high level, the second control signal changes for a predetermined period of time. The present invention is characterized in that the impedance of the decoupling transistor is reduced by providing a circuit that controls the potential level from an initial high level to a higher potential level during the period of time.

(Embodiment) FIG. 4 is a circuit diagram of an embodiment of the present invention, FIG. 5 is a circuit diagram of the latch signal forming section 10' of FIG. 4, and FIG.
FIG. 3 is a waveform chart showing the operation shown in FIG. This embodiment differs from the conventional circuit (FIG. 1) in that the decoupling transistor Q
Although the load portions other than the load transistor Q3 are simplified and shown using only the load transistor Qso, the circuit is equivalent to that shown in FIG.
The present invention is characterized in that the latch signal φ10 generated by the signal forming section 10' lowers the twin pedance of the decoupling transistor Qs.

Transistor Ql to which input signal (DATA) is applied
A latch signal φ10 is supplied to the gate of the inverter-type dynamic circuit, and a control signal φl is connected to the drain of the load transistor Qso of the inverter type dynamic circuit.

First, it is assumed that this control signal, that is, the activation signal φl is activated and rises from a low level to a high level. When the input data changes its level in synchronization with this signal φ1, the latch signal φto reaches a potential ■2 which is further increased from the initial high potential v1 (Fig. 6). Therefore, this activation signal φ1 is activated. At the same time, the input impedance of the input transistor Ql decreases, and in synchronization with the start of outputting the output signal, which is a complementary signal to the input signal, to the contact NIG, the input impedance of the input transistor Ql decreases, and the input signal is transferred to the gate of the transistor Q3 at a higher speed. Communicate to. Therefore, when the input signal changes from a high level to a low level or from a low level to a high level, the transistor Q3 can generate an input signal and an inverted complementary signal as an output voltage at a higher speed. .

Such a latch signal φ10 is formed, for example, in the circuit of the fifth section. In this circuit, Q s l~Q3
9 is a MOS) transistor, 03 to Cs are capacitors, and the delay circuit section of transistors Q25 to Q27 is the third transistor.
It is similar to the figure. First, when the control signal φl is at a low level,
The complementary signal <6t of this signal φl is at a resoundingly high level, 1
Is transistor Qaa in an off state? Transistor Q3? Since it is in the on state, the contact N15rrua is at the ground level. At this time, the level of the output contact N14, that is, the latch signal φ1°, is different from the level of the power supply Vcc because the transistor Q25 is in the off state and is the output of a putt strap type inverter. Further, a charge of +Vcc is held between the contacts N, . . . , N, and 4 by the capacitor C5.

When the signal φ1 becomes high level, the contact N111 changes from the ground level to the power supply level. Further, the delay of the transistor QshQS2 + Qss + Q34 can be adjusted so that the transistor Qste is turned off after the capacitor C3 is charged up. Therefore, the output contact N14 (φ10) rises from the initial power level V+ (Vcc) to twice the initial power level V, (2Vcc) via the capacitor C5. This output contact N
The level of 14 is such that when the delay time required for the input latch is provided by the capacitor C2, that is, the contact Ns becomes high level and the transistor Qzs is turned off, it will not fall to the ground level. As shown by the latch signal φ10 in FIG. 6, a thick lifetime waveform with a rising level can be output.

In this embodiment, the control signal φ10 can supply a signal that increases from the initial high potential V l (Vcc) to v2 (approximately 2 Vcc) only when the input signal changes; It is also possible to use a control signal that always increases from the initial high potential v1 to reach (2) in synchronization with the change in voltage.

(Effects of the Invention) According to the present invention, in the input-side inverter type dynamic circuit of the data input circuit, the latch signal φ1o changes the data input signal to a signal complementary to its initial level at the same time as the control signal φ1 is activated. When the input signal changes, the initial high level is raised to a higher potential, and the change in the input signal is quickly transmitted to the MOS (MOS) transistor Q3, so the output signals Nl and N2 of the 7 lip-flop are quickly determined and high-speed operation is possible. is possible. As a result, a high speed and stable data input circuit can be obtained. Furthermore, since the input signal can be transmitted to the inverter transistor at high speed, the time required to set the input signal relative to the start signal can also be minimized.

As explained above, according to the present invention, it is possible to transmit an input signal to the gate of an inverter transistor at high speed, and the input signal can be transmitted to the gate of an inverter transistor at high speed. The speed of the data type circuit itself can be increased, and it can be applied to various circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an example of an input circuit used in a conventional dynamic memory, FIG. 2 is a waveform diagram showing the operation timing of FIG. 1, and FIG. 3 is a circuit diagram of the latch signal forming section of FIG. 1. FIG. 4 is a circuit diagram showing the basic configuration of an embodiment of the present invention;
FIG. 5 is a circuit diagram of the latch signal forming section of FIG. 4, and FIG. 6 is a waveform diagram showing the operation timing of FIGS. 4 and 5. In the figure, 1... data input terminal, 2...
...Reference signal input terminal, 10.11...Latch signal forming section, c, ~cs""" capacitor, Qt
-Qts + Qtt = (h71Qsr~Qse・
・Mark ・MOS transistor, φ1. φ2・・・・・・
・Control signal, φ3. φ10: Group latch signal. 11 ÷ 2nd figure■ m-Uo rule 7G concave

Claims (1)

[Claims] A load transistor whose drain or gate is supplied with a first control signal for activating the transistor, an impark transistor whose source is connected to the drain and whose source is grounded, and a source or drain which is connected to the gate of the inverter transistor. A semiconductor input circuit having an inverter-type dynamic circuit including a decoupling transistor to which a decoupling transistor is connected, a drain or source is supplied with an input signal, and a gate is supplied with a second control signal synchronized with the first control signal,
When the first control signal changes from a low level to a high level, the second control signal is controlled from an initial high level to a higher potential level for a predetermined period of time. A semiconductor input circuit characterized by lowering the impedance of the ring transistor◇