JPH0237635B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor input circuit that is used in a dynamic memory or the like and writes data at high speed.

The present invention is particularly applicable to MOS (Metal Oxide) field effect transistors among insulated gate field effect transistors suitable for IC implementation.
It is assumed that it is composed of (Silicon) transistors.
Note that N-channel MOS (N-MOS) is used here.
Although a transistor is described, it can be similarly realized using a P-channel MOS (P-MOS) transistor.

In general, dynamic MOS memory using MOS transistors has become the mainstream semiconductor memory because it achieves higher density and higher speed through shorter channels, but the basic operations of this memory are write and read operations. There is. In order to speed up this read operation, various sense amplifier circuits have been devised and contribute to speeding up the read operation.
Similarly, write operations must be made faster.

(Prior Art) FIG. 1 shows a data input circuit used in a conventional dynamic memory. In the figure, MOS transistors Q ₁ , Q ₃ , Q ₅ , and Q ₈ constitute an inverter type dynamic circuit, which amplifies the level of the input signal DATA IN from terminal 1 while converting the positive and complementary signals of the input signal. This is a circuit that outputs to contacts N1 and N2. This input circuit receives the control signals φ ₁ , φ ₂ as activation signals supplied by the start signal.
and the latch signal φ ₃ created by this signal φ ₁
It is driven by

FIG. 2 is a waveform diagram illustrating the operation of FIG. 1. Normally, a TTL level input signal is supplied to a dynamic memory to perform a write operation. That is, the input signal is amplified, a positive signal and a complementary signal are generated at the same time, and the signals are transmitted to the inside of the memory, and the sense amplifier for reading the digit line is driven to provide a storage signal to the memory cell. In order to perform this write operation at high speed, it is necessary to drive the data input circuit, which is the first input stage, at high speed.

FIG. 3 is a circuit diagram of a portion of FIG. 1 in which the latch signal φ ₃ is formed from the control signal φ ₁ and its inverted signal ₁ . In the figure, Q ₂₁ to _{Q 27} are MOS transistors, C ₁ and C ₂ are capacitors, transistors Q ₂₁ and Q ₂₂ and capacitor C ₁ are a bootstrap circuit, and transistors Q ₂₅ to _{Q 27} and capacitor C ₂ are delay circuits. It constitutes the circuit (DL).
The operation of this circuit is as follows: First, when the control signal φ ₁ is at a low level, the source (N ₄ ) of the transistor Q ₂₂ becomes the power supply (Vcc) level, and the contact point of the delay circuit
Since the DL signal of N ₅ is low level and the transistor Q ₂₅ controlled by this DL signal is turned off,
The level of contact N ₆ , that is, the latch signal φ ₃ is the power supply
It is at a high level that is lower than Vcc by V _T (drain-source voltage). Next, when the control signal φ ₁ becomes high level at the remaining time t ₁ , the contact N ₄ becomes low level, and the transistor Q ₂₄ turns off.
The output contact N ₆ maintains a high floating level because the transistor Q ₂₅ is also off. Here, the DL signal at contact _N5 gradually rises to a high level due to the load of the delay circuit, but the V _T of transistor _Q25
When the time t ₂ exceeds the level, the transistor Q ₂₅
turns on and drops the level (φ ₃ ) of output contact N ₆ to ground. The value of the capacitor _C2 may be determined so as to set the time required for the DL signal level to exceed V _T as the time required to latch the input signal.

In this data input circuit, (1) it is necessary to set the input signal earlier than the data input circuit activation signal _φ1 . In other words, since the input signal is a start signal, this means that the activation signal φ ₁ must be made later than this, which is contradictory to speeding up the write operation, and (2) input
It is necessary to increase the size of the MOS transistor _Q1 to lower the input impedance, which causes the problem of increasing the area of the circuit and increasing the input capacitance.

(Object of the invention) The object of the invention is to solve such problems,
An object of the present invention is to provide a semiconductor input circuit that operates stably and at high speed in response to input signals.

(Configuration of the Invention) The configuration of the present invention includes a load transistor whose drain or gate is supplied with a first control signal for activating the transistor, and an inverter transistor whose drain is connected to the source of the load transistor and whose source is grounded. , a source or drain is connected to the gate of this inverter transistor, an input signal is supplied to the drain or source, and a second control signal synchronized with the first control signal is supplied to the gate.
In the semiconductor input circuit having an inverter-type dynamic circuit including a decoupling transistor to which a control signal is supplied, when the first control signal changes from a low level to a high level, the second control signal changes to a predetermined level. The present invention is characterized in that the impedance of the decoupling transistor is reduced by providing a circuit that is controlled from an initial high level to a higher potential level for a period of time.

(Embodiment) Fig. 4 is a circuit diagram of an embodiment of the present invention, Fig. 5 is a circuit diagram of the latch signal forming section 10' of Fig. 4, and Fig. 6 shows the operation of Figs. 4 and 5. FIG. This embodiment differs from the conventional circuit (Fig. 1) in that the load portions other than the decoupling transistor Q ₁ and the inverter transistor Q ₃ are replaced by load transistors.
Although it is simplified and shown using only Q ₃₀ , it is equivalent to Figure 1. The circuit of this embodiment is characterized in that the latch signal _φ10 generated by the latch signal forming section 10' lowers the impedance of the decoupling transistor _Q1 .

A latch signal _φ10 is supplied to the gate of the transistor _Q1 to which the input signal (DATA) is applied, and the load transistor of the inverter type dynamic circuit is
The control signal _φ1 is connected to the drain of _Q30 .
First, it is assumed that this control signal, that is, the activation signal φ ₁ is activated and rises from a low level to a high level. When the input data changes its level in synchronization with this signal φ ₁ , the latch signal φ ₁₀ reaches a potential V2 which is further increased from the initial high potential V1 (FIG. 6). Therefore, at the same time as this activation signal φ ₁ is activated, that is, in synchronization with the start of outputting the output signal, which is a complementary signal to the input signal, to contact N ₁₀ , the input impedance of the input transistor Q 1 decreases, and the input impedance of the input transistor Q ₁ decreases. Transistor signals faster
Transmit to gate of Q ₃ . Therefore, the transistor
_Q3 can generate an input signal and an inverted complementary signal as an output voltage more quickly when the input signal changes from a high level to a low level or from a low level to a high level.

Such a latch signal _φ10 is formed, for example, by the circuit shown in FIG. In this circuit, Q _31
-Q39 are MOS transistors, _C3 - _C5 are capacitors, and the delay circuit portion of transistors _Q25 - _Q27 is the same as that shown in FIG. First, when the control signal φ ₁ is at a low level, the complementary signal ₁ of this signal φ ₁ is naturally at a high level, and since the transistor Q ₃₆ is off and the transistor Q ₃₇ is on, the contact N ₁₃ is at the ground level. ing. At this time, the level of the output contact _N14 , that is, the latch signal _φ10 , is at the level of the power supply Vcc because the transistor _Q25 is in the off state and serves as the output of the bootstrap type inverter. In addition, capacitor C ₅ connects contacts N ₁₃ and N ₁₄
+Vcc charge is maintained during this period.

Here, when the signal φ ₁ becomes high level, the contact N ₁₃ changes from the ground level to the power supply level. In addition, transistors Q ₃₁ , Q ₃₂ , Q ₃₃ , and Q ₃₄ are connected to capacitor C ₃
The delay can be adjusted to turn off transistor _Q37 after charging up. Therefore, the output contact N ₁₄ (φ ₁₀ ) rises from the initial power level V ₁ (Vcc) to twice the initial power level V ₂ (2Vcc) via the capacitor C ₅ . The level of this output contact N ₁₄ is set to ground after the necessary delay time for the input latch is provided by capacitor C ₂ , i.e. when contact N ₅ goes high and transistor Q ₂₅ is turned on. As a result, a waveform with a large rising level can be output as shown by the latch signal _φ10 in FIG.

In this embodiment, the control signal _φ10 changes from the initial high potential V1 (Vcc) to V only when the input signal changes.
2 (approximately 2Vcc), but the control signal must always rise from the initial high potential V1 to V2 in synchronization with the activation of the activation signal _φ1 . I don't mind.

(Effects of the Invention) According to the present invention, in the input-side inverter-type dynamic circuit of the data input circuit, the latch signal _φ10 is activated at the same time as the control signal _φ1 is activated, and the data input signal is a complementary signal to its initial level. When the flip-flop changes to , the potential is raised to a higher potential than the initial high level, and the change in the input signal is quickly transmitted to the MOS transistor _Q3 , so the output signals N1 and N2 of the flip-flop are quickly determined and high-speed operation is possible. is possible. As a result, a high speed and stable data input circuit can be obtained. Furthermore, since the input signal can be transmitted to the inverter transistor at high speed, the time required to set the input signal relative to the start signal can also be minimized.

As explained above, according to the present invention, it is possible to transmit an input signal to the gate of an inverter transistor at high speed, and the speed of the inverter type circuit itself can be increased, making it possible to apply it to various circuits. becomes.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an example of an input circuit used in a conventional dynamic memory, Figure 2 is a waveform diagram showing the operation timing of Figure 1, and Figure 3 is a circuit diagram of the latch signal forming section of Figure 1. , FIG. 4 is a circuit diagram showing the basic configuration of an embodiment of the present invention, FIG. 5 is a circuit diagram of the latch signal forming section of FIG. 4, and FIG.
FIG. 4 is a waveform diagram showing the operation timing of the figure. In the figure, 1...data input terminal, 2...reference signal input terminal, 10, 11...latch signal forming section,
_C1 to _C5 ...Capacitor, _Q1 to _Q13 , _Q21 to _Q27 , _Q31
~Q ₃₉ ...MOS transistor, _φ1 , _φ2 ...control signal,
_φ3 , _φ10 ...Latch signals.

Claims (1)

[Claims] 1. A load transistor whose drain or gate is supplied with a first control signal for activating the transistor, an inverter transistor whose source is connected to the drain and whose source is grounded, and whose source or drain is connected to the gate of the inverter transistor. A semiconductor input circuit having an inverter-type dynamic circuit including a decoupling transistor to which a decoupling transistor is connected, a drain or source is supplied with an input signal, and a gate is supplied with a second control signal synchronized with the first control signal, When the first control signal changes from a low level to a high level, the second control signal is controlled from an initial high level to a higher potential level for a predetermined period of time. A semiconductor input circuit characterized by reducing the impedance of a transistor.