JPS60137131A - Lock detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a lock detection signal securely by providing a filter function circuit which inputs the pulse output of a phase comparing circuit and a counter function circuit which inputs the output of the filter function circuit. CONSTITUTION:When there is a phase difference in falling between pulses of a reference signal (8e) and a comparison signal (f), a phase difference output signal (g) is an L-level pulse corresponding to the phase difference. This signal (g) passes through a filter circuit 22 to generate a filter output signal (h), which resets a counter circuit 23 while a lock signal (i) is at a level L. The circuit 23 generates an H-level clock output signal (i) by comparison by a phase comparing circuit 21 at every fall of the signal (e) only when the phase difference becomes small enough not to pass the signal through the circuit 22 or when there is no position difference in specific time t3 from the ceasing of the phase difference signal, thereby detecting a clock state.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to PLL (Phase Locked)
Loop) lock detection circuit.

Configuration of the conventional example and its problems As shown in FIG. 1, the conventional lock detection circuit has a position A;
The phase comparison circuit 1 has two input terminals 2 and 3 for a reference signal and a comparison signal, and the cathode side of a diode 5 is connected to the output terminal 4 of the phase comparison circuit 1, and the anode side of the diode 5 is connected to the output terminal 4 of the phase comparison circuit 1. ] is connected to a capacitor 6 which is grounded at one end and a resistor 7 which is connected to a power supply at the other end, and this anode side is used as a lock output terminal 8.

FIG. 2 shows an operational quimming chart of the conventional lock detection circuit. 2L! :b is position A゛11 comparison circuit 2
A signal that enters two input terminals, each of which is a reference signal.

It is a comparison signal. C is the signal/waveform of the output terminal of the phase ratio 1.0 circuit, and d is the output waveform of the lock output terminal.

Now, when the phase of the comparison signal 1i'j is leading or lagging with respect to the signal B, which is the input signal 7 of the phase ratio 1-bit circuit, the output signal C of the phase comparison circuit is Outputs "L" level/V according to the phase difference. At this time, the charging portion of the capacitor 6 is discharged through the diode 5, and the lock output (M) becomes the "L" level. On the other hand, the two human power (1y+'
-, ,, a When the phases at the falling edge of 1b match, the output signal C of the position a comparator circuit reaches the level C'H', and the capacitor 6 is charged through the resistor 7, 4c, The lock output signal d was at the "H" level, and PLL system lock detection was being performed.

In the case of this circuit, a slight difference of 4'f'l between the reference signal and the comparison signal due to a minute leakage of the PLL thread causes a 4'f'l difference.
With the narrow "L" level output pulse of the S1 comparator circuit output signal, the capacitor's load is released,
In addition to the disadvantage that the lock output signal does not reach the ``H'' level, there is also the problem that it is difficult to integrate into a single-chip IC because it includes a capacitor.

1 purpose of invention The present invention solves the problems of the prior art described above.

Phase ratio i1K due to minute flow of PLL system
It is an object of the present invention to eliminate the narrow "L"level/" output pulse of the 17"l pedal output, generate a stable lock output signal, and provide a tasenoku detection circuit suitable for 1-tread C.

Structure of the Invention To summarize, the present invention inputs two types of waveform signals, outputs a pulse corresponding to the signal I phase difference based on the phase ratio of the two types of nine waveform signals, and filters the PALNU output. The output of the filter circuit is input to a circuit with a counting function. Narrow output pulses are removed and a lock detection signal is reliably obtained.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows the configuration of a lock detection circuit according to an embodiment of the present invention.
, a filter circuit 22 and a counter circuit 23. The phase comparator circuit 21 compares the two positions at the falling edge of the human power, Iζ1), and responds to the value A″lli'5.
Reference signal input terminal 2 that outputs L” level pulses
4, has a comparison signal input terminal 26 and a phase difference output terminal 26. The phase difference output terminal 26 is connected to an input terminal 27 of a fill circuit 22 configured by a so-called inverter chain in which an odd number of stages of impars are connected in series. This filter circuit 22 is configured with an odd number of impark stages so as to be difficult to respond to the falling edge of the input pulse to the input terminal 27, so that it cannot pass through a narrow varnu. Output of fill circuit 22 ☆II,
The i child 28 is connected to the counter circuit 23. Reference numerals 29 to 31 are D-type flip-flops (referred to as D-F and F) which are examples of resent terminals, and 32 is a locking J terminal. More specifically, the output terminal 28 of the fill circuit 22 is D
- Connected to each recessor 1 to @ child of FFs 29 to 31. The data input terminals of D-F and F29 are connected to the power supply, and the output terminal Q is connected to the data input terminal of the next D-F and F30. Connect to the data input terminal of next D-F, F31,
The output terminal Q of -F.F31 is the lock output terminal 32. The tarlock input terminals C of the D-Fs 29 to 31 are commonly connected to the reference signal input terminal 24 of the phase comparator circuit 21.

Next, the operation of the embodiment of the present invention will be explained with reference to the timing chart of FIG. e is the input signal of the reference signal input terminal 24 that is input to the phase comparison circuit 21, f is the comparison signal that is input to the comparison signal input terminal 25 of the phase comparison circuit 21, and q is the position i ζ [1 comparison Circuit 210 phase difference output terminal 26
0 is the output signal of the filter circuit 22, and 1 is the output of the counter circuit 23 and the signal of the lock output terminal 32, that is, the lock output signal. Seven.

Position F' at the falling edge of each parnu of the reference signal e and the comparison signal f
1. When there is a difference l, the phase difference output signal q generates an "L" level pulse corresponding to the phase difference. This signal q passes through the fill circuit 22, becomes a fill output signal, resets the counter circuit 23, and becomes the lock output signal 1 (rJ, "L" level. In other words, the fill circuit output signal becomes While this occurs, the lock output signal 1 remains at the "L" level.

The fill circuit 22 has a pulse width t of the person's J signal q,
and the pulse reflex width t2 of the output signal, (t, -
12),>.

It has this characteristic. Therefore, a phase difference signal with a slight pulp width, such as a phase difference caused by leakage of the PLL yarn, cannot pass through the fill circuit 22 and is removed.

The counting circuit 23 compares the reference signal e every time the reference signal e falls in the phase comparison circuit 21, and determines whether the phase difference signal becomes narrow enough to not pass through the fill circuit 22, or within a specified time period t3 after the phase difference signal disappears. , only when there is no phase difference, the lock output signal i becomes 'H', and the lock state is detected.

Alternatively, the counting circuit 23 may be replaced with a delay circuit having an appropriate counting function.

In this case, the delay circuit is defined as t3 in Figure 4, after the Pallesi disappears,
If the predetermined signal can be obtained after the elapse of the time indicated by J2.

Further, the count circuit 23 performs appropriate pulp omission detection 1.
1] You can also change to 11 on the j path. In this case, the PALNU deletion detection circuit may be any circuit that responds and generates a predetermined signal after a specified amount has been stored after the pulse output from the fill circuit 22 disappears. has also been realized, and this is also one of the circuits that has a counting function.

Effect of the invention According to the present invention, the following effects can be obtained.

(2) A circuit with a fill function removes narrow phase difference pulses and maintains stable lock state detection even in the presence of a slight phase difference due to PLL system leakage.

(4) 4'tli can be achieved using circuits such as inverters and DFFs that are suitable for IC implementation, and can be easily integrated into one chip.

■ Pulling the PLL system into the locked state 'L'i1'l
Even when the overshoe 1-4 is generated, the lock detection output is not generated until the lock state is stabilized.

In this way, the present invention realizes a stable and reliable lock detection circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a conventional lock detection circuit, FIG. 2I is a timing diagram 1-1 of a conventional lock detection circuit, FIG. This is an operation timing diagram 1- in one embodiment. 21--Phase ratio 1 bit circuit, 22--Filter circuit based on impark, 23--Count circuit,
29 to 31...I) -F, F Name of agent Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 dj 22: ; shi 2--1-11111

Claims (2)

[Claims] (1) A phase comparison circuit that inputs three signals and generates a pulse according to the phase difference between the two signals through phase comparison, a filter function circuit that inputs the pulse output of the phase comparison circuit, and a filter function circuit. A lock detection circuit equipped with a counter function circuit that inputs the output from. (2) The lock detection circuit according to claim 1, wherein the fill function circuit is constituted by an odd number of inverter stages connected in series.