JPS60136362A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60136362A JPS60136362A JP58244048A JP24404883A JPS60136362A JP S60136362 A JPS60136362 A JP S60136362A JP 58244048 A JP58244048 A JP 58244048A JP 24404883 A JP24404883 A JP 24404883A JP S60136362 A JPS60136362 A JP S60136362A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- diffusion layer
- type diffusion
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 abstract description 27
- 238000002955 isolation Methods 0.000 abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 54
- 239000003990 capacitor Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0777—Vertical bipolar transistor in combination with capacitors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特に微細化構造をもつ半導体集積
回路装置における容量形成技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a capacitance formation technique in a semiconductor device, particularly a semiconductor integrated circuit device having a miniaturized structure.
バイポーラ形ＩＣ，ＬＳＩ等の半導体集積回路装置の高
集積化がすすみ、トランジスタなどの半導体素子の微細
化とともにこれらを相互に分離するアイソレージ９ン部
栴造も微細化の傾向にある。BACKGROUND ART As semiconductor integrated circuit devices such as bipolar ICs and LSIs become more highly integrated, semiconductor elements such as transistors become smaller, and the isolation circuits that separate them from each other also tend to become smaller.
上記回路の一部を構成する容量素子は、小型化が困難で
あるため容量の占める面積がチップ面積に対して相対的
に増大化していることが問題となることが本発明者によ
ってあきらかとされた。The inventor has found that the problem is that the area occupied by the capacitor increases relative to the chip area because it is difficult to miniaturize the capacitive element that forms part of the above circuit. Ta.
ところで１本発明者は上記の半導体素子とアイソレージ
覆ン部の微細化技術として、下記の技術を開発した。す
なわち、エピタキシャルｎ型中４体層の表面に素子を囲
むように溝を掘り、溝にそって溝の直下にｐ型拡散層を
形成してｐ型基板との間を接続することによりアイソレ
ージ１ン部を形成した。それにより、アイソレーション
部の面積を微細にした。さらに上記溝により囲まれｆｃ
ｎ型半型体導体層レクタとするバイポーラｎｐｎトラン
ジスタを形成し、上記溝のすくなくとも一部にｎ型拡散
層を形成しＣｎ型半導体層直下のｎ＋型坤込層に接触さ
せコレクタ取出し部とする技術である。By the way, the present inventor has developed the following technology as a technology for miniaturizing the above-mentioned semiconductor element and isolation covering portion. That is, a groove is dug in the surface of the epitaxial n-type medium 4-layer to surround the element, and a p-type diffusion layer is formed along the groove and directly under the groove to connect it to the p-type substrate. The inner part was formed. As a result, the area of the isolation section was made smaller. Furthermore, surrounded by the above groove, fc
A bipolar npn transistor is formed as an n-type semi-conductor conductor layer, and an n-type diffusion layer is formed in at least a part of the groove to contact the n+ type embedded layer directly under the Cn-type semiconductor layer to serve as a collector extraction part. It's technology.
これにより、アイソレーション部の微細化と、さらには
、素子の微細化をも達成できる様になつ飢
しかし、かかる技術においても容ｉ素子のチップ面積に
しめる割合は大きくなり、チップサイズの小型化が防げ
られるという問題点があることが本発明者によりあきら
かとされた。As a result, it becomes possible to achieve miniaturization of the isolation section and further miniaturization of the element.However, even with this technology, the proportion of the chip area of the capacitor element becomes large, making it difficult to miniaturize the chip size. The inventors have found that there are problems that can be prevented.
本発明は上記したアイソレーション部を容量として利用
するものである。The present invention utilizes the above-described isolation section as a capacitor.
〔発明の目的］
本発明の目的とするところは、半導体集積回路装置にお
いて、チップサイズの小型化を損うことなく容ｉｔを装
置内に組込むことのできる構造を提供することにある。[Object of the Invention] An object of the present invention is to provide a structure in which a capacitor can be incorporated into a semiconductor integrated circuit device without compromising miniaturization of the chip size.
本願において開示される発明のうち代表的なものの概要
を簡単に朕明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、第１導を型半導体基板となるｐ型半導体基板
の上に第２導電型半導体層となるｎ型半導体層が形成さ
れ、このｎＷ層の表面に半導体素子が形成されこの半導
体素子はその周囲をかこむように細られた溝と、この壽
にそってその直下に形成されｐ型基板に接続される第１
導電型半導体層であるｐ型半導体層とによって周辺の半
導体領域から電気的に分離された半導体装置において、
上記ｐ型半導体層はその表面にそって拡散された第２導
車型層であるｎｆＪＪ層とで構成されたｐｎ接合容量を
有するもので、これにより半導体装置の微細化を損うこ
となく容量が形成でき、前記発明の目的が達成できる。That is, an n-type semiconductor layer that becomes a second conductivity type semiconductor layer is formed on a p-type semiconductor substrate that becomes a first conductivity type semiconductor substrate, and a semiconductor element is formed on the surface of this nW layer. A narrow groove encircling the circumference and a first groove formed just below the groove and connected to the p-type substrate.
In a semiconductor device electrically isolated from a surrounding semiconductor region by a p-type semiconductor layer that is a conductive type semiconductor layer,
The p-type semiconductor layer has a pn junction capacitance composed of the nfJJ layer, which is a second conductor type layer, diffused along its surface, and this allows the capacitance to be increased without impairing the miniaturization of the semiconductor device. The object of the invention can be achieved.
〔実施例１〕
第１図及び第２図は本発明の一実施例を示すもの〒あっ
て、第１図はバイポーラＩＣにおけるトランジスタとそ
の周辺部に形成した容量の平面図、第２図は第１図にお
けるＡ−Ａ’切断断面図である、
】はｐ型シリコン単結晶基板、２けｎ 型埋込層、３は
その上にエピタキシャル成長させたｎ型シリコン層であ
る。[Example 1] Figures 1 and 2 show an example of the present invention. Figure 1 is a plan view of a transistor in a bipolar IC and a capacitor formed around it, and Figure 2 is a plan view of a transistor and a capacitor formed around it. This is a cross-sectional view taken along the line AA' in FIG. 1. ] is a p-type silicon single crystal substrate, 2 is an n-type buried layer, and 3 is an n-type silicon layer epitaxially grown thereon.
このｎ型シリコ７層３の一部３＆はｎｐｎ）ランジスタ
累子のコレクタを形成するものであって、その表面にト
ランジスタのペースとなるｐ型拡散１Ｍ４．エミッタと
なるｎ＋ｎ型拡散層が形成される。ｎ８！Ｉシリコン（
＠３ｈの一部はエッチされて薄くなった表面にコレクタ
取出し部となるｎ＋型型数散層６ｎ＋＋埋込層２に接続
するように形成されるｒ、ｎｐｎ）ランジスタ素子領域
の周囲を取囲むように溝７が掘られ、ｎ７にそってｐ型
拡散層８が形成されてその直下のｐ型基板１に接続し、
周辺領域から素子頭載３ａをγ電気的に分離するアイソ
レーション部をつくっている。A part 3& of this n-type silicon 7 layer 3 forms the collector of the npn) transistor transistor, and p-type diffusion 1M4. An n+n type diffusion layer serving as an emitter is formed. n8! I silicon (
A part of @3h is formed on the etched and thinned surface so as to be connected to the n+ type scattered layer 6n++ buried layer 2, which will serve as the collector extraction part.R, npn) surrounds the transistor element region A groove 7 is dug as shown in FIG.
An isolation section is created that electrically isolates the element head 3a from the surrounding area.
このアイソレーション部のｐ銅拡散層８０表面にそって
ｎ＋型型数散層９コの字形に形成され、このｎ＋型型数
散層９ｐ型拡散Ｎ８とのｐｎ接合が容量となる。一方の
ｎ＋型型数散層９容ｉｔ極（Ｎ＋ ）１０が設けられ、
他方はｐ型基板に接続する接地電極（ＧＮＤ ）１１と
なっている。上記ｎ＋型型数散層はエミッタｎ＋型拡散
層５の拡散工程を利用して形成されるものでその拡散層
５゜９表面に酸化膜が欠除する場合、この上をトランジ
スタのアルミニウム配線を通すことはできないので、第
１図に示すようにトランジスタの各を称からの引き出し
配線はコの字形のｎ＋型型数散層９形成されない部分か
ら実線で示す方向に取り出す（Ｂ、Ｃ，Ｅ’）。あるい
は気相化学堆積法（ＣＶＤ）によるリンシリケートガラ
ス（ＰＳＧ）又はポリイミド系樹脂などからなる層間絶
縁膜を介した２層配線構造を利用する。Nine n+ type scattered layers are formed in a U-shape along the surface of the p copper diffusion layer 80 in this isolation section, and the pn junction between this n+ type scattered layer 9 and the p type diffusion N8 becomes a capacitor. On the other hand, an n+ type scattering layer 9 and an it pole (N+) 10 are provided,
The other side is a ground electrode (GND) 11 connected to the p-type substrate. The above n+ type scattering layer is formed using the diffusion process of the emitter n+ type diffusion layer 5, and if the oxide film is missing on the surface of the diffusion layer 5.9, the aluminum wiring of the transistor is formed over this. As shown in FIG. '). Alternatively, a two-layer wiring structure using an interlayer insulating film made of phosphosilicate glass (PSG) or polyimide resin by chemical vapor deposition (CVD) is used.
以上実施例で述べｌζ本発明によれば、従来利用されて
いないアイソレーション領域を容量として活用するもの
であり、微細楢造を損うことなく容量面枳を確保できる
。一つのＩＣ，ＬＳＩのチップには多数のトランジスタ
、例えば２０００個のトランジスタを具えるものであれ
ば、それらの周辺のアイソレーション領域にそって２０
００個の容おを形成することができる、これらを並列に
接続１れはチッブナイズを増すことなく大容量を確保す
ることができる。According to the present invention, which has been described in the embodiments above, an isolation area that has not been used conventionally is utilized as a capacitor, and a capacitance can be secured without damaging the fine structure. If one IC or LSI chip has a large number of transistors, for example 2000 transistors, 20
By connecting these in parallel, a large capacity can be secured without increasing the number of chips.
〔実施例２〕
第３図乃至第１０図は本発明の他の一夾施例な示すもの
であって、一つの導体体基体にｎｐｎトランジスタ素子
とＩ ＩＬ（注入集積論理素子）とを有し、それらの間
に設けられた溝アイソレージ・９ン部を利用して容量な
形成する場合のプロセスの工程１析１ω図である。[Embodiment 2] FIGS. 3 to 10 show another embodiment of the present invention, in which an npn transistor element and an IIL (implant integrated logic element) are provided on one conductive substrate. FIG. 6 is a diagram showing a step 1 analysis of a process in which a capacitance is formed by utilizing a groove isolation portion provided between them.
Ｊソ、下沓工程に従って説明する。J So, I will explain according to the step-by-step process.
ｉｌｌ ａｍ３図に示すように、ｐ型シリコン基板１を
用意し、表面にｎ＋型埋込層２を拡散してその上にｎ型
ドープ７リコンＩＶ１３を厚さ１．７５ｍμにエピタキ
シャル成長させ、このｎ型シリコン層表面に熱酸化１嘆
１２． ＣＶ Ｄ−酸化Ｖ＜ ｓｈｏ、 ） １３を生
成させる。As shown in Figure ill am 3, a p-type silicon substrate 1 is prepared, an n+ type buried layer 2 is diffused on the surface, and an n-type doped 7 recon IV13 is epitaxially grown on it to a thickness of 1.75 mμ. 12. Thermal oxidation on the surface of the mold silicon layer. Generate CV D-oxidation V<sho, ) 13.
（２）ホトレジスト技術により第４図に示すように上記
酸化膜を部分的にエッチしたマスク１２ａ。(2) A mask 12a in which the oxide film is partially etched using a photoresist technique as shown in FIG.
１３ａを通してシリコン層のエッチ（異方性エッチ）を
行ないアイソレーション部となる深さ０．８μｍ程度の
テーパ状溝１４を掘る。The silicon layer is etched (anisotropically etched) through the silicon layer 13a to dig a tapered groove 14 having a depth of about 0.8 μm to serve as an isolation section.
（３）第５図に示すようにＩＩＬを形成すべき側のｎ型
シリコン層の表面をｄ−０３μｍ８度エッチする。(3) As shown in FIG. 5, the surface of the n-type silicon layer on the side where the IIL is to be formed is etched d-03 μm 8 times.
（４）酸化膜マスク１２ａ、１３ａを取除き、新たに酸
化膜１４を生成した後、ホトレジストマスク１５を介し
ボロンイオン杓込み、拡散を行なって第６図に示すよう
にアイソレーション部となる溝１４とｐ型基板１との曲
にｐ銅拡散層（アイソレーション部）１７を形成する。(4) After removing the oxide film masks 12a and 13a and forming a new oxide film 14, boron ions are poured in through the photoresist mask 15 and diffused into grooves that will become isolation parts as shown in FIG. A p copper diffusion layer (isolation section) 17 is formed between the p-type substrate 14 and the p-type substrate 1.
（５１マスク１６を取除き、ホトエッチを行い、第７図
に示すように上記酸化ｗ７４１５の一部を窓開する。(Remove the mask 16 and perform photoetching to open a part of the oxidized w7415 as shown in FIG. 7.
（６１ＣＶＤ＠酸化膜１８で上記酸化膜１５の窓開した
一部を覆った状態でボロンイオン打込み（ぺ′−ス拡散
）を行い、第８図に示すようにｎｐｎ）ランジスタのベ
ースｐＷＩ１４及びＩＩＬｆ７）インジェクタｐ型層１
９インバーストランジスタのベースｐ型層２０を形成す
る。(Boron ion implantation (peace diffusion) is performed with the 61CVD@oxide film 18 covering the open part of the oxide film 15, and npn as shown in FIG. 8) Bases of the transistor pWI14 and IILf7 ) Injector p-type layer 1
9. A base p-type layer 20 of an inverse transistor is formed.
（力 上記ＣＶＤ−酸化膜１８を取除き、新たに酸化、
ホトエッチ工程を軽でリン・イオン打込み（エミッタ拡
散）を行い、第９図に示すようにｎｐｎトランジスタの
エミッタｎ 型層５、コレクタ取出しｔｉ−１ｉ ｎ＋
型層６、ＩＩＬのマルチコレクタｎ＋型層２１を形成す
るとともに、アイソレーション部であるｐ型拡散層１７
の表面に接合容量のためのｎ＋型層９を拡散する・
（８）最後に表面酸化膜に対しコンタクトアロイ・ソチ
、アルミニウム、スパッタ（又ｔｊＡＡ着）、アルミニ
ウムポトエノチ、コンタクトアロイを行なって、第１０
図に示すように各領域にコンタクトするアルミニウム１
ｉ’、４ｉ（配線）を完成させる。(Force) Remove the above CVD-oxide film 18, oxidize it anew,
Phosphorus ion implantation (emitter diffusion) is performed using a light photoetch process, and as shown in FIG.
The type layer 6 forms the multi-collector n+ type layer 21 of IIL, and also forms the p type diffusion layer 17 which is the isolation part.
Diffusion of n+ type layer 9 for junction capacitance onto the surface of , 10th
Aluminum 1 contacting each area as shown in the figure
Complete i', 4i (wiring).
すなわち、ｎｐｎトランジスタ側でエミッタ市松Ｅ、ベ
ースｉｔ極Ｂ１コレクタ電極Ｃ１ＩＩＬ側でイン伏、ク
タ電極Ｉｎｊ、ベース電、ｔｋＢ、マルチコレクタ電極
ＣＩ＋Ｃ２が形成され、アイソレーション部に形成した
接合容量のｎ＋ｍ層側に電極Ｎ＋接合容量のｐ型層側に
接地（ＧＮＤ）’ｉｆｆ、極が形成される。That is, an emitter checkerboard E is formed on the npn transistor side, an indentation electrode Inj, a base electrode, tkB, and a multi-collector electrode CI+C2 are formed on the base IT electrode B1 collector electrode C1IIL side, and an n+m layer of junction capacitance formed in the isolation part. An electrode is formed on the N+ side of the p-type layer of the junction capacitance, and a ground (GND) pole is formed on the side of the p-type layer.
以上本実施例で述べた本発明によれば、下記の効果が得
られる。According to the present invention described above in this embodiment, the following effects can be obtained.
（１）容量素子の形成に、ノくイボーラ・トランジスタ
（ｎｐｎ）ランジスタ素子及びＩＩＬ素子）の製造プロ
セスをそのまま適用できるため、該容量素子の形成のた
めのプロセスを追加する心安がなく、プロセスの単純化
が計れる。(1) Since the manufacturing process of the Nokuibora transistor (NPN transistor element and IIL element) can be applied as is to the formation of the capacitive element, there is no need to worry about adding a process to form the capacitive element, and the process Simplification is possible.
（２）容量素子を、従来素子の形成に利用出来なかった
領域たとえば、アイソレーション領域に形成するため、
チッブザイズの小型化が可能となる。(2) To form a capacitive element in an area that could not be used for conventional element formation, such as an isolation area,
It becomes possible to reduce the chip size.
（３）上記２より、生導体装置の低コスト化が達成でき
る。(3) From 2 above, cost reduction of the live conductor device can be achieved.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で釉々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, it is to be understood that the present invention is not limited to the above-mentioned examples, and can be modified without departing from the gist thereof. Not even.
本発明はバイポーラＩＣの全てに適用することができ、
特に素子の数の多い半導体装置に適用して有効である。The present invention can be applied to all bipolar ICs,
This is particularly effective when applied to semiconductor devices with a large number of elements.
図【０ｊの簡単な駅間
第１図及び第２図は本発明の一実施例を示し、第１図は
バイポーラトランジスタ素子とその周辺部を含むＩＣの
平面図、
第２図ｔ［１１図におけるＡ−Ａ’断面図である８第３
図乃至第１０図は本発明の他の実施例を示し、一つの導
体体基体にトランジスタとＩＩＬを形成する場合のプロ
セスの工程断面図である。Figures 1 and 2 show an embodiment of the present invention, and Figure 1 is a plan view of an IC including a bipolar transistor element and its surrounding area, and Figure 2 is a plan view of an IC including a bipolar transistor element and its surrounding area. 8-3, which is a cross-sectional view taken along line A-A' in
10 to 10 show other embodiments of the present invention, and are cross-sectional views of a process in which a transistor and an IIL are formed on one conductive substrate.
１・・・ｐ型シリコン単結晶基板、２・・・１型埋込層
、３，３ａ・・・エピタキシャルｎ型シリコン層、４・
・・ベースｐ型拡散層、５・・・エミッタｎ 型拡散層
、６・・・コレクタｎ″岱拡散層、７・・・ｕ・１．８
・・・アイソレーションｐ型拡散層、９・・・ｎｌＪ拡
散層、１０・・・￥Ｉ叶低椿−１１・・・接地ｔａ他、
１２・・・熱酸化膜、１３・・・ＣＶＤ酸化膜、１４・
・・テーバ状溝、１５・・・酸化膜、１６・・・ホトレ
ジストマスク、１７・・・アイソレーショｙｐ型酸化層
、１８・・・ＣＶＤ酸化膜、１９・・・インジェクタｐ
型層、２０・・・インバーストランジスタのベースｐ型
層、２１・・・マルチコレクタｎ＋型層。DESCRIPTION OF SYMBOLS 1... P-type silicon single crystal substrate, 2... 1-type buried layer, 3, 3a... Epitaxial n-type silicon layer, 4...
...Base p-type diffusion layer, 5...Emitter n-type diffusion layer, 6...Collector n''-diffusion layer, 7...U-1.8
...Isolation p-type diffusion layer, 9...nlJ diffusion layer, 10...¥I Kano Low Tsubaki-11...Grounding ta, etc.
12... Thermal oxide film, 13... CVD oxide film, 14.
... Tapered groove, 15 ... Oxide film, 16 ... Photoresist mask, 17 ... Isolation yp type oxide layer, 18 ... CVD oxide film, 19 ... Injector p
type layer, 20... Base p-type layer of inverse transistor, 21... Multi-collector n+ type layer.
第 ２ 図 Ｊ冗 ２ ／ 第 ３ 図 、３ 第 ６ 図 第 ７ 図 第 ８ 図 第 ９ 図 第１０図 ？ｔｒ７ＬＴｌ？Ｇ ＩＩＬFigure 2 J Jyo 2 / Figure 3, 3 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 ? tr7LTl? G IIL
Claims (1)
形成され、この第２導を型牛導体層表面に半導体素子が
形成され、この半導体素子はその同曲をかこむように掘
られた溝と、この溝にそってその直下に形成され第１導
電型牛導体基板に接続される第１導電型牛導体層とによ
って周辺の導体体領域から電気的に分離された半導体装
置であって、上記第１導電型牛導体層はその表面にそっ
て拡散された第２導電型層とで構成された容量を有する
ことを特徴とする半導体装置。 ２、上記半導体素子の形成された第２導電型半導体領域
とその下の＠１導を警手導体基板との間には高濃度第２
導亀型埋込層が埋込まれ、上記纂２４ｖＬ型牛導体領域
をコレクタとし、上記溝の一部に設けられた高ａ度第２
導電型層を上記埋込層に接触させてコレクタ取出しｆＩ
ｌＳとするトランジスタが形＋＋２されている特１′ｒ
−請求の範囲第１項に記載の半導体装置。[Claims] 1. A second conductivity type semiconductor layer is formed on the first conductivity type conductor substrate, and a semiconductor element is formed on the surface of the second conductivity type conductor layer. A groove is dug to surround the same groove, and a first conductive type conductor layer is formed directly below the groove and connected to the first conductive type conductive substrate, thereby electrically connecting the surrounding conductor area. 1. A separated semiconductor device, wherein the first conductive type conductor layer has a capacitance formed by a second conductive type layer diffused along its surface. 2. A high-concentration second conductor substrate is placed between the second conductivity type semiconductor region where the semiconductor element is formed and the @1 conductor substrate below it.
A conductive tortoise-shaped buried layer is embedded, the above-mentioned 24vL type cow conductor region is used as a collector, and a high-a degree second layer provided in a part of the above-mentioned groove is used.
The conductivity type layer is brought into contact with the buried layer to take out the collector fI
The characteristic 1'r in which the transistor designated as lS is of the shape ++2
- A semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58244048A JPS60136362A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58244048A JPS60136362A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60136362A true JPS60136362A (en) | 1985-07-19 |
Family
ID=17112944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58244048A Pending JPS60136362A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60136362A (en) |
-
1983
- 1983-12-26 JP JP58244048A patent/JPS60136362A/en active Pending
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