JPS60134434A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable to more enhance the integration degree of a semiconductor integrated circuit while a disconnection, etc., of gate wirings are eliminated in the manufacture thereof by a method wherein, when an interelement isolation of the integrated circuit made with a III-V compound semiconductor is performed, an isolating region between elements is brought into a high-resistance state by selectively implanting ions therein. CONSTITUTION:An I-type InP buffer layer 2, an N type In0.53Ga0.47As active layer 3 and an N<+> type InP electrode layer 4 are laminatedly grown on a semiinsulative InP substrate 1. Then, when an interelement isolation is performed on this wafer obtained, a high resistive layer 8, which intrudes into the layer 2 by selectively implanting B<+> ions, is formed and a part of the active layer 3 of about 0.05OMEGA.cm or thereabout, where is included in the layer 8, is raised to a resistivity of about 5,000OMEGA.cm. After that, an AuGeNi/Au film 5 is adhered on the whole surface, an alloyed thermal treatment is performed for enabling the film 5 to make an ohmic contact to the layer 4, Si3N4 films 6 are provided on gate parts, the exposed parts of the layer 4 are removed using the Si3N4 films 6 as masks, and gate electrodes 7 are mounted on the exposed parts of the layer 3. In such a way, the MISFET is not constituted in a mesa structure. As a result, a disconnection, etc., of the electrodes 7 can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor integrated circuit.

(Structure of conventional example and its problems) ■-■ Compound semiconductors have higher mobility than semiconductors of group ■ simple elements such as SL and Ge, and MES structures can be easily obtained in terms of materials. Research and development is progressing as a MESFET material with excellent high frequency characteristics. It is attracting attention as a material for integrated devices because semi-insulating crystals, which have been difficult to obtain with St and Ge, can be easily obtained.

■-■ MESFETs using compound semiconductors are semi-insulating (
S・Engineering・) via an additive-free i-type buffer layer on the substrate
゛An active layer is placed thereon, and various electrodes constituting the FET are formed. Conventionally, separation between FETs has been carried out by mesa etching that reaches the buffer layer, but the unevenness of the step or the very existence of the step that occurs in this process causes metal wiring to break. Therefore, it was not possible to obtain a highly integrated IC device.

(Object of the Invention) The present invention provides a method for manufacturing a semiconductor integrated circuit that overcomes the above problems and enables high integration.

(Structure of the Invention) The present invention provides an MES constructed on a ■-■ compound semiconductor substrate.
When separating the FBTs individually, the ion-implanted high-resistance semiconductor layer is used as a separation layer.

(Description of Embodiment) The figure is a sectional view of a semiconductor integrated circuit manufactured according to an embodiment of the present invention.

An i-type InP buffer layer 2 with a thickness of 1.0 μm is provided on a semi-insulating InP substrate l, and an active layer n'' is formed on it.
I n”o,' s”aG ao, 47 A 8 layer 3
80'0 x% electrode layer n -InPn seed layer 2000
Each of the X grows. Although the MBE method and MOCVD method, which allows easy control of film thickness, are used for growth, in this example, the Ml method was used for growth. The substrate temperature was 500°C, the Ga cell temperature was 1100°C, the engineering n cell temperature was 1200°C, the A8 cell temperature was 250°C, and the P cell temperature was 250°C. Sn was used as the n-type impurity, and the cell temperature was 780°C. 1-I
The growth time of the nP layer 2, n-InGaAs layer 3, and n-InPn seed layer was 1 hour, 6 minutes, and 5 minutes, respectively.

In order to isolate the elements of the obtained wafer, a high resistance layer 8 was formed by partially increasing the resistance of the active layer 3 by selective ion implantation. B+ was used as the implanted ion. By performing the implantation under the conditions of an accelerating voltage of 150 kV and a dose of lXl014cIn-2, the active layer 3 with ρ = O, 05Ω-α has a resistivity of ρ' = 500OΩ-saw, and good isolation characteristics are obtained. Obtained. An AuGeNi/Au film 5 is deposited as a contact for current injection to the drain and source, and an alloying heat treatment is performed to establish ohmic contact with the n-InPn seed layer of the electrode layer.

In the rear portion, the electrode layer n+-I nP layer 4 is etched through the opening formed in the 813N4 film 6. HC1/1120 solution was used as the etching solution. With this etching solution, “0.53Ga0.4□As and In”
Since selective etching with P is possible, etching is performed on active layers Lno, s3Gag, 47A8 layer 3 and electrode layer n-
It stops at the interface with the InP layer 4. Therefore, the channel thickness directly below the dart electrode 7 is t. ' is just n −I no
, s 3G a o, 4 □A equal to the film thickness of 83.

Since crystal growth is performed by MBE growth, which has excellent in-plane film thickness uniformity and controllability, t,' = 800X is always formed at any location on the wafer, and as a result, normally-off characteristics are achieved with excellent reproducibility. can get. The Schottky gate electrode 7 is formed by At vapor deposition and lift-off technique. At this time, in the conventional mesa structure, the dart electrode 7 is
Since it is as thin as 1 μm, wire breakage at the stepped portion poses a problem, but in this example, separation is performed by ion implantation, so there is no step, and wire breakage is no longer a problem. The MESFET shown in the figure is obtained in the above manner.

In this example, the impurity concentration of each layer is l x l in the active layer 3.
017cm-3, electrode layer 4 is l X l Q19ca
It is r-3.

The high concentration of the n+-InPn seed layer lXl019on-'' has a low specific resistance of 5X10-'Ω-m, and therefore the resistance between the dirt and the source is due to the active layer n''-I produced by side etching of the InPn seed layer. n 6.53 Ga
The resistance is only the resistance of the o47As layer 3, which is a low resistance of several ohms. In this way, since element isolation is performed by ion implantation instead of the conventional mesa etch, there is no breakage at the step part of the dirt metal, and the conventional date yield is 800/1.
A yield of 1000/1000 compared to 0.000 was obtained, and current leakage between elements was about 1 μA when IOV was applied at 2 μm intervals, which was the same as in the conventional method, making it possible to achieve high integration.

The static characteristics of the obtained MKSFET are as follows: threshold gate voltage VT = 0.1V (drain current 20μA) conmecance box = 150 mS /mm , on-resistance 150
An Ω propagation delay rate of 20 ps was obtained. In addition, the minimum plane distance between elements is 2μm, and the leakage between elements is 1μm/IOV.
The implanted ions mentioned in the above explanation are not limited to B, but also A.
It is also possible to use r+, O+, H+, Fe+, etc. Furthermore, the channel type of the FET is not limited to n-channel. Furthermore, the FET characteristics are not limited to normally-off type, but may be normally-on type.

(Effects of the Invention) As described above, the present invention uses a semiconductor layer whose resistance has been increased by ion implantation as a separation layer, so that it is possible to eliminate υ without disconnection of gate wiring, and to arrange elements with a high degree of integration. It has become possible.

[Brief explanation of drawings]

The figure is a cross-sectional view of a semiconductor integrated circuit according to an embodiment of the present invention. l... Semi-insulating InP substrate, 2... Buffer layer 1-
InPs3...Active layer n"' I n 6.5a G
il o, 47A 8 layers, 4... Electrode layer n+InP layer, 5... AuGeNi/A for source and drain
u film, 6... Spacer S 1 aN4 film, 7... Dirt electrode, 8... 1 ON implantation high resistance layer.

Claims (1)

[Claims] (1)-(2) A method for manufacturing a semiconductor integrated circuit, characterized in that isolation between elements of a semiconductor integrated circuit using a compound semiconductor is achieved by selectively implanting ions between the elements to increase resistance.