JPS60134328U - binary counter - Google Patents
binary counterInfo
- Publication number
- JPS60134328U JPS60134328U JP2272084U JP2272084U JPS60134328U JP S60134328 U JPS60134328 U JP S60134328U JP 2272084 U JP2272084 U JP 2272084U JP 2272084 U JP2272084 U JP 2272084U JP S60134328 U JPS60134328 U JP S60134328U
- Authority
- JP
- Japan
- Prior art keywords
- clock pulse
- output
- signal
- pulse
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図、第２図は従来のバイナリカウンタの構成を示す
図、第３図は本考案のバイナリカウンタの構成を示す図
、第４図は本考案のバイナリカウンタの動作を説明する
ためのタイムチャート、第５図は本考案のバイナリカウ
ンタの構成要素のひとつであるクロックパルス整形回路
の構成例を示す図、第６図は第５図の回路の各点におけ
るパルス波形を示す図である。
図において１００，１０１はフリップフロップ回路、１
０２はＱ信号、１０３はｎ信号、１０４はｎ信号、１０
５はｎ信号、１０６はＣ信号、１０７はＣ８号、１０８
はマスターフリップフィロツブの一σ出力信号、２００
，２０１はフリップフロップ回路、２０２，２０３，２
０４および２０５は２人力ナンドゲート、２０６，２０
７はワイヤードオア回路、２０８はＣ信号、２０９はで
信号、３００はクロックパルス整形回路、３０１は入力
クロックパルス、３−０２は出力クロックパルス、３０
３，３０６は２人力ナンドゲート、３０４はｎ信号、３
０５はＳ信号、３０７はｎ信号、３０８はＷ信号、３０
９はセットリセット・フリップフロップ回路、３１０，
３１１は２人力ナンドゲート、３１２はＱ信号、３１３
はＱ信号、４００はＣ信号、４０１は（信号、４０２は
Ｑ信号、４０３はｎ信号、４０４はＱ信号、４０５はｎ
信号、４０６はＣ信号の変化点、４０７はｎ信号の変化
点、４０８はｎ信号の変化点、４０９はＣ信号がゼロレ
ベルに戻る時点、４１０は次のり 。
ロックパルスの到来点、４１１はｎ信号、４１２はｎ信
号の反転、４１３はｎ信号の変化、４１４はＱ信号の反
転、４１５はｎ信号の変化、４１６はｎ信号の変化点、
４１７はｎ信号の変化点、４１８はクロックパルスが低
レベルに戻る時点、５００はインバータ、５０１は遅延
回路、５０２は７１図
Ｃｏ−’ ＋０８ ｌ−誌
７２図
一′−−−−−−−
） ２
２０８ ２０９ −
７４図 −
一−（ソFigures 1 and 2 are diagrams showing the configuration of a conventional binary counter, Figure 3 is a diagram showing the configuration of the binary counter of the present invention, and Figure 4 is a time diagram for explaining the operation of the binary counter of the present invention. 5 is a diagram showing an example of the configuration of a clock pulse shaping circuit which is one of the components of the binary counter of the present invention, and FIG. 6 is a diagram showing pulse waveforms at each point of the circuit of FIG. 5. In the figure, 100 and 101 are flip-flop circuits, 1
02 is Q signal, 103 is n signal, 104 is n signal, 10
5 is n signal, 106 is C signal, 107 is C8, 108
is the 1σ output signal of the master flip filter, 200
, 201 are flip-flop circuits, 202, 203, 2
04 and 205 are two-man powered Nand gates, 206, 20
7 is a wired OR circuit, 208 is a C signal, 209 is a signal, 300 is a clock pulse shaping circuit, 301 is an input clock pulse, 3-02 is an output clock pulse, 30
3,306 is a two-person NAND gate, 304 is an n signal, 3
05 is S signal, 307 is n signal, 308 is W signal, 30
9 is a set-reset flip-flop circuit, 310;
311 is a two-man NAND gate, 312 is a Q signal, 313
is the Q signal, 400 is the C signal, 401 is the (signal, 402 is the Q signal, 403 is the n signal, 404 is the Q signal, 405 is the n signal,
406 is the change point of the C signal, 407 is the change point of the n signal, 408 is the change point of the n signal, 409 is the point at which the C signal returns to zero level, and 410 is the next step. The arrival point of the lock pulse, 411 is the n signal, 412 is the inversion of the n signal, 413 is the change in the n signal, 414 is the inversion of the Q signal, 415 is the change in the n signal, 416 is the change point of the n signal,
417 is the change point of the n signal, 418 is the point at which the clock pulse returns to low level, 500 is the inverter, 501 is the delay circuit, 502 is the 71 figure Co-' +08 l- magazine 72 figure 1' ) 2 208 209 - Figure 74 - 1 - (So
Claims (1)
述する値より小さな一定パルス幅をもつ出力クロックパ
ルスに変換するクロックパルス整形回路と、入力データ
信号と前記出力クロックパルスとを入力してセットパル
スを出力する第１の２人力ナンドゲートと、入力データ
反転信号と前記出力クロックパルスとを入力してリセッ
トパルスを出力する第２の２人力ナンドゲートと、２込
個の２人力ナンドゲートから成り前記セットパルスによ
りセットされて出力データ信号を出力し前記リセットパ
ルスによりリセットされて出力データ反転信号を出力す
るセットリセット・フリップフロップ回路とを少くとも
含み、前記セットリセット・フリップフロップ回路の出
力データ信号を前記第２の２人力ナンドゲートの入力デ
ータ反転信号として帰還し、前記セットリセット・フリ
ップフロップ回路の出力データ反転信号を前記第１の２
人力ナンドゲートの入力データ信号として帰還するよう
に構成し、前記クロックパルス整形回路の出力クロック
パルス幅を、前記第１、第２のナントゲート及び前記セ
ットリセット・フリップフロップ回路に使用されるゲー
ト素子の伝播遅延時間の２倍よりも小とすることを特徴
とするバイナリカウンタ。A clock pulse shaping circuit inputs a clock pulse having an arbitrary pulse width and converts it into an output clock pulse having a constant pulse width smaller than a value described later, and a clock pulse shaping circuit inputs the input data signal and the output clock pulse to generate a set pulse. a first two-man-powered NAND gate that outputs the set pulse; a second two-man-powered NAND gate that receives the input data inversion signal and the output clock pulse and outputs a reset pulse; and two two-man powered NAND gates that output the set pulse. a set-reset flip-flop circuit that is set by the reset pulse to output an output data signal, and is reset by the reset pulse to output an output data inversion signal; The output data inversion signal of the set-reset flip-flop circuit is fed back as the input data inversion signal of the two-man powered NAND gate of No. 2, and the output data inversion signal of the set-reset flip-flop circuit is
The output clock pulse width of the clock pulse shaping circuit is configured to be fed back as an input data signal of the human-powered NAND gate, and the output clock pulse width of the clock pulse shaping circuit is adjusted to the output clock pulse width of the gate element used in the first and second NAND gates and the set-reset flip-flop circuit. A binary counter characterized in that the propagation delay time is smaller than twice.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2272084U JPS60134328U (en) | 1984-02-20 | 1984-02-20 | binary counter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2272084U JPS60134328U (en) | 1984-02-20 | 1984-02-20 | binary counter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60134328U true JPS60134328U (en) | 1985-09-06 |
Family
ID=30515278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2272084U Pending JPS60134328U (en) | 1984-02-20 | 1984-02-20 | binary counter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60134328U (en) |
-
1984
- 1984-02-20 JP JP2272084U patent/JPS60134328U/en active Pending
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