JPS60133632U - Semiconductor element mounting structure - Google Patents

Semiconductor element mounting structure

Info

Publication number
JPS60133632U
JPS60133632U JP1942884U JP1942884U JPS60133632U JP S60133632 U JPS60133632 U JP S60133632U JP 1942884 U JP1942884 U JP 1942884U JP 1942884 U JP1942884 U JP 1942884U JP S60133632 U JPS60133632 U JP S60133632U
Authority
JP
Japan
Prior art keywords
mounting structure
semiconductor element
element mounting
mounting
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1942884U
Other languages
Japanese (ja)
Other versions
JPH051079Y2 (en
Inventor
貴志男 横内
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1942884U priority Critical patent/JPS60133632U/en
Publication of JPS60133632U publication Critical patent/JPS60133632U/en
Application granted granted Critical
Publication of JPH051079Y2 publication Critical patent/JPH051079Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

体チップの形状で同図Ａは平面、−、 Ｂは側面図、第２図は本考案に係る半導体チップの装着
状態を示す断面図また第３図は冷却能力とピンの長さと
の関係図である。In the figure, A is a plan view, B is a side view, FIG. 2 is a sectional view showing the mounting state of the semiconductor chip according to the present invention, and FIG. 3 is a diagram showing the relationship between cooling capacity and pin length. It is.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 耐熱性基板上に複数個の半導体素子をチップの状態で装
着して使用する実装形態において、萌半導体素子に設け
た複数の取り出し端子部と耐熱性基板上に設けた複数の
半導体素子据付は電極端子部とを一定の間隔を隔て金属
線夕相互に配線接続し固定することを特徴とする半導体
素子の実装構造。In a mounting configuration in which multiple semiconductor devices are mounted in the form of chips on a heat-resistant substrate, the multiple lead-out terminals provided on the semiconductor device and the mounting of multiple semiconductor devices provided on the heat-resistant substrate are connected to electrodes. A mounting structure for a semiconductor element, characterized in that terminal parts are interconnected and fixed by metal wires at a certain interval.
JP1942884U 1984-02-14 1984-02-14 Semiconductor element mounting structure Granted JPS60133632U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1942884U JPS60133632U (en) 1984-02-14 1984-02-14 Semiconductor element mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1942884U JPS60133632U (en) 1984-02-14 1984-02-14 Semiconductor element mounting structure

Publications (2)

Publication Number Publication Date
JPS60133632U true JPS60133632U (en) 1985-09-06
JPH051079Y2 JPH051079Y2 (en) 1993-01-12

Family

ID=30509002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1942884U Granted JPS60133632U (en) 1984-02-14 1984-02-14 Semiconductor element mounting structure

Country Status (1)

Country Link
JP (1) JPS60133632U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5728337A (en) * 1980-07-28 1982-02-16 Hitachi Ltd Connecting constructin of semiconductor element
JPS5791586A (en) * 1980-11-29 1982-06-07 Tokyo Shibaura Electric Co Hybrid integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5728337A (en) * 1980-07-28 1982-02-16 Hitachi Ltd Connecting constructin of semiconductor element
JPS5791586A (en) * 1980-11-29 1982-06-07 Tokyo Shibaura Electric Co Hybrid integrated circuit device

Also Published As

Publication number Publication date
JPH051079Y2 (en) 1993-01-12

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