JPS60122437A - Programmable watchdog timer - Google Patents

Abstract

PURPOSE:To optimize the setting time by detecting a difference between a set timer time and a data processing execution time during that timer time and renewing and storing a minimum value of the result of detection to check the propriety of the timer time. CONSTITUTION:A processing unit 1 gives timer time data set in response to a data processing scheduled amount of the period to a timer register 6 via a data register 3 and also to a decrement counter 7 depending on the input of a selection signal and a write signal. The detected value being a difference between the set time value and the data processing execution time of the couner 7 is fed to minimum time register 8 and a comparator 9. Then the comparator 9 compares the output value of the counter 7 with the output value of the minimum time register 8 inputted to an input terminal B to renew the minimum value. Then whether or not the set timer time is appropriate is checked.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field of the invention]
,fart.

When a timer is repeatedly refreshed using a flash signal and a runaway of the processor unit is detected when the timer times out, the timer time after each refresh is set according to the amount of data that the processor unit is scheduled to process until the next refresh. Regarding the programmable watchdog timer.

[Prior art]

In a conventional watchdog timer, the timer is refreshed periodically by overtime of another timer, or
or the progress of data processing in the processor unit (
In both cases, the timer time set at the time of refreshing is fixedly determined using hardware such as a CR circuit or a digital counter. For example, when sequentially executing programs PI, P2°, fist, etc. as shown in FIG.
After executing programs 2, P3, and P4, perform a refresh as the execution of the next program, then refresh the programs PI and P5' twice after executing [1], and then continue to program P6.
, P7, and P8, but at the program start time TO and at each refresh time TI.

The timer time set in T2,... is always one step time determined by the above hardware, for example Id2
00m5ec is out. For this reason, due to the difference in the amount of data processed by the processor unit in the interval between each refresh, for example, the time t1 until a runaway of the processor unit that occurs after executing programs P1 to P4 is detected by a timeout, and the Time t2 until later runaway is detected by timeout
In addition, in order to avoid erroneous timeouts, the timer time is determined with a margin based on the entire section with the heaviest load.
t2 etc. inevitably tended to be large and were rare. This t
A long time such as 1, t2, etc. means a long runaway time, and a large amount of memory etc. is destroyed during that time.

For this reason, it is conceivable to make the timer time after each refresh programmable, but even in that case, the remaining nine hours such as tl and t2 will vary depending on the execution content of each program and the processing method of the executive program. You won't know its actual value until you run the program.

If the set timer time is just barely adequate for the amount of data processed during that time, the watchdog timer will time out if some special processing, such as interrupt processing, occurs within that period.

[Object and structure of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to provide a programmable watchdog timer fil that can check whether or not the set timer time has rarely reached an appropriate value.

In order to achieve all of these objectives, the present invention is provided with means for detecting the difference between the set timer time and the data processing execution time during that time, and means for updating and storing the minimum value of the detection results for each section. It is something that

The present invention will be described in detail below using Examples.

[LOL example]

FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a processor unit such as a well-known CPU or microprocessor unit, 2 ('1 is an address register as an address driver of the processor unit 1, 3 is a data register as a data buffer of the processor unit 1, and 4 is an address register. 5 is a control signal generating circuit that outputs all read, /write, and other special control signals such as clear signals; 6;
Enter the timer register.

In the above configuration, the timer time is set by the processor unit 1. That is, the processor unit 1 supplies data corresponding to a larger timer time to the timer register 6 via the data register 3 according to the amount of data to be processed in that section, and the larger the amount of data to be processed is to the timer register 6 via the data register 3. and address decoder 4
A select signal is sent out through the control signal generation circuit 5, and a write signal is sent out through the control signal generation circuit 5. By inputting the select signal a and the write signal, the timer register 6 takes in the data of the timer time, and also by inputting the select signal and the write signal, the data is reset in the decrement counter 7.

After setting the timer time data, the decrement counter T decrements its contents by 1 every time the clock signal CL is input. As long as the processor unit 1 continues to operate normally, it sends out a refresh signal (write signal) at a cycle shorter than the above-mentioned timer time. The contents of the decrement counter 7 will not become "0" as long as it is set.
The output OUT indicating the time delay is also not sent out.

The contents of decrement counter 7 are the minimum time and register 8
and is supplied to the A input terminal of comparator 9. Here, the minimum time register 8 is the processor unit 171
), the maximum value is supplied as an initial value by a clear signal supplied via the control signal generation circuit 5. On the other hand, the comparator 9 compares the output value of the decrement counter 7 with the output value of the minimum time register 8 inputted to the B input terminal, and when the former is smaller than the latter, the output value k
Let it be "l". As a result, when the clock signal CL is input through the inverter 10, the enable signal is input from the AND circuit 11 to the minimum time register 8, so that the contents of the decrement counter 7 at that time are taken in. This situation is shown in FIG.

FIG. 3(a) shows the clock signal, FIG. 3(b) shows the output signal of the comparator 9, FIG. 3(c) shows all the output signals of the AND circuit 11, ■ is the timing to decrement the decrement counter 7, This shows the timing for refreshing the entire time register 8.

In this way, the minimum time register 8 always records the minimum value of the decrement counter 7, i.e. the timer time set in FIG.
The difference between the data processing execution time of tl and t2.

t3. ...The minimum value of ◆ will be kept.

This minimum value can be read out in the processor unit 1 via the buffer 12'fr:. That is, the buffer 12 becomes output enabled by the select signal supplied via the address decoder 4 and the read signal supplied from the control signal generation circuit 5, and sends the value fetched from the minimum time register 8 to the data bus. Therefore, by monitoring all of these values, it is possible to check whether or not the set value of the timer time is maintained appropriately.

In the embodiments described above, the decrement counter γ is used as a means for detecting the difference between the set timer time and the data processing execution time, and the minimum time register 8 and the comparator are used as means for updating and storing the minimum value. 9 was used, but the present invention is not limited to this, and it is of course possible to perform the calculation of the above-mentioned time difference or the comparison of the minimum value by software processing in the processor unit 1. .

〔Effect of the invention〕

As explained above, according to the present invention, by providing means for detecting the difference between the set timer time and the data processing execution time during that time, and means for updating and storing the detected result above the minimum value, It is possible to check whether or not the set time is appropriate, and the set time can be optimized.

[Brief explanation of the drawing]

Figure 1 shows the relationship between timer time and data processing time in the conventional watchdog tie system. 2 is a block diagram showing an example of the present invention, FIG. 3 is a time chart for explaining the update operation sound of the minimum time register, and FIG. 4 is a diagram showing the relationship between timer time and data processing time. The diagram shown is Ruru. 1: Fist processor unit, 6e: Timer register, T: Decrement counter, 8: Minimum time register, 9: e Fist comparator. Figure 1 Figure 4 A flat 100m54 150mSeC-gure+, 200m5ec--→1:
: + j12: m: "Figure 2 Figure 3 (b) A<8-m: "-- II II II 11 (-L-m-" +A-

Claims (1)

[Claims] , the processor unit 71), etc. In a watchdog timer that repeatedly refreshes a timer and detects runaway of the processor unit when the timer times out, the timer time after each refresh of the timer is changed from the current refresh to the next refresh. means for setting according to the scheduled data processing amount of the processor unit in the interval up to, means for detecting the difference between the set timer time and the data processing execution time of the processor unit in the interval, and the detection result in each interval. A programmable watchdog timer, comprising means for updating and storing the minimum value of .