JPS59160896A - Detection and correction system of memory error - Google Patents

Abstract

PURPOSE:To obtain a high-speed, high-reliability microprocessor system by detecting and correcting a memory error by utilizing a free time after an instruction or data is read out of a memory by a microprocessor. CONSTITUTION:A memory address generating circuit 6 has a counter circuit which counts up by one automatically and its output signal is supplied to the memory 22 through an AND gate 7 and an OR gate 3 by memory access signal 20 under the control of an NOT gate 21. The resulting read data from the memory 22 is supplied to an error detecting circuit 8 to check a humming code, and a correctable error is obtained to output an correctable error signal 9. Error data is then inputted to an error correcting circuit 12 to correct a one- bit error. The memory address generating an error is inputted to and stored in an error address register circuit 13 through an AND gate 10 and corrected data is inputted to and stored in a corrected data register circuit 14 through an AND gate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory error detection and correction method, particularly in a microprocessor system including a microprocessor and a memory storing a microprogram, without extending the cycle time. Memory error detection/
This invention relates to a memory error detection/correction method that enables correction.

[Prior art]

In a microprocessor system that includes a microprocessor and a memory that stores a microprogram, data read from the memory is conventionally processed for error detection and
The method used was to wait for the time required for correction before using it, but this method had the problem of not being able to speed up the cycle time because it required wasted time even when there was no error. .

In order to solve the above problem, data read from memory is input to the microprocessor without error detection and correction, and at the same time input to the error detection and correction circuit. A method has been proposed in which the operation of the microprogram is temporarily stopped and then the corrected data is operated in the subsequent cycle, or the microprogram is branched to the IJ) write routine.

However, although the above method can shorten the cycle time when there are no errors, extra cycle time is required when there is an error. There was a risk that this would cause another problem.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in conventional memory error detection and correction methods, and to detect and correct memory errors without extending the cycle time. An object of the present invention is to provide a memory error detection/correction method that enables correction and realizes a high-speed, highly reliable microprocessor system.

[Summary of the Invention] The main point of the present invention is to note that in a microprocessor system, the reading of instructions or data from memory by a microprocessor is generally only the first period of its cycle time. Therefore, the detection and correction of memory errors is performed using the waiting time after the cycle time.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a microprocessor illustrating an embodiment of the present invention.
FIG. 2 is a block diagram of the system. In the figure, 1 is a microprocessor, 22 is a memory storing instructions or data, 8 is an error detection circuit, 12 is an error correction circuit,
6 is a memory address generation circuit, 13 is an error address register circuit, 14 is a correction data register circuit, 15 is an address comparison circuit, and 2, 4, 7, 10, 11 (17), 3.5 are It is orgate.

When the microprocessor reads instructions or data from the memory 22, the memory address signal 19 is controlled by the AND gate 2. It is applied to the memory 22 via the OR gate 3. The memory 22
The data read from AND gate 4. or gate 6
The signal is input to the microprocessor 1 via. The aforementioned r
ta<, Since the above operations are completed in the first half of the microprocessor cycle time at the latest, this period is used to execute the next operation.

The memory address generation circuit 6 has a counter circuit that automatically increments by 1, and its output signal is equal to the memory access signal 2.
0 and the AND gate 7 by the control of the NOT gate 21. It is applied to the memory 22 via the OR gate 8. The data thus read from the memory 22 is checked for Hamming code by the error detection circuit 8, and if there is a jJ correctable error, a correctable error error 9 is output.

The above error data is subsequently input to the error correction circuit 12, where 1-bit errors are corrected. Then, the memory address where the error occurred is input to the error address register circuit 13 via the AND gate 10, and the above-mentioned corrected data is input to the corrected data register circuit 14 via the AND gate 11 and stored. .

Pull! When the memory 22 is accessed, the address comparison circuit 15 compares the contents of the error address register circuit 13 with the memory address signal 19. If they match, by closing the AND gate with NOT gate 16, the modified data register times instead of the data read from memory 22! ! The contents of 14 are AND gate 17. It is input to the microprocessor l via the OR gate 5. 2, that correct data has been transferred to the microprocessor 1 in place of the incorrect data, without prolonging the cycle time.

Note that since the data in the memory 22 may be rewritten at any time by the microprocessor program, the memory address generation circuit 6 constantly monitors the memory write signal 18 output from the microprocessor l. When the signal is given, the operation of the counter circuit is stopped, and the memory address signal 19 is output, so that the contents of the memory address 7'L''r: are read out just before the cycle of the westward operation of one memory. .Thus, it is possible to always check the memory of the prayer. 3) After completion of the recycle, the above-mentioned rotation is performed again.The above-mentioned error detection and correction operation continues.

The number of stages of the error address register circuit 13 and the old correct data register circuit 14 is determined by the number of stages after the occurrence of a memory error (Iff, b, and: i after the correct data is transmitted to the microprogram 1. If the data register circuit l+2 is cleared, the Hg of memory 22 will be cleared.
It is good enough that it can be ignored compared to the standard. If a memory error occurs frequently at 4M times, which causes the error address register circuit 13 to overflow, it is possible to make it uncorrectable (machine error is displayed). Furthermore, if a memory error frequently occurs in a specific pit at a specific memory address, the contents of the 1% positive data register circuit 14 are stored in the memory. In this case, it goes without saying that the operation should be performed outside the memory usage period.

In the above embodiment method, it is necessary to check the data at all addresses in the memory and prepare the corrected data before the microprogram starts operating, but this can be done, for example, when the device is powered down. This can be done after waiting for the data to be flushed into the memory to be completed.

〔Effect of the invention〕

As described above, according to the present invention, by using the free time after the microprocessor in the microprocessor system finishes reading instructions or data from the memory, the process continues during the subsequent cycle time during this period. Since the new technology detects and corrects errors in instructions or data that are processed, it is possible to detect and correct memory errors without extending the cycle time, making it possible to realize a high-speed, highly reliable microprocessor system. This has a remarkable effect. Furthermore, the range of applications is wide, such as rewriting to the memory using the above-mentioned free time.

[Brief explanation of the drawing]

FIG. 1 shows a microprocessor that is an embodiment of the present invention.
FIG. 2 is a block diagram of the system. l: Y Iku o bu o 7+, 2.4.7.10.11
゜17: AND gate, 3, 5 = OR gate, 6: 7 Mori address generation circuit, 8: Error detection circuit, 9: Correctable error signal, 12: 'Error correction circuit, 13: Error address register circuit, 14: ( I positive data register circuit, 15 near address comparison circuit, 16, 21: Not gate, 18: Memory write signal, 19: Memory address signal, 2Q: Memory access @ number, 22: Memory.

Claims (1)

[Claims] A memory error detection and correction method in a microprocessor system including a microprocessor and a memory that stores a microprogram reads the contents of the memory during a period when the microprocessor is not accessing the memory, and detects and corrects the error. and a means for storing the memory address where the error occurred and the corrected data, and each time the microprocessor executes a memory read, it compares it with the above address, and if the two match, it reads it from the memory. A memory error detection/correction method characterized in that the corrected data is input to a microprocessor instead of the corrected data.