JPS60121709A - Power source device for magnetic erase - Google Patents

Abstract

PURPOSE:To accomplish uniform magnetic-erasing pattern and obtain the high effect of magnetic erase by prevention of the variation in action by method wherein the switching action is speeded up by controlling the action of a polarity-switching circuit according to the magnetic erasing patterns stored in a memory circuit. CONSTITUTION:On the input of the magnetic-erase starting signal, an initial address signal specified 22 is fed out 20 to a memory 18; then, the memory 18 performs the polarity switching 14 of a constant voltage current rectified 12 by the operating signal of a corresponding address, resulting in conduction to an excitation coil 16. On the other hand, when the time-specifying signal of the memory 18 amounts to a specific counted value by counting 24 clock pulses 26, a ripple carry is generated 24, and an address altering signal 28 is generated and then alters 28 an address setting 20 and the counted value 24. The memory 18 emits action stopping signals at the time of finish of the magnetic-erasing pattern corresponding to a received address signal, and stops the address setting 20 and the current switching to the coil 16. This construction enables the prevention of the high-speed switching of polarity in the magnetic-erasing coil current and the variation of the switch period patterns, and thus an effective magnetic- erasing device can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention supplies direct current of a constant voltage to an excitation coil or the like of an electromagnetic chuck alternately in forward and reverse directions while gradually decreasing the polarity switching period.
The present invention relates to a demagnetization power supply device used in a so-called loop attenuation demagnetization method in which demagnetization is performed by this method.

In a conventional power supply device of this kind, a constant voltage DC current output from a rectifier circuit is supplied to an excitation coil through a polarity switching circuit including a pair of relays or the like. The operation of the polarity switching circuit is conventionally controlled by a limit switch that controls energization to the relay and a rotating cam that controls opening and closing of the limit switch, or by a rotating plate having a conductive band separated in the circumferential direction, and a rotating plate having a conductive band divided in the circumferential direction. This was done by a switch mechanism consisting of a brush that came into contact with a rotating plate.

However, by controlling the switching cycle using a rotating body such as the rotating cam or rotary plate described above, it is not possible to switch the polarity of the current supplied to the excitation coil at high speed, and therefore a good demagnetizing effect cannot be expected. I can't. Further, in the conventional power supply device, the switching cycle pattern is determined by the rotating cam or the rotating plate on which the conductive band is formed, so the switching cycle pattern is determined depending on the processing accuracy of the rotating cam or rotating plate. Variations were observed, which could cause variations in the demagnetization effect. Furthermore, in the conventional power supply device, in order to change the switching period to enhance the demagnetization effect, it is necessary to replace the rotating cam or the rotating plate, and therefore the switching period pattern cannot be easily changed. Ta.

An object of the present invention is to achieve a relatively simple configuration with excellent demagnetization effect by speeding up the polarity switching of the current supplied to the excitation coil for demagnetization and preventing variations in the switching cycle pattern. The purpose of the present invention is to provide a demagnetizing device.

The present invention basically consists of alternately switching the polarity of a DC current output from a rectifier circuit using a polarity switching circuit and gradually decreasing the period in order to generate an attenuated alternating magnetic field for demagnetization in an excitation coil. The degaussing power supply device for supplying power to the excitation coil includes a memory circuit that stores at least one degaussing pattern and sends an operation signal to the polarity switching circuit, and a memory circuit that sends an address designation signal designated by input of a degaussing start signal to the memory circuit. an address setting circuit that sequentially advances an addressing signal sent to the circuit and outputted to the memory circuit in response to a clock pulse from a clock pulse generating circuit to a subsequent addressing signal, and after the degaussing pattern has progressed, the addressing signal is outputted to the memory circuit. It is characterized in that it is put into a hibernation state by a hibernation signal sent to the address setting circuit.

According to the present invention, by controlling the operation of the polarity switching circuit according to the degaussing pattern stored in the memory circuit, the operation of the polarity switching circuit can be made faster and uniform by preventing variations in the operation. Therefore, it is possible to achieve a uniform demagnetization pattern with a relatively simple configuration, and a high demagnetization effect without variation can be obtained.

The features of the invention will become more apparent from the following description of the illustrated embodiments.

FIG. 1 shows a diagram of a degaussing power supply device IO according to the present invention. The power supply device IO includes a rectifier circuit 12 for rectifying alternating current AC, and a polarity switching circuit 14 for switching the polarity of a constant voltage DC current output by the rectifier circuit. The DC current whose polarity is alternately switched is supplied to, for example, an excitation coil 16 of an electromagnetic chuck.

The switching circuit 14 is controlled by an operation signal outputted from a memory circuit 18, and the memory circuit stores a one-way energization time to the excitation coil 16 and a one-way current supply time to the excitation coil 16, with a current supply stop time to the excitation coil 16 in between. Upper positions for a plurality of degaussing patterns that determine the gradually decreasing ratio of the energization time in the reverse direction are stored for each address. It is possible to eliminate the need for the current supply suspension time.

The memory circuit 18 receives an address signal from the address setting circuit 20, and upon input of the degaussing start signal, the address setting circuit sends the initial address signal designated by the initial address selection means 22 for selecting a degaussing pattern to the memory circuit 18. send to The memory circuit 18 sends an operation signal of the address corresponding to the initial address signal to the polarity switching circuit 14, and also sends a time designation signal of the address to the counter circuit 24.

The counter circuit 24 receives clock pulses from the clock pulse generation circuit 26, and when the number of clock pulses reaches a value specified by the time designation signal from the memory circuit 18, the counter circuit 24 receives the clock pulse from the address change signal generation circuit 28. Send Ripple Carry.

When the circuit 28 receives a ripple carry, the address change signal generating circuit sends an address change signal to the address setting circuit 20 and the counter circuit 24, respectively.

The address setting circuit 20 that has received this address change signal sends an address signal to the memory circuit 18 in order to execute the selected one degaussing pattern. The memory circuit 18 receives this address signal, and sends an operation signal of a new address following the address corresponding to the initial address signal to the polarity switching circuit 14, and also sends a time designation signal of the new address to the counter circuit 24. send to As described above, this counter circuit 24 sends a ripple carry to the circuit 28 when the number of clock pulses reaches the value specified by the new time designation signal.

By repeating the above-described circuit operation, the polarity switching circuit 14 changes the current supply to the excitation coil 16 according to the selected degaussing pattern stored in the memory circuit 18, with interruptions in the supply of current to the excitation coil 16. It operates to gradually reduce the switching period of the forward and reverse direct current. When the address corresponding to the address signal received from the address setting circuit 2o reaches the end r of the degaussing pattern, the memory circuit 18 sends an operating body stop signal to the address setting circuit 2o, and stops the current supply to the excitation coil 16. will be stopped.

FIG. 2 shows an electric circuit of the degaussing power supply device 10 according to the present invention, and the electric circuit includes an excitation coil 16 of the electromagnetic chuck in order to enable the magnetic body to be attracted by the electromagnetic chuck. A circuit for supplying a constant-voltage DC power source is incorporated into the device, which will be explained below with reference to FIG.

The rectifier circuit 12 is connected to an alternating current power supply AC via a pair of power switches SW. The rectifier circuit 12 is a rectifier element SR.
A surge absorbing varistor ZNR is provided between the input terminals of the element.

Further, between one side of the power switch SW and the input terminal of the rectifier circuit 12, an a contact CR of an AC cutoff relay CR is connected.
1a is inserted, and a surge absorbing element RI is inserted into the contact point.
+ CI is connected.

A contact Msl of a relay Ms constituting a polarity switching circuit 14 is inserted into the output side of the rectifier circuit 12. In the illustrated example, relay Ms is a contact CFi of main relay CR2.
2 is an auxiliary relay Ms that operates by closing and connecting a,
A surge absorbing element R is attached to the a contact CR2a of the main relay CR2.
2, C2 is connected. A contact C of main relay CR2
By making R2a the a contact Ms1, the auxiliary relay Ms
can be made unnecessary. Between the polarity switching circuit 14 and the excitation coil 16, surge absorbing elements R3, C3,
SA is connected.

Further, a conventionally well-known constant voltage power supply circuit 30 is connected to the alternating current power supply AC via the pair of power switches SW. The constant voltage power supply circuit 30 includes the relays CR,
, CR2, memory circuit, 18, address setting circuit 20
, initial address selection 1 stage 22. A predetermined operating current is supplied to each circuit including the counter circuit 24, the clock pulse generation circuit 26, and the address change signal generation circuit 28.

The initialization setting circuit 32, which is one of the circuits that receives the operating current from the constant voltage power supply circuit 30, includes a pull-up resistor R4, a diode D, and a capacitor C4. The circuit 32 is configured such that the voltage between the terminals of the capacitors C and l after a predetermined time has elapsed after the power switch SW is turned on is "
By changing from the L'° level to the "H" level, this "H" level signal, ie, the "1" signal, is sent to the signal generating circuit 34 in order to initialize the entire device.

This signal generation circuit 34 receives the rOJ signal from the operation switch 36 as a degaussing start signal by switching the switch. In addition, the operation switch 36 sends a "0" signal to the forward excitation signal generation circuit 38 in order to attract and hold the magnetic material by the chuck. This operation switch 36 is a switch that is mechanically held in the positive excitation position when operated from the neutral position to the positive excitation position, and automatically returns from the demagnetization position to the neutral position when operated to the demagnetization position. is desirable.

The signal generation circuit 38 includes a pull-up resistor R5, a delay element R6+S, a waveform forming NOT gate element IC, and an oven collector NOT gate element C2. When the signal generation circuit 38 receives a "0" signal from the operation switch 36 by operating the operation switch 36, it sends a halt signal, that is, an rQJ signal, to the signal generation circuit 34 from the output terminal of the gate element IC2, and also sends a halt signal, that is, an rQJ signal, to the signal generation circuit 34 from the output terminal of the gate element IC2. Send a "0" signal to IC3 (indicated by a negative logic NOR gate element symbol in the figure). The gate element IC
3, by receiving the "o" signal, the NOT gate element IC4 and the open left output type part operating element ■C
5, the relay CR is driven. Further, the drive relay cR7 is not driven and the contact Ms1 of the auxiliary relay Ms is held at one closed contact.

, Therefore, after turning on the switch SW, the operation switch 3
6 to the forward excitation position, the relay C
R, is driven, thereby supplying a constant voltage direct wave current to the excitation coil 16 of the chuck, and generating a constant magnetic field for holding the magnetic material in the chuck.

By operating the operation switch 36 to the demagnetizing position, the
” The signal generating circuit 34 receives the signal.

A pair of waveform shaping NAND gate elements IC6゜IC,,
(IC6 is shown by a negative logic NOR gate element symbol) and a monostable multivibrator 42. flip flop 40
One input terminal 40a receives the output signals from the signal generation circuit 38 and the initialization setting circuit 32, and the other input terminal 40b receives the output signal from the operation switch 36. The flip-flop 40 has one input terminal 40a.
When the rlJ signal is received at the other input terminal 40b,
When it receives a "0" signal, it outputs a "1" signal to one output terminal 40c, and outputs an "O" signal to the other output terminal 40d. This output does not change even if the input signal of the other input terminal 40b changes to the rlJ signal as long as the input signal of one input terminal 40a does not become "0", and the flip-flop 40 does not change to the input terminal 40a. By receiving a pause signal, that is, a "0" signal from the positive excitation signal generation circuit 38 and the memory circuit 18, the output signal is inverted. Therefore, when a degaussing start signal, that is, an "O" signal is received from the operation switch 36 while receiving the rlJ signal from the signal generating circuit 38, "1" is sent to one output terminal 40c.
” signal and outputs the rQJ signal to the other output terminal 40d. This output state is self-maintained and chattering of the switch 36 is prevented.

When the vibrator 42 receives the rlJ signal from the flip-flop 40 at its input terminal B, it emits a positive single pulse from its output terminal Q, and also emits a negative single pulse from its output terminal Q. The width of each single pulse is the resistance R
7 and capacitor C6.

The "0" signal output from the output terminal 40d of the flip-flop 40 is sent to the memory circuit 18, and the single negative pulse output from the output terminal Q of the vibrator 42 is sent to the address setting circuit 20.

In the illustrated example, the address setting circuit 20 includes NAN, D gate elements IC8, and IC9 (the gate element IC8 is a negative logic NO
two 7-up-down counters I connected in series to the phase 1 through the phase 1 (denoted by the symbol R) and having four input terminals A-D and four output terminals QA"QD respectively;
, J, pull-up resistors R8, R9 and two DIP switches DS constituting the n-n period address selection means 22, and a NAND gate element IC. (denoted by a negative logic NOR symbol) and a delay element RIO, C7. The two up-down counters described above can be made into one up-down counter.

A DIP switch DS is connected to two input terminals C and D of the up/down counter J, and a constant voltage Vcc is applied to the other input terminals A and H. Further, a constant voltage Vcc is applied to input terminals A-D of the up-down counter I. Therefore, the two DIs
The address setting circuit 2 is set by operating the P switch DS.
0 can be selected from four types of starting addresses. The output terminals Q8-Qn of the up-down counter J are connected to the corresponding address buses A4-A7 of the memory circuit 18, and the output terminals Q8-Q of the up-down counter I are connected to the corresponding address buses A4-A7 of the memory circuit 18.
D is the corresponding address bus Ao-A of the memory circuit 18
The output terminals of the up-down counters I and J connected to 3, that is, the output terminals of the address setting circuit 20, QA"QD, Q^~QD are (1111, 1111)
, and can take on states up to (0000, 0000).

Both up/down counters I and J receive the single negative pulse from the output terminal Q of the vibrator 42 at their respective ] terminals, and pass the single pulse to the delay element R.
After a predetermined time delay caused by IO and C7, the pulses are received as a single positive pulse at the respective CK terminals via the gate elements IC9 and gate elements IC and o, respectively. Both counters I and J receive the above-mentioned single pulses at their respective input terminals A-D,
An output signal corresponding to the signal set to A-D is output to each output terminal QA"QD, QA"Qn.

Further, the up/down counter I is connected to the CK terminal via the gate element IC,0 to the address change signal generating circuit 2.
When the address change signal from 8 is received, the output (1111) from the output terminal QA"QD is subtracted every time the signal is received.
When =Qn becomes (oooo), a negative pulse is emitted from the positive terminal of the up-down counter each time the address change signal is inputted, and as a result, the up-down counter J outputs an output from its output terminal QA''QD. F (+11
1) Subtract.

Therefore, when the address setting circuit 20 receives a single negative pulse at both terminals and receives a "1" signal at the CK terminal of the up/down counter I, the address setting circuit 20 selects the selected leading address signal specified by the DIP switch DS. Its output terminal QA”QD.

QA"QD to each address/Hess Ao-A7 corresponding to the memory circuit 18, and up/down counter I
When the rlJ signal is received only at the CK terminal of the DIP switch DS, a new address signal following the first address is issued to the address buses A0 to A7 in order to perform one degaussing pattern cut out by the DIP switch DS.

The memory circuit 18 is composed of an IC in the illustrated example, and is connected to the output terminals QA to Qn and QA- of the address setting circuit 20.
It has eight address buses Ao-A corresponding to Qn and eight data buses D, -D, and when its σ terminal receives the rQJ signal from the output terminal 40d of the flip-flop 40, the address setting circuit The address signal from 20 is read from address buses A and -A7, and information corresponding to the address specified by the address bus signal is output to data buses D and -D. The memory circuit 18 includes
Information about a plurality of degaussing patterns, for example four, is input, and drive signals for relays CR, CR2 and CR3 are output as "0" signals from the upper 3-bit data bus Ds-D7, respectively. . The drive signal of the data bus D7 is the a contact CRI of the relay CR.
It is input to the IC 3 to close a. The drive signal of the data bus D6 is applied to an open collector output type part movement element IC, in order to switch the contact Msl of the auxiliary relay Ms.
, and as the output voltage of the element decreases, a direct current is passed to the main relay CR2, thereby energizing the relay. Further, the drive signal of the data bus D5 is input to the open collector output type movement element IC,2, thereby exciting the relay CR3. This relay CR3 is a backup relay for operating a device loaded externally to the device 10 in synchronization with the relay CRI of the polarity switching circuit 14, and can be made unnecessary. Further, a "0" signal is emitted from the data bus D4 of the memory circuit 18 as a stop signal of the operating body, and this stop signal is transmitted to the device 10.
The signal is inputted to the one input terminal 40a of the flip-flop 40 in the signal generating circuit 34 via the NOT gate element Id and the open collector NOT gate element IC, 4 in order to put the signal in a dormant state. Time data is output from the F-order 4-bit data buses D0 to D3 of the memory circuit 18 to the counter circuit 24.

A counter circuit 24 receives one-time data, that is, a time designation signal, from the data bus Do-03 of the memory circuit 18.
are input terminals A-D corresponding to each data bus D0-D3
A counter 44 is provided. The hebrator 42
The single pulse of the pressure emitted from the output terminal Q of is N
OT gate element IC, 1, NAND gate element IC, 6
(indicated by a negative logic NOR symbol) and is sent as a negative single pulse to the ■ terminal of the counter 44 by passing through the NOT gate element IC, 7, and the delay element R1.
After passing through the NAND gate element IC,8 with a predetermined time delay due to l+08, it is sent to the CK terminal r- of the counter 44 as a single positive pulse. The counter 44 receives the above-mentioned single pulse at both its LD and CK terminals, thereby calculating the time D from the memory circuit 18.
0-D3 are read into its input terminals A-D.

The counter 44 also receives a NAND gate element I"Cl9 (indicated by a negative logic NOR symbol) from the clock pulse generation circuit 26 and the gate element I"Cl9 (indicated by a negative logic NOR symbol) at its CK terminal.
C, , and when the number of clock pulses reaches the value read from the input terminals A-D, the counter 44 sends a ripple carry, which is a negative pulse, from its open terminal to the address change signal generation circuit. Send to 28th.

The time designation signals outputted to the counter 44 from the f-order 4-beat data bus DO to D3 of the memory circuit 18 are (0000) to (1111), and for example, if the counter 44 corresponds to the lO propulsion method 2', When the time designation signal (0010) is read, the counter receives two clock pulses from the clock pulse generation circuit 26, that is, after 2T when the oscillation period of the clock pulse is T, the address change signal generation circuit 28 Sends a ripple carry.

Therefore, depending on the time information of data buses D0 to D3, 15
It is possible to set the time up to T, and if a longer time setting is required, the signals of the upper 4 bits of data buses D4 to D7, which are not concerned with the time setting, are continued in the subsequent addresses to fix the insufficient time. In order to compensate for this, a 4-bit F-order time designation signal is provided. -D3 can be set to a desired value.

The clock pulse generation circuit 26 includes a multivibrator 46, and as long as its input terminal 1B receives the "1" signal and its input terminal 2B receives the rlJ signal from the output terminal 40c of the flip-flop 40, the output terminal IQ
A clock pulse is then sent to the CK terminal of the counter 44 via the gate element IC+9+ICl3. The oscillation period T of this clock pulse is determined by the resistor R13.

It is determined by RI4 and capacitor C8° + CI1, but as shown in the figure, the multivibrator 48 includes noise filters RFC, , RFC2, C,2.

By adding a variable resistor 50 via Cl3 and increasing or decreasing the pulse interval by adjusting the variable resistor, the oscillation period T can be adjusted to, for example, between 0.01 seconds and 0.1 seconds.
■It can be strange.

The clock pulse generation circuit 26 is connected to the input terminal 2B.
“0” is output from the output terminal 40c of the flip-flop 40.
The oscillation is stopped by receiving the signal 1-S, and the address change signal generation circuit 28 inputs rO to the input terminal IH.
Oscillation is temporarily stopped by receiving the address decrement signal, which is the J signal.

The address change signal generation circuit 28 includes a monostable multivibrator 48, and has a counter 44 at its input terminal B.
When receiving the ripple carry from the output terminal Q, a negative pulse signal with a constant width determined by the resistor RI2 and the capacitor C9 is sent as an address change signal, that is, an address decrement signal, to the up/down counter Send it to the CK terminal.

Upon input of this address decrement signal, the address setting circuit 20 operates to output a subsequent address signal to the memory circuit 18' as described above.

Further, the address decrement signal is sent to the counter 44 via the gate elements ic,6, IC1, , IC, .
The counter 44 reads the subsequent new time designation signal output from the memory circuit 18.

Furthermore, the address decrement signal is sent to the long end rIB of the pulse generating circuit in order to temporarily stop the oscillation of the clock pulse circuit 26.

In the device according to the present invention, as described above, t
) By operating the operation switch 36 in item 11 to the forward excitation position, the rQJ signal is sent to the gate element Ic3.
This drives the relay CR, and the auxiliary relay M
s can be excited and its a contact CRI a can be closed. Further, since the [OJ times signal and the rlJ signal are outputted to the output terminals 40c and 40d of the flip-flop 40 in the signal generation circuit 34, respectively, the oscillation of the clock pulse circuit 26 is stopped and the memory "l" from data bus D6 of circuit 18
A signal is output, which causes contact Ms of auxiliary relay Ms
1 is held in the closed position on the ~ side.

Therefore, by operating the switch 36, a constant DC current can be supplied to the excitation coil 16 of the chuck, thereby generating a constant magnetic field in the chuck, which causes the chuck to attract and hold the magnetic material. be able to.

Further, when removing the magnetic material from the chuck, a degaussing pattern appropriate for erasing the residual magnetism of the chuck is determined by operating the DIP switch DS of the initial address selection means 22. Thereafter, by operating the operation switch 36 to the demagnetizing position, the respective outputs of the output terminals 40c and 40d of the flip-flop 40 can be inverted. This flip flop 4
Due to the inversion of the output of 0, the address setting circuit 20 becomes DI
One leading address designation signal selected by the P switch DS is output to the memory circuit 18, and the memory circuit outputs (+111
), that is, outputs the signal "F' in hexadecimal notation, and also outputs (+111), that is, 1, to the data buses D3 to D0.
Outputs the signal "Foo" in hexadecimal notation. As a result, the relays CRI, CR2, and CR3 are kept in a non-excited state for 15T seconds specified by the data buses D3 to D0, and the energization to the excitation coil is stopped. be done.

When the number of clock pulses from the clock pulse generation circuit 26 reaches 15, that is, after 15T seconds, the counter circuit 24 issues a ripple carry to the address change signal generation circuit 28, and thereby the address change signal generation circuit 2
8 issues an address change signal. In response to this address change signal, the address setting circuit 20 outputs to the memory circuit 18 an address designation signal subsequent to the start address signal, that is, an address designation signal obtained by subtracting rlJ from the start address. As a result, +iif memosa memory-
For example, the circuit 18 has data buses D7 to D4 (Ooll
), that is, outputs a “3” signal in hexadecimal notation,
It also outputs (+111), that is, a signal of °F in hexadecimal notation, to the data buses D3 to Do. As a result, the relay CR and the relay CR2 are excited for 15T seconds. Said relay CR.

The relay contact CRI a is closed due to the excitation of the relay CR2, and the contact Ms of the relay Ms is closed due to the excitation of the relay CR2.
l is held in the other closed position. As a result, a reverse current flows through the excitation coil 16 for 15T seconds.

The following information is sequentially stored in the memory circuit and in the DIP.
Along the degaussing pattern selected by switch DS,
For example, as shown in FIG.
The operation of R2 is controlled, and the excitation coil 16 is supplied with a constant value of current whose polarity is switched and whose switching period gradually decreases;
As a result, the residual magnetism of the chuck is completely erased.

When the degaussing pattern is completed, the rlJ signal from the data bus D4 of the memory circuit 18 places the device 10 in a sleep state.

Next, Tables 1 and 2 illustrate data stored in the memory circuit 18 for different degaussing patterns.

1: Two-color base - J EF 3F (repeat from here on) μD 3C ECBF EB B4 EA FF B9 F4 E 8 76 B7 FF B6 F4 E 5 35 B4 BF B3 B4 B2 FF EI F4 E 0 74 DF FF DE F4 DD 33 DCBF DB B4 DA FF 09 F4 D 8 72 07 FF D6 F4 D5 31 04 BF D3 B4 D2 FF DI F4 Do FF 0F F4 CE EF , -1/Hess = ) Table 1゜Data No. 2 (Comments omitted) Table 2゜ Address - 1 ta L upper yz-j Yonomu 52: x 7" -
Noah F FF 67 7F 4F 72 7E F4 66 FF 4E FF 7D 3F 65 F4 40 F4 7C3F 64 3F 4C31 783F 63 8F 4B BF 7A 3D 62 B4 4A B4 79 BF 61 FF 49 F F 78 B4 60 F4 48 F4 77 FF 5F 76 47 FF 76 F4 5E FF 46 F4 75 7F 5D F4 45 EF 74 7F 5C35 (end r) 73 7F 58 BF 72 74 5A 84 71 FF 59 FF 70 F4 58 F4 6F 3F 57 74 6E 3F 56 FF 6D 3C55F4 6CBF 54 33 68 B4 53 8F 6A FF 52 B2 S3 F4 51 FF 68 7F 50 F4 The addresses and data in each of the above tables are expressed in hexadecimal notation. For example, the address FF is (1111, 1
111), and the data FFs correspond to data buses D7~
D4. The outputs of D3 to D0 correspond to (II+, +111). Therefore, for example, address FF in Table 1
, FE data FF.

According to F4, the hibernation state is specified by the value "F" of the 4 bits in the 1st place, and this hibernation state is the sum of the 4 bits in the 1st place, that is, the values of the data buses D3 to Do, or 20T seconds (T- is the above-mentioned value). The clock pulse oscillation period) is maintained for the duration of the clock pulse oscillation period).The subsequent reverse excitation state is determined by data 3F, 3F, 3F, 3D.
It is specified by the value "3" of the upper 4 bits of each of the data buses D7 to D4 (0011), and the time is the sum of the lower 4 bits, ie, 61 T seconds.

Therefore, in order to perform the degaussing pattern according to Table 1 stored in the memory circuit 18, the initial address (F , F
) That is, both DIs of the initial address selection f1 stage 22 are used to specify (1111, 1111) to the address setting circuit 20.
After opening the P switch DS, press the operation switch 36.
All you have to do is move it to the demagnetized position. In addition, in order to perform the degaussing pattern according to Table 1 and Table 2, one DIP corresponding to the D input terminal of the up/down counter J is required to specify the initial address (7, F), that is, (0111, 1111) to the address setting circuit 20. It is sufficient to close only the switch DS.

According to the degaussing device 10, as described above, it is possible to select the optimal degaussing pattern from a plurality of degaussing patterns only by operating the DIP switch DS. Also,
Since the control of the relay for switching the current supplied to the excitation coil is electrically controlled based on information in the memory circuit, there is no variation in the selected demagnetization pattern, and polarity control at high speeds. Since switching is possible, a uniform and extremely good demagnetizing effect can be achieved. Furthermore, by setting the pulse generation period of the clock pulse generation circuit to f, it is possible to increase or decrease the degaussing time for one selected degaussing pattern.
This makes it possible to obtain an optimal demagnetizing effect.

Instead of storing a plurality of degaussing patterns in parallel in the memory circuit 18, a single degaussing pattern is stored in the memory circuit 18, and the degaussing start address of the degaussing pattern is selected as an initial address. A plurality of degaussing patterns can be selected by selecting by the means.

Furthermore, by storing a single degaussing pattern in the memory circuit 18, eliminating the need for the initial address setting means, and fixing the degaussing start address, that is, the leading address designated by the address selection means, it is possible to perform a single degaussing pattern. Patterns can be reproduced with high repeatability without variation, and as a result, a more uniform and better demagnetizing effect can be obtained than in the past.

Further, as the polarity νJ switching circuit 14, an electrical νJ switching circuit such as a conventionally well-known inverter using transistors can be used.

In the above, an example was explained in which the upper 4 bits of the data bus of the memory circuit were used as control state information signals, and the lower 4 bits were used as time information signals, but it is clear from the explanation of Table 1 above. By storing the same control state as the previous address in the subsequent address, it is possible to control the duration of each control state. The same control state as in the previous address is stored in an address, and the duration of each control state can be controlled by the number of addresses in which the same control state continues. in this case,
The address of the memory circuit is passed through the gate element JC1o of the address setting circuit 20 to the CK of the up/down counter.
A clock pulse from the clock pulse generation circuit applied to the terminal advances the puzzle to the next address every unit time. This eliminates the need for the counter circuit 24, and since the clock pulses from the clock pulse generation circuit act as address change signals, the address change signal generation circuit becomes unnecessary, thereby further simplifying the configuration. It becomes a Noh performance.

[Brief explanation of drawings]

FIG. 1 is a diaphragm showing a demagnetizing power supply device according to the present invention, FIG. 2 is an electric circuit diagram of the demagnetizing device according to the present invention, and FIG. 3 is a diagram of the relay and excitation coil shown in FIG. 2. It is a time chart showing an excitation state. 12: Rectifier circuit, 14: Polarity switching circuit, 16: Excitation coil, 18: Memory circuit, 20 Near address setting circuit, 22: Initial address selection means, 24: Counter circuit, 26: Clock pulse generation circuit, 28 Near address change signal generation circuit. Agent Patent Attorney Nobuyuki Matsunaga

Claims (1)

[Claims] In order to generate an attenuated cross-width magnetic field for demagnetization in the excitation coil, a polarity switching circuit alternately switches the polarity of the DC current output from the rectifier circuit and gradually decreases the Gino switching period to supply the DC current to the excitation coil. A degaussing power supply device comprising: a memory circuit that stores at least one degaussing pattern and sends an operation signal to the polarity switching circuit; and a memory circuit that sends an addressing signal designated by input of a degaussing start signal to the memory circuit and clocks an address setting circuit that receives a clock pulse from a pulse generation circuit and sequentially advances an addressing signal outputted to the memory circuit to a subsequent addressing signal; A degaussing device characterized in that it is put into a hibernation state by a transmitted hibernation signal.