JPS6211484B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a demagnetization power supply device used in the so-called loop attenuation demagnetization method, in which a direct current of a constant voltage is alternately supplied in forward and reverse directions by gradually decreasing the polarity switching period to the excitation coil of an electromagnetic chuck, thereby performing demagnetization. In a conventional power supply device of this kind, a constant voltage DC current output from a rectifier circuit is supplied to an excitation coil through a polarity switching circuit including a pair of relays or the like. Conventionally, the operation of the polarity switching circuit is controlled by a limit switch that controls energization of the relay and a rotating cam that controls opening and closing of the limit switch, or by a rotating plate having a conductive band separated in the circumferential direction, and a rotating plate having a conductive band separated in the circumferential direction. This was done by a switch mechanism consisting of a contacting brush. However, by controlling the switching cycle using a rotating body such as the rotating cam or rotating plate described above, it is not possible to switch the polarity of the current supplied to the excitation coil at high speed, and therefore it is not possible to expect a good demagnetizing effect. Can not. Furthermore, in the conventional power supply device, the switching cycle pattern is determined by the rotating cam or the rotating plate on which the conductive band is formed, so the switching cycle pattern is determined depending on the machining accuracy of the rotating cam or rotating plate. There were variations in the degaussing effect, which caused variations in the demagnetizing effect. Furthermore, in the conventional power supply device, in order to change the switching period to enhance the demagnetization effect, it is necessary to replace the rotating cam or the rotating plate, and therefore, it is not possible to easily change the switching period pattern. Ta. An object of the present invention is to achieve a relatively simple configuration with excellent demagnetization effect by speeding up the polarity switching of the current supplied to the excitation coil for demagnetization and preventing variations in the switching cycle pattern. The purpose of the present invention is to provide a demagnetizing device. Basically, the present invention involves alternately switching the polarity of a direct current output from a rectifier circuit using a polarity switching circuit and gradually decreasing the period, in order to generate an attenuated alternating magnetic field for demagnetization in an excitation coil. A degaussing power supply device for supplying power to an excitation coil includes a memory circuit that stores at least one degaussing pattern and sends an operation signal to the polarity switching circuit, and a memory circuit that sends an address designation signal designated by input of a degaussing start signal. and an address setting circuit that sequentially advances an addressing signal outputted to the memory circuit in response to a clock pulse from a clock pulse generation circuit to a subsequent addressing signal, and after performing a degaussing pattern, the address setting circuit is configured to set the address from the memory circuit after performing a degaussing pattern. It is characterized in that it is put into a hibernation state by a hibernation signal sent to the circuit. According to the present invention, by controlling the operation of the polarity switching circuit according to the degaussing pattern stored in the memory circuit, it is possible to speed up the operation of the polarity switching circuit and prevent variations in the operation. It is possible to achieve a uniform demagnetization pattern,
As a result, a high demagnetizing effect without variation can be obtained with a relatively simple configuration. The features of the invention will become more apparent from the following description of the illustrated embodiments. FIG. 1 shows a degaussing power supply device 10 according to the present invention.
is shown in the diagram. The power supply device 1
0 is a rectifier circuit 1 for rectifying alternating current AC
2, and a polarity switching circuit 14 for switching the polarity of the constant voltage DC current output by the rectifier circuit.
The DC current, the polarity of which is alternately switched by the polarity switching circuit, is supplied to the excitation coil 16, for example, to an electromagnetic chuck. The switching circuit 14 is controlled by an operation signal outputted from a memory circuit 18, and the memory circuit stores a one-way energization time to the excitation coil 16 and a one-way current supply time to the excitation coil 16, with a current supply stop time to the excitation coil 16 in between. Upper positions for a plurality of degaussing patterns that determine the gradually decreasing ratio of the energization time in the reverse direction are stored for each address. It is possible to eliminate the need for the current supply suspension time. The memory circuit 18 receives an address signal from the address setting circuit 20, and upon input of the degaussing start signal, the address setting circuit sends the initial address signal designated by the initial address selection means 22 for selecting a degaussing pattern to the memory circuit 18. send to The memory circuit 18 transfers the operation signal of the address corresponding to the initial address signal to the polarity switching circuit 14.
At the same time, a time designation signal of the address is sent to the counter circuit 24. The counter circuit 24 is the clock pulse generation circuit 2.
Counter circuit 24 sends a ripple carry to address change signal generation circuit 28 when the number of clock pulses reaches the value specified by the time designation signal from memory circuit 18. When the circuit 28 receives a lip carry, the address change signal generating circuit sends an address change signal to the address setting circuit 20 and the counter circuit 24, respectively. The address setting circuit 20 that has received this address change signal sends an address signal to the memory circuit 18 in order to execute the selected one degaussing pattern. The memory circuit 18 receives this address signal, and sends an operation signal of a new address following the address corresponding to the initial address signal to the polarity switching circuit 14, and also sends a time designation signal of the new address to the counter circuit 24. send to As before, this counter circuit 24 sends a ripple carry to the circuit 28 when the number of clock pulses reaches the value specified by the new time designation signal. By repeating the circuit operation described above, the polarity switching circuit 14 changes the current supply to the excitation coil 16 according to the selected demagnetization pattern stored in the memory circuit 18, with interruptions in the supply of current to the excitation coil 16. It operates to gradually reduce the switching period of the forward and reverse direct current. The memory circuit 18 is
When the address corresponding to the address signal received from the address setting circuit 20 reaches the end of the degaussing pattern, an operation stop signal is sent to the address setting circuit 20, and the current supply to the excitation coil 16 is stopped. FIG. 2 shows an electric circuit of the degaussing power supply device 10 according to the present invention, which includes an excitation coil 16 of the electromagnetic chuck in order to enable the electromagnetic chuck to attract a polar body. A circuit for supplying a constant voltage DC power source is incorporated in the device, which will be explained below with reference to FIG. The rectifier circuit 12 is connected to an alternating current power supply AC via a pair of power switches SW. Rectifier circuit 12
is equipped with a rectifying element SR, and a surge absorbing varistor ZNR is provided between the input terminals of the element. Further, one side of the power switch SW and the rectifier circuit 12
AC cutoff relay CR ₁ a is connected between the input terminal of
A contact CR _1a is inserted, and surge absorbing elements R ₁ and C ₁ are connected to this contact. A contact Ms ₁ of a relay Ms forming a polarity switching circuit 14 is inserted into the output side of the rectifier circuit 12 . In the example shown, relay Ms is the main relay
This is an auxiliary relay Ms that operates by closing the a contact CR _2a of the main relay CR ₂ , and the surge absorbing elements R ₂ and C ₂ are connected to the a contact CR _2a of the main relay CR ₂ . By setting the a contact CR _2a of the main relay CR ₂ to the a contact Ms ₁ , the auxiliary relay Ms can be made unnecessary. Surge absorbing elements R ₃ , C ₃ , and SA ₁ are connected between the polarity switching circuit 14 and the excitation coil 16. Further, a conventionally well-known constant voltage power supply circuit 30 is connected to the alternating current power supply AC via the pair of power switches SW. Constant voltage power supply circuit 30
are the relays CR ₁ and CR ₂ , the memory circuit 18,
Address setting circuit 20, initial address selection means 2
2. A predetermined operating current is supplied to each circuit including the counter circuit 24, clock pulse generation circuit 26, and address change signal generation circuit 28. The initialization setting circuit 32, which is one of the circuits receiving the operating current from the constant voltage power supply circuit 30, includes a pull-up resistor R ₄ , a diode D, and a capacitor C ₄ . The circuit 32 initializes the entire device by changing the voltage across the terminals of the capacitor _C4 from the "L" level to the "H" level after a predetermined period of time has elapsed after the power switch SW is turned on. An H” level signal, that is, a “1” signal is sent to the signal generation circuit 34. This signal generating circuit 34 receives a "0" signal from the operating switch 36 as a degaussing start signal. In addition, the operation switch 36
As a result of the switching operation, a "0" signal is sent to the forward excitation signal generating circuit 38 in order to attract and hold the magnetic material by the chuck. The operating switch 36 is a switch that is mechanically held at the positive excitation position when operated from the neutral position to the positive excitation position, and automatically returns from the demagnetization position to the neutral position when operated from the demagnetization position. is desirable. The signal generation circuit 38 includes a pull-up resistor.
R ₅ , delay element R ₆ , C ₅ , waveform shaping NOT gate element IC ₁ and open collector NOT gate element
Equipped with IC ₂ . When the signal generating circuit 38 receives a "0" signal from the operating switch 36, it sends a stop signal, that is, a "0" signal, to the signal generating circuit 34 from the output terminal of the gate element IC ₂ , and Sends a "0" signal to the NAND gate element (indicated by a negative logic NOR gate element symbol in the figure) _IC3 . Said gate element IC ₃
By receiving the "0" signal, drives the relay CR ₁ via the NOT gate element IC ₄ and the open collector output type driving element IC ₅ . Further, the drive relay _CR2 is not driven and the contact _Ms1 of the auxiliary relay Ms is held at one closed position. Therefore, after turning on the switch SW, by operating the operation switch 36 to the forward excitation position, the relay CR ₁ can be driven, thereby supplying a constant voltage DC current to the excitation coil 16 of the chuck. It is possible to generate a constant magnetic field in the chuck for holding the magnetic material. The signal generating circuit 34 receives a "0" signal by operating the operation switch 36 to the demagnetizing position, and includes a pair of waveform shaping NAND gate elements IC ₆ and IC ₇ (IC ₆
RS flip-flop 40 and monostable multivibrator 42 are provided. One input terminal 40a of the flip-flop 40 receives the output signals from the signal generation circuit 38 and the initialization setting circuit 32, and the other input terminal 40b receives the output signal from the operation switch 36. The flip-flop 40 has one input terminal 40a set to "1".
When receiving a "0" signal at the other input terminal 40b while receiving a signal, it outputs a "1" signal to one output terminal 40c and a "0" signal to the other output terminal 40d. This output is, unless the input signal of one input terminal 40a becomes "0".
Even if the input signal of the other input terminal 40b changes to a "1" signal, the flip-flop 40 remains unchanged.
receives a pause signal, that is, a "0" signal from the positive excitation signal generation circuit 38 and the memory circuit 18 at its input terminal 40a, thereby inverting the output signal. Therefore, the operation switch 36 is activated while receiving the "1" signal from the signal generation circuit 38.
When it receives a degaussing start signal, ie, a "0" signal, it outputs a "1" signal to one output terminal 40c and a "0" signal to the other output terminal 40d. This output state is self-maintained and chattering of the switch 36 is prevented. When the vibrator 42 receives a "1" signal from the flip-flop 40 at its input terminal B, it emits a single positive pulse from its output terminal Q;
It also emits a single negative pulse from its output terminal. The width of each single pulse is determined by the values of resistor R ₇ and capacitor C ₆ . The "0" signal output from the output terminal 40d of the flip-flop 40 is sent to the memory circuit 18, and the single negative pulse output from the output terminal of the vibrator 42 is sent to the address setting circuit 20. In the illustrated example, the address setting circuit 20 is a NAND
Gate elements IC ₈ , IC ₉ (gate element IC ₈ is negative logic
two up-down counters I, J connected in series to each other via the NOR symbol) and each having four input terminals A to D and four output terminals Q _A to Q _D , and an initial address Pull-up resistors R ₈ , R ₉ and two DIP switches DS constituting the selection means 22 and a NAND gate element IC ₁₀
(denoted by the negative logic NOR symbol) and the delay element
It comprises R ₁₀ and C ₇ . The two up-down counters described above can be combined into one up-down counter. A DIP switch DS is connected to two input terminals C and D of the up-down counter J, and a constant voltage Vcc is applied to the other input terminals A and B. Also, up-down counter I
A constant voltage Vcc is applied to input terminals A to D of. Therefore, four types of starting addresses can be selected for the address setting circuit 20 by operating the two DIP switches DS. The output terminals Q _A to Q _D of the up-down counter J are connected to the corresponding address buses A 4 to _{A 7} of the memory circuit 18, and the output terminals Q _A to Q _D of the up-down counter I are connected to the corresponding address buses A ₄ to A 7 of the memory circuit 18. are connected to address buses _A0 to _A3 . Each output terminal of both up-down counters I and J, that is, each output terminal Q _A -Q _D , Q _A -Q _D of the address setting circuit 20, is preset to (1111, 1111), and (0000,
0000). Both up-down counters I and J receive the negative single pulse from the output terminal of the vibrator 42 at their respective terminals, and respectively transmit the single pulse with a predetermined time delay by the delay elements R ₁₀ and C ₇ . It is received as a single positive pulse at each CK terminal via the gate element IC ₉ and gate element IC ₁₀ . Both counters I and J receive the above-mentioned single pulses at their respective terminals A to D and A to D, respectively.
An output signal corresponding to the signal set to D is output to each output terminal Q _A to Q _D and Q _A to Q _D. The up-down counter I also connects the address change signal generating circuit 2 to the CK terminal via the gate element IC ₁₀ .
When receiving an address change signal from 8, the output (1111) from the output terminals Q _A to Q _D is subtracted each time the signal is received. When the output terminals Q _A to Q _D of the up-down counter I reach (0000), a negative pulse is generated from the terminal of the up-down counter every time the address change signal is inputted, and this causes the up-down counter J to output a negative pulse. subtracts the output F(1111) from its output terminals Q _A to Q _D. Therefore, when the address setting circuit 20 receives a single negative pulse at both terminals and a "1" signal at the CK terminal of the up-down counter I, the address setting circuit 20 sets the selected start address signal specified by the DIP switch DS. its output terminals Q _A ~ Q _D , Q _A
~ Q _D to each of the corresponding address buses A ₀ to _{A 7} of the memory circuit 18, and when a "1" signal is received only to the CK terminal of the up-down counter I, one degaussing signal selected by the DIP switch DS is sent. To execute the pattern, a new address signal following the first address is sent to the address buses _A0 to _A7.
emanates from. The memory circuit 18 is composed of an IC in the illustrated example, and is connected to the output terminals Q _A ~ of the address setting circuit 20.
Eight address buses A ₀ corresponding to Q _D , Q _A to Q _D
~ _A7 and eight data buses _D0 ~ _D7 , and when the terminal thereof receives a "0" signal from the output terminal 40d of the flip-flop 40, the address signal from the address setting circuit 20 is transferred to the address bus A. ₀ to _A7 , and outputs information corresponding to the address designated by the address bus signal to data buses _D0 to _D7 . The memory circuit 18 includes
Information about multiple degaussing patterns, for example four, is input, and the upper 3 bits of the data bus
Drive signals for relays CR ₁ , CR ₂ and relay CR ₃ are output as "0" signals from D ₅ to _{D 7} , respectively. A drive signal from the data bus _D7 is input to the IC ₃ to close the a contact CR _1a of the relay CR ₁ . The drive signal of the data bus D ₆ is input to the open collector output type drive element IC ₁₁ in order to switch the contact Ms ₁ of the auxiliary relay Ms, and as the output voltage of this element decreases, direct current is passed to the main relay CR ₂ . , which energizes the relay.
Further, the drive signal of the data bus _D5 is input to the open collector output type drive element _IC12 , thereby exciting the relay _CR3 . This relay CR ₃
is a backup relay for operating devices loaded externally to the device 10 in synchronization with the relay CR ₁ of the polarity switching circuit 14, and this can be made unnecessary. In addition, the data bus of the memory circuit 18
A "0" signal is emitted from D ₄ as an operation stop signal, and this stop signal is sent to the signal generation circuit 34 via the NOT gate element IC ₁₁ and the open collector NOT gate element IC ₁₄ in order to put the device 10 into the rest state. The signal is input to the one input terminal 40a of the flip-flop 40. Memory circuit 1
Time data is outputted to the counter circuit 24 from the data buses D ₀ to D ₃ of the lower 4 bits of 8. The counter circuit 24, which receives time data, ie, time designation signals, from the data buses _D0 to _D3 of the memory circuit 18 includes a counter 44 having input terminals A to D corresponding to each data bus _D0 to _D3 . The single positive pulse emitted from the output terminal Q of the vibrator 42 is connected to the NOT gate element IC ₁₅ ,
It is sent to the terminal of the counter 44 as a single negative pulse through the NAND gate element IC ₁₆ (indicated by a negative logic NOR symbol) and the NOT gate element IC ₁₇ , and is also sent to the terminal of the counter 44 as a negative single pulse by the delay elements R ₁₁ and C ₈ . The counter 4 is output as a single positive pulse by passing through the NAND gate element IC ₁₈ with a time delay of
It is sent to the CK terminal of 4. The counter 44 calculates the time from the memory circuit 18 by receiving the above-mentioned single pulse at both its LD and CK terminals.
Read D ₀ to D ₃ to its input terminals A to D. The counter 44 also has a NAND gate element IC ₁₉ connected to its CK terminal from the clock pulse generation circuit 26.
(indicated by a negative logic NOR symbol) and the gate element IC ₁₈ , and when the number of clock pulses reaches the value read from the input terminals A-D, the counter 44 receives a clock pulse from the negative logic NOR symbol at that terminal. A ripple carry pulse is sent to the address change signal generation circuit 28. The time designation signals output from the lower 4-bit data buses D ₀ to D ₃ of the memory circuit 18 to the counter 44 are (0000) to (1111), and are, for example,
When the counter 44 reads the time designation signal (0010), which corresponds to "2" in decimal notation, the counter receives two clock pulses from the clock pulse generation circuit 26, that is, when the oscillation period of the clock pulses is T, the clock pulse is 2T. Thereafter, a ripple carry is generated to the address change signal generation circuit 28.
Therefore, it is possible to set a time up to 15T using the time information on the data buses _D0 to _D3 , and if a longer time is required, the upper 4 addresses that are not concerned with the time setting can be used in subsequent addresses. The time designation signals D0 _{to D3 of} the lower ₄ bits can be set to desired values in order to continue the signals of the bit data buses D4 to _D7 and compensate for the insufficient time. The clock pulse generation circuit 26 includes a multivibrator 46, which receives a "1" signal at its input terminal IB, and receives a "1" signal from the output terminal 40c of the flip-flop 40 at its input terminal 2B.
As long as a signal is received, a clock pulse is sent from the output terminal 1Q to the CK terminal of the counter 44 via the gate elements IC ₁₉ and IC ₁₈ . The oscillation period T of this clock pulse is determined by resistors R ₁₃ and R ₁₄ and capacitors C ₁₀ and C ₁₁ , and as shown in the figure, the multivibrator 48 includes a noise filter RFC ₁ ,
By adding a variable resistor 50 via RFC ₂ , C ₁₂ and C ₁₃ and increasing or decreasing the pulse interval by adjusting the variable resistor, the oscillation period T can be varied, for example, between 0.01 seconds and 0.1 seconds. It can be done. The clock pulse generation circuit 26 stops oscillation by receiving a "0" signal from the output terminal 40c of the flip-flop 40 at the input terminal 2B, and receives a "0" signal from the address change signal generation circuit 28 at the input terminal 1B. The oscillation is temporarily stopped by receiving an address decrement signal. The address change signal generation circuit 28 includes a monostable multivibrator 48, and its input terminal B
When the ripple carry from the counter 44 is received, a negative pulse signal with a constant width determined by the resistor R ₁₂ and the capacitor C ₉ is output from the output terminal as an address change signal, that is, an address decrement signal, to the output terminal via the gate element IC ₁₀ . It is sent to the CK terminal of down counter I. Upon input of this address decrement signal, the address setting circuit 20 operates to output a subsequent address signal to the memory circuit 18 as described above. Further, the address decrement signal is sent to the counter 44 via the gate elements IC ₁₆ , IC ₁₇ , and IC ₁₈ .
The counter 44 reads the subsequent new time designation signal output from the memory circuit 18. Further, the address decrement signal is applied to the input terminal 1 of the clock pulse generating circuit 26 in order to temporarily stop the oscillation of the clock pulse generating circuit 26.
Sent to B. In the device according to the present invention, as described above, by operating the operating switch 36 to the forward excitation position, a "0" signal is applied to the gate element IC ₃ , thereby driving the relay CR _1. By doing so, the auxiliary relay Ms can be excited and its a contact CR _1a can be closed. Further, since the "0" signal and the "1" signal are output to the output terminals 40c and 40d of the flip-flop 40 in the signal generation circuit 34, respectively, the oscillation of the clock pulse circuit 26 is stopped and the memory A “1” signal is output from the data bus D ₆ of the circuit 18, which causes the contacts of the auxiliary relay Ms to
Ms ₁ is held in one closed position. Therefore, by operating the switch 36, a constant DC current can be supplied to the excitation coil 16 of the chuck, thereby generating a constant magnetic field in the chuck, which attracts and holds the magnetic material on the chuck. can be done. Further, when removing the magnetic material from the chuck, the initial address selection means 22 selects a degaussing pattern suitable for erasing the residual magnetism of the chuck.
is determined by the operation of the DIP switch DS. Thereafter, by operating the operating switch 36 to the demagnetizing position, the flip-flop 40
The respective outputs of the output terminals 40c and 40d can be inverted. This flip-flop 40
Due to the inversion of the output, the address setting circuit 20
One head address designation signal selected by the DIP switch DS is output to the memory circuit 18, and the memory circuit outputs, for example, its data bus D ₇ to _{D 4} .
(1111), that is, a signal "F" expressed in hexadecimal notation is output to the data buses D3 to _D0 , and (1111), that is, a signal "F" expressed in hexadecimal notation is outputted to data buses _D3 to D0. This causes the relays CR ₁ , CR ₂ , CR ₃ to operate for 15T seconds specified by data buses D ₃ to _{D 0} .
is placed in a non-excited state, and power supply to the excitation coil is stopped. When the number of clock pulses from the clock pulse generation circuit 26 reaches 15, that is, after 15T seconds, the counter circuit 24 issues a ripple carry to the address change signal generation circuit 28, which causes the address change signal generation circuit 28 to issue an address change signal. In response to this address change signal, the address setting circuit 20 outputs to the memory circuit 18 an address designation signal subsequent to the start address signal, that is, an address designation signal with "1" subtracted from the start address. As a result, the memory circuit 18 outputs (0011), that is, a "3" signal in hexadecimal notation, to its data buses D ₇ to D ₄ , and outputs (1111) to its data buses D ₃ to _{D 0} , for example. ) In other words, it outputs an "F" signal expressed in hexadecimal notation. This will cause the relay to run for 15T seconds.
energize CR ₁ and said relay CR ₂ ; Excitation of the relay CR ₁ closes the relay contact CR _1a , and excitation of the relay CR ₂ closes the relay contact CR 1a.
Contact Ms ₁ of Ms is held in the other closed position.
As a result, a reverse current flows through the excitation coil 16 for 15T seconds. Thereafter, in accordance with the degaussing pattern stored in the memory circuit and selected by the DIP switch DS, the operation of relays CR ₁ and CR ₂ is controlled, for example, as shown in FIG. 16 is supplied with a constant value of current of switched polarity and decreasing switching period, thereby completing the erasure of the residual magnetism in the chuck. When the degaussing pattern is completed, a "1" signal from the data bus _D4 of the memory circuit 18 places the device 10 in a sleep state. Next, Tables 1 and 2 illustrate data stored in the memory circuit 18 for different degaussing patterns.

【table】

【table】

【table】

【table】

[Table] The addresses and data in each table above are 16
For example, the address FF corresponds to (1111, 1111), and the data FF corresponds to the outputs of data buses D ₇ to _{D 4} and D ₃ to D ₀ (111, 1111). Therefore, for example, the address in Table 1
According to the data FF, F4 of FF, FE, each top 4
The dormant state is specified by the bit value “F”, and this dormant state is determined by the lower 4 bits, that is, the data bus _D3 ~
It is held for a sum of each value of _D0 , that is, 20T seconds (T is the clock pulse oscillation period described above). In addition, the subsequent reverse excitation state is "3", which is the value of the upper 4 bits of data 3F, 3F, 3F, and 3D, that is, the data bus
It is specified by D ₇ to _{D 4} (0011), and the time is the sum of the values of the lower 4 bits, that is, 61T seconds. Therefore, in order to perform the degaussing pattern according to Table 1 stored in the memory circuit 18, the initial address selection means 22 is required to specify the initial addresses F, F, that is, (1111, 1111) to the address setting circuit 20.
After opening both DIP switches DS, the operating switch 36 may be operated to the demagnetizing position. In addition, in order to execute the degaussing pattern according to Table 2, one DIP switch corresponding to the D input terminal of the up/down counter J is required to specify the initial address 7, F, that is, (0111, 1111) to the address setting circuit 20.
Only DS needs to be closed. According to the degaussing device 10, as described above,
The optimum degaussing pattern can be selected from a plurality of degaussing patterns only by operating the DIP switch DS. In addition, since the control of the relay for switching the current supplied to the excitation coil is electrically controlled based on the information in the memory circuit,
Since there is no variation in the selected demagnetization pattern and the polarity can be switched at high speed, a uniform and extremely good demagnetization effect can be obtained. Furthermore, by making the pulse generation period of the clock pulse generation circuit variable, the degaussing time can be increased or decreased for one selected degaussing pattern, thereby making it possible to obtain an optimal degaussing effect. Instead of storing a plurality of degaussing patterns in parallel in the memory circuit 18, a single degaussing pattern is stored in the memory circuit 18, and the degaussing start address of the degaussing pattern is set by the initial address selection means. By making a selection, a plurality of demagnetizing patterns can be selected. Further, by storing a single degaussing pattern in the memory circuit 18, eliminating the need for the initial address setting means, and fixing the degaussing start address, that is, the leading address designated by the address selection means, a single degaussing pattern can be created. The demagnetization pattern can be reproduced with high repeatability without variation, and as a result, it is possible to obtain a more uniform and better demagnetization effect than in the past. Further, as the polarity switching circuit 14, an electrical switching circuit such as a conventionally well-known inverter using transistors can be used. In the above, an example was explained in which the upper 4 bits of the data bus of the memory circuit were used as control state information signals, and the lower 4 bits were used as time information signals, but it is clear from the explanation of Table 1 above. By storing the same control state as the previous address in the subsequent address, it is possible to control the duration of each control state. The same control state as in the previous address is stored in the subsequent address, and the duration of each control state can be controlled by the number of addresses in which the same control state continues. In this case, the address of the memory circuit is determined by the gate element IC ₁₀ of the address setting circuit 20.
The clock pulse from the clock pulse generation circuit is applied to the CK terminal of the up-down counter I through the clock pulse generation circuit, and the address is advanced to the next address every pulse unit time. This eliminates the need for the counter circuit 24, and since the clock pulse from the clock pulse generation circuit acts as an address change signal, the address change signal generation circuit becomes unnecessary, thereby making it possible to further simplify the configuration. becomes.

[Brief explanation of the drawing]

FIG. 1 is a diaphragm showing a demagnetizing power supply device according to the present invention, FIG. 2 is an electric circuit diagram of the demagnetizing device according to the present invention, and FIG. 3 is a diagram of the relay and excitation coil shown in FIG. This is a time chart showing the excitation state. 12: Rectifier circuit, 14: Polarity switching circuit, 16:
Excitation coil, 18: Memory circuit, 20: Address setting circuit, 22: Initial address selection means, 2
4: Counter circuit, 26: Clock pulse generation circuit, 28: Address change signal generation circuit.

Claims (1)

[Claims] 1. In order to generate an attenuated alternating magnetic field for demagnetization in the excitation coil, a polarity switching circuit alternately switches the polarity of the DC current output from the rectifier circuit and gradually decreases the switching period, and supplies the DC current to the excitation coil. The degaussing power supply device includes a memory circuit that stores at least one degaussing pattern and sends an operation signal to the polarity switching circuit, and a memory circuit that sends an address designation signal designated by input of a degaussing start signal to the memory circuit and generates a clock pulse. an address setting circuit that receives a clock pulse from the circuit and sequentially advances an addressing signal output to the memory circuit to a subsequent addressing signal;
A degaussing device characterized in that the degaussing device is put into a hibernation state by a hibernation signal sent from the memory circuit to the address setting circuit after performing the degaussing pattern.