JPS6030130B2 - Variable pulse width one-shot multivibrator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable pulse width one-shot multivibrator, that is, a digital one-shot, which is optimal for use in FM demodulation of a magnetic recording/reproducing device.

A data recorder is generally configured using an FM recording/reproducing method, and has an FM demodulation circuit in the reproducing system.

Then, the FM demodulation circuit transmits the reproduced FM wave to a zero cross detector. Digitize it with a peak detector etc., and use this digitized frequency signal to run a one-shot multivibrator (
The system is configured to trigger a frequency demodulation pulse train (monostable multipipulator), which is passed through a low-pass filter to remove the carrier wave component and become an analog signal.
By the way, general data recorders are configured so that the tape speed can be changed in multiple stages.
In conjunction with changing the tape speed, the output pulse width of the one-shot multivibrator in the FM demodulation circuit must be changed. For this reason, variable pulse width one-shot multivibrators, commonly referred to as digital one-shots, shown in FIG. 1, are already in use. In the digital one-shot multivibrator shown in FIG. 1, a digitized frequency signal corresponding to the FM wave is sent as a trigger signal from the trigger input line to the set terminal S of flip-flop 2 at time t, as shown in FIG. 2A. , the Q output line 3 of flip-flop 2
As shown in FIG. 8, the low level is changed to the high level. At the same time, the Q output of the flip-flop 2 is applied to the clock signal generation circuit 4, the gate is opened, and a clock signal is sent to the output line of the clock signal generation circuit 4 as shown in FIG. 2C. Then, in order to input this clock signal to the counter 5 at the next stage, the counter 5 counts this clock signal. Since the counter output control circuit 6 is provided at the output stage of the counter 5, the counter output is not sent out as is, and the counter output selection signal given from the counter output selection signal generation circuit 7 matches the counter output. At time t2, an output signal is generated as shown in FIG. 2D. The output of the counter output selection signal 6 is given to the reset terminal R of the flip-flop 2, the flip-flop 2 is reset at time t2, its output is inverted to low level at time t2, and the output line 3 is supplied with a pulse width of L to t2. You can get the output of Incidentally, since the counter 5 is reset by the Q output of the flip-flop 2, an output with a pulse width of t, to t2 is obtained on the output line 3 every time the trigger IJ signal is input. In addition, in the counter output selection signal generation circuit 7, a switch 8 is switched in conjunction with the magnetic tape speed.
By switching the lines a to g connecting the power supply 9, a different force counter output is selected, the time point at which the output pulse in FIG. 2D occurs changes, and eventually the width of the output pulse shown in FIG. 2B also changes. That is, if the output shown in FIG. 2D is obtained with the count number n of the clock signal of period T shown in FIG. 2C, then the output shown in FIG.
The pulse width of is T×(n-1).

Then, if the output pulse width at n, counter is T^, and the output pulse width at n2 count is TB, then T^ T×(
The following relationship holds: n, -1) n, -I TB - Tx02-1) n2-1, and the pulse width can be changed according to the ratio of (n, -1) and (n2 -1). .

By the way, although the delay time of each circuit element was not taken into account in Figure 2, in reality there are delays in rise time, fall time, etc., and if you draw a timing chart taking these delays into account, it will look like Figure 3. become. In other words, even if the trigger signal is applied at the time point shown in FIG.
be at a high level at this point. However, this delay time between t and t2 is substantially unrelated to the output pulse width ratio. Next, even if the Q output of flip-flop 2 becomes high level at time t2, the clock signal is not immediately sent out, and the first clock pulse is generated at time t3 after a delay time T. In other words, even if the last clock signal is generated at time t5, the output signal from the counter output control circuit 6 is not obtained immediately at time t5, but the output shown in FIG. 3D is obtained at a later time after delay time T2. Furthermore, even if the counter output is obtained at time k, the Q output of flip-flop 2 does not immediately invert to a low level, but inverts at time t7 after the delay time. Therefore, la~t? The pulse width of the period is Tx(n-1)
10T, 10T20T3.

Then, the ratio of the output pulse width T^ at n and count to the output pulse width TB at count is Tx (n, -1) + T
, 10T20T3T×(Yama 1) 10T, 10t+T3, and because of the constant terms T, 10T20T3, the ratio is not as in the case of Fig. 2, and n, and n2 It is not possible to obtain a pulse width with a fixed integer ratio.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a variable pulse width one-shot multivibrator that has a good correspondence between the ratio of the number of counted pulses and the ratio of output pulse widths.

To achieve the above object, the present invention includes a trigger signal input line, and a set output from a reset output state in response to a trigger input signal coupled to the trigger signal input line and supplied with V from the trigger signal input line. a first flip-flop that switches from the set output state to the reset output state in response to a reset signal supplied from a second flip-flop described below; and an output line of the first flip-flop; a clock signal generation circuit coupled to an output line of the clock signal generation circuit and an output line of the first flip-flop; a counter that counts the clock signal sent from the clock signal generation circuit and enters a reset state in response to a reset output of the first flip-flop; and a counter that outputs an output signal when a selected output line of the counter is in a power state. a counter output selection signal generation circuit capable of providing a plurality of counter output selection signals for generation; and a counter output selection signal generation circuit coupled to an output line of the counter and the counter output selection signal generation circuit; a counter output control circuit that sends out an output signal when an output state specified by a selection signal is reached; and a counter output control circuit configured to operate as a D-type flip-flop and whose data input terminal is connected to the output line of the counter output control circuit. and a clock terminal thereof is coupled to an output line of the clock signal generation circuit, and an output terminal thereof is coupled to a terminal for resetting the first flip-flop; The first output state is changed to the second output state in response to the first clock signal being supplied, and the output signal of the counter output control circuit is supplied to the data input terminal and the clock terminal is supplied with the output signal of the counter output control circuit. When the clock signal is supplied, the output state is changed from the second output state to the first output state to generate an output of a desired pulse width, and from the second output state to the first output state. a second flip-flop configured to provide the reset signal to the first flip-flop in synchronization with the transition of
Flipf.

and an output line of the one-shot multivibrator connected to the output terminal of the second flip-flop. According to the present invention, a D-type second flip-flop is added and its clock terminal is connected to the clock signal generation circuit that drives the counter, so that the count is substantially synchronized with the start and end of counting in the counter. This makes it possible to control the output of the second D-type flip-flop, so that the change in pulse width based on the change in the counter output selected by the counter output selection signal generation circuit corresponds well to the change in the count number. Become.

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 4 to 6.

In the digital one-shot multivibrator in the FM demodulation circuit of the data recorder shown in Fig. 4, a D-type flip-flop is used as the first flip-flop 2, and the trigger input line 1 is connected to its set terminal S. , its data input terminal D is grounded, and its clock terminal C is coupled to the Q output terminal of the second flip-flop 10.

The first output line 11 connected to the Q output terminal of this flip-flop 10 is connected to the gate of the clock signal generation circuit 4, and the second output line 12 connected to the Q output terminal is connected to the digital counter. It is connected to the reset terminal R of No.5. The data input terminal D of the second flip-flop 10 having a type flip-flop configuration is
coupled to the output line 13 of the counter output control circuit 6;
Its clock terminal C is connected to the output line 14 of the clock signal generation circuit 4, and its set terminal S is connected to a switch 15 which is turned on in conjunction with the reproduction mode setting and supplies a voltage of 10V.

The one-shot output line 3 is connected to the Q output terminal of the second flip-flop 10, and the clock terminal C of the first flip-flop 2 is also connected thereto.
The counter 5, counter output control circuit 6, and counter output selection signal generation circuit 7 are constructed in the same manner as the circuit shown in FIG. FIG. 5 shows the clock signal generation circuit 4 of the circuit shown in FIG. 4, which is composed of an intermittent oscillation circuit 4a and an AND gate 4b, and the AND gate 4b has an output line of the oscillation circuit 4a and a first flip-flop The first output line 11 of No. 2 is connected thereto.

Therefore, the clock signal of the oscillation circuit 4a is sent to the output line 14 only when the Q output terminal of the first flip-flop 2 becomes high level and the AND gate 4b is opened. FIG. 6 shows the counter counter 5 and counter output control circuit 6 of FIG. 4.

The counter 5 is a well-known circuit composed of NAND gates G,,○2 and seven flip-flops FFo to FF6, and its output is input to the NAND gates G3 to G9 of the counter output control circuit 6. There is. Seven control lines a to g of the counter output selection signal generation circuit 7 shown in FIG. 4 are also input to the NAND gates G3 to G9 of the power counter output control circuit 6. The outputs of the seven NAND gates G3 to G9 are input to one NOR gate ○, o, respectively, and this output is sent to the output line 13 via an inverter (INV). As a result, for example, the tape speed is 4.76/s, 9.5/s on the control input lines a to g.
2c/s, 19.05 arc/S, 38, 1C double/S, 7
6.2 skin/S, 152.4 skin/S, 304.8cm/s
A pulse is obtained on the output line 13 during the count state corresponding to the signal provided correspondingly. Next, the operation of the circuit shown in FIG. 4 will be explained with reference to the time chart shown in FIG.

In this embodiment, in order to ensure that the Q output of the second flip-flop 10 is at a high level (first level) before the point in time, the switch 15 is set as an initial state setting circuit in conjunction with the playback mode setting. Turn on. As a result, the second flip-flop signal is input, and the second flip-flop signal is input.
The Q output of the flip-flop 10 becomes high level. Incidentally, if the Q output of the second flip-flop 10 has been previously maintained at a high level by the previous operation, setting by the switch 15 is of course unnecessary. Also, the data input terminal D and clock terminal C of this flip-flop 10 may be used to set the Q output to a high level. With the Q output of the flip-flop 10 set at a high level as described above, when one pulse of a pulse train forming an FM wave is input as a trigger signal to the set terminal S of the first flip-flop 2 as shown in FIG. 7A, A little later than time t, the first flip-flop 2 is set and its Q output becomes high level as shown in FIG. 7B. Therefore, the gate of the clock signal generating circuit 4 is opened, and the clock signal shown in FIG. 7C is generated at a constant period T from time t3. The first clock pulse at time t3 becomes an input to the counter 5 and is also supplied to the clock terminal C of the second flip-flop 10. Since the data input terminal D of the second flip-flop 10 is at a low level in advance at this point t3,
In response to the clock pulse at time t3, the Q output changes to a low level at time t4 after a delay time L, as shown in FIG. 7E. On the other hand, counter 5 counts clock signals. Now, if the counter output selection signal generation circuit 7 is set so that an output is generated from the counter output control circuit 6 when the nth clock pulse is counted, then the nth clock pulse at time t. At a time slightly delayed from the front green, a counter output pulse is sent to output line 13 as shown in FIG. 7D. As a result, the data input terminal D of the second flip-flop 10 becomes high level, but the output is not inverted immediately because it lags behind the rise of the n-th clock pulse. Then, when the (n+1)th clock pulse is generated at time t8, in response to the high level data at output terminal D at the time of this clock pulse, output terminal Q is output at t, which is delayed by delay time T5 from t8.
At time 9, the level changes from low level (second level) to high level (first level).
level). When the Q output terminal of the second flip-flop 10 goes to a high level at the time point, this is applied to the clock terminal C of the first flip-flop 2 as a reset signal, and after a delay. At this point, the Q output of the first flip-flop 2 changes from a high level (first level) to a low level (second level), the gate of the clock signal generation circuit 4 closes, and the Q output of the first flip-flop 2 changes from a high level (first level) to a low level (second level). Counter 5 is set by the signal from the output terminal. As a result, the counter output obtained from the counter output control circuit 6 also becomes low level again, and the second flip-flop 1
It becomes possible to generate the next output pulse. Since it operates as described above, the period between the clock signal and the output pulse ToUT of the second flip-flop 10 is T, where T is the period of the clock signal.

The relationship UT=T×n+T5−T4 holds true.

However, the delay time L of the transition of the output of the second flip-flop 10 from a high level to a low level in response to the first clock pulse is equal to this flip-flop. T5 is approximately the same as the delay time L when the output of pin 10 changes from low level to high level at the n+1th clock pulse.
-T4=0, and T. UT=T×n. Therefore,
n, the second flip-flop 10 when set to provide the output pulse of FIG. 7D in response to the count.
The output pulse width ToUT, and the output pulse width Tom2 of the second flip-flop 10 when set so that the output pulse shown in FIG. 7D is obtained in response to the n2 count.
The ratio is T. UT, -Txn, -nIT.

UT2-Tx~n2, and the pulse width also changes according to the change in the ratio of the count numbers specified according to the tape speed by the counter output selection signal generation circuit 7, so that a pulse width of an integer ratio is obtained.

Therefore, it is possible to variably set the output pulse width ToUT in response to changes in the playback speed at which FM data is read from the recording medium. term is no longer included, and the DC level of the analog signal can be kept approximately constant even if the playback speed is changed.

Although one embodiment of the present invention has been described above, the present invention is not limited to this and can be further modified.

For example, the first flip-flop 2 may be an RS flip-flop. In this case, a minute width set pulse synchronized with the 9-point or edge of the output of the second flip-flop 10 shown in FIG. 7E is created and supplied to the reset terminal of the RS flip-flop. In addition, the output of the second flip-flop 10 is added to the clock terminal of the first flip-flop 2 in FIG. It is also possible to create a synchronized minute width reset pulse and supply it to the reset terminal of the first flip-flop 2.Also, the outputs of the first and second flip-flops 2 and 10 can be taken out. The present invention is not limited to the above method, and it is possible to use the Q output in place of the Q output, to use the Q output in place of the Q output, or to invert the phase by providing an inverter. Alternatively, the clock signal generation circuit 4 may not be formed as shown in FIG. 5, but the clock signal generation may be controlled by controlling the power supply of the oscillation circuit 4a on and off using the output of the first flip-flop 2. You can also use it as

Further, the counter output control circuit 5 and the counter output selection signal generation circuit 7 are not limited to the circuit shown in FIG.
Any circuit may be used as long as the circuit generates an output pulse at the specified counter output. For example, a digital comparison circuit is provided, and the output of the counter 5 is input thereto, and
A digital signal set corresponding to the tape speed may be input to the digital signal generating circuit, and an output pulse may be generated when both inputs are satisfied.

Alternatively, a microcomputer may be used to respond to a predetermined count output.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional digital one-shot multivibrator, Fig. 2 is a voltage waveform diagram schematically showing the states of points A to D in Fig. 1, and Fig. 3 is a diagram showing A to D in Fig. 1. 4 is a block diagram showing a one-shot multi-noise oscillator of a data recorder according to an embodiment of the present invention, and FIG. 5 is a waveform diagram showing the state at points D taking into account delay. 6 is a block diagram showing the counter and counter output selection signal generating circuit 7 of FIG. 4, and FIG. 7 is a waveform diagram showing the states of points A to E in FIG. 4. In the symbols used in the drawings, 1 is a trigger input line, 2 is a first flip-flop, 4 is a clock signal generation circuit, 5 is a counter, 6 is a counter output control circuit, and 7 is a counter output selection signal. The generator circuit is a second flip-flop. Figure 1 Figure 2 Figure 3 Figure 5 Figure 4 Figure 6 Figure 7

Claims (1)

[Scope of Claims] 1. a trigger signal input line; a trigger signal coupled to the trigger signal input line and configured to switch from a reset output state to a set output state in response to a trigger input signal supplied from the trigger signal input line; a first flip-flop that switches from the set output state to the reset output state in response to a reset signal provided from a second flip-flop; a clock signal generation circuit that outputs a clock signal in response to a set output of the flip-flop; and a clock signal generation circuit coupled to an output line of the clock signal generation circuit and an output line of the first flip-flop, counting the clock signals and counting the clock signals;
a counter that is placed in a reset state in response to a reset output of a flip-flop; and a counter output selection signal capable of providing a plurality of counter output selection signals to generate an output signal during a selected output state of the counter. a counter output control circuit that is coupled to an output line of the counter and the counter output selection signal generation circuit and that outputs an output signal when the counter reaches an output state specified by the counter output selection signal; , is configured to operate as a D-type flip-flop, and has its data input terminal coupled to the output line of said counter output control circuit, and its clock terminal coupled to the output line of said clock signal generation circuit, and whose output terminal is coupled to a terminal for resetting the first flip-flop, and changes the output from the first output state to the second output state in response to the first clock signal being supplied to the clock terminal from the clock signal generation circuit. the second output state to the first output state when the output signal of the counter output control circuit is supplied to the data input terminal and the clock signal is supplied to the clock terminal. and is configured to provide the reset signal to the first flip-flop in synchronization with the transition from the second output state to the first output state. Second
A variable pulse width one-shot multivibrator comprising: a flip-flop; and an output line of the one-shot multivibrator connected to the output terminal of the second flip-flop.