JPS6412191B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control system for a DC motor, and in particular, to match the frequency of a speed reference signal with the frequency of a speed signal obtained from a speed frequency generator attached to the motor that provides information on the rotational speed of the motor. The present invention relates to a speed phase control device for a motor that rotates.

Conventional motors used in audio equipment such as record players and tape recorders often use speed control motors that use voltage as the standard for their rotational speed, but this method It is difficult to create a reference voltage that is sufficiently stable as the components change over time, and there are also problems in that speed deviations occur with respect to the load.

To solve this problem, high-end machines add a phase control loop to the speed control loop, and in particular, use something highly stable, such as the output of a crystal oscillator, as a comparison reference for the phase control. However, this method is composed of two control loops, a speed control loop and a phase control loop, and the operations of these two control loops influence each other, making adjustment complicated.
Further, the configuration becomes complicated, and there are also problems such as the operating points of both shift due to changes in ambient temperature or aging of electronic components, and the phase synchronization range decreases.

Furthermore, when applying phase control to the motor,
The stability of phase synchronization pull-in is an extremely important issue. If phase synchronization pull-in is not carried out stably, not only will the motor not rotate normally at the specified rotational speed, but the hunting phenomenon will occur in which the speed fluctuates greatly. This often occurs. Therefore, when applying phase control to a motor, the stability of phase synchronization pull-in is a very important factor. The phase synchronization pull-in characteristic of a motor is controlled by several factors, one of which is important.
Another factor is the acceleration/deceleration torque of the motor itself. In order to smoothly perform phase synchronization pull-in, acceleration torque and A necessary condition is to use a motor that generates deceleration torque in both directions. Therefore, in the past, motors that generate bidirectional torques, namely acceleration torque and deceleration torque, have often been used as motors to which phase control must be applied. However, in order to realize a motor that generates bidirectional torque,
It is necessary to switch the direction of motor current, which makes the motor drive circuit considerably complex, resulting in increased costs.

Next, the case of speed phase control of a conventional DC motor will be explained with reference to FIG. In FIG. 1, 1 is a reference signal oscillator, the output of which is supplied to a phase difference-to-voltage converter 2 as a motor speed phase reference.
Reference numeral 7 denotes a DC motor, and a speed frequency generator 8 that generates a frequency proportional to the number of rotations of the motor is connected to its rotating shaft. The output of the speed frequency generator 8 is connected to a waveform shaping circuit 9, and after being waveform-shaped, it is input to both the phase difference-voltage converter 2 and the speed-voltage converter 3. The phase difference-voltage converter 2 converts the phase difference between the reference signal obtained by the reference signal oscillator 1 and the speed signal of the speed frequency generator 8 into a voltage. This converted voltage will be referred to as a phase difference voltage signal. The speed-voltage converter 3 converts the speed signal of the speed frequency generator 8 into a voltage proportional to its frequency, and this voltage will be referred to as a speed voltage signal. 4 is an adder which adds the phase difference voltage signal and the speed voltage signal. The next added signal is the DC amplifier circuit 5
After being amplified by , the signal is supplied to a drive circuit 6 that drives a DC motor 7 .

In the speed phase control method described above, the reason why a phase control loop system that outputs a phase difference voltage signal and a speed control loop system that outputs a speed voltage signal are used together is as follows. That is, when considering the transfer function from torque to rotational speed of a rotary motion system including a motor, the moment of inertia of the motor is an integral term, and the phase control loop system is a differential term. Therefore, this negative feedback control system becomes mathematically in an oscillating state if only this is done. In reality, the motor produces a hunting phenomenon.
Therefore, proper damping is absolutely necessary to restore the stability of the system, and this corresponds to the speed control loop system. If damping is insufficient, a resonance phenomenon occurs at a specific frequency, resulting in instability, and at the same time, wow and flutter in the rotational speed generally worsens. On the other hand, if the damping is too deep, it will become more stable, but it will also cause problems such as longer start-up times. The speed control loop system also functions to smoothly perform phase synchronization pull-in, by applying a large starting torque at startup and bringing the rotation speed close to the reference rotation speed during synchronization, facilitating phase synchronization pull-in.

However, the above conventional speed phase control method
In the figure, since the adder 4 adds the phase difference voltage signal and the speed voltage signal including the DC component,
The drift of the speed voltage signal in the speed control loop system has an adverse effect on the phase control loop system, and in the worst case, phase synchronization may become impossible. Furthermore, in order to smoothly perform phase synchronization pull-in,
The DC motor drive circuit 6 must be configured to be able to generate acceleration torque and deceleration torque in both directions, which has the disadvantage that the circuit is complicated and costs are high.

As one solution to the above problem, if attention is paid to the fact that the speed voltage signal can be obtained by differentiating the phase difference voltage signal, the circuit configuration becomes extremely simple. That is, a differentiating circuit is newly provided in place of the speed-voltage converter 3, and the phase difference voltage signal and the speed voltage obtained by differentiating this phase difference voltage signal with the differentiating circuit are generated using the phase control loop system as the main body. If the signal is used, the DC component of the speed voltage signal is excluded, so the DC drift of the speed voltage signal can be ignored, and the two loops of the conventional phase control loop system and speed control loop system Control characteristics equivalent to those of the velocity phase control system configured by the system can be obtained.

FIG. 2 shows a block diagram of the speed phase control method described above. In the figure, blocks that perform the same functions as those shown in FIG. 1 are given the same numbers.
In FIG. 2, 20 is a differentiator circuit for differentiating the phase voltage signal obtained by the phase difference-voltage converter 2 and converting it into a speed voltage signal. The phase difference voltage signal obtained by the phase difference-voltage converter 2 and the speed voltage signal converted by the differentiating circuit 20 are amplified by amplifiers 22 and 21, respectively, and then input to an adder 4. . Note that the phase difference voltage signal and the speed voltage signal may be added and then amplified. The addition signal obtained by the adder 4 is supplied to a drive circuit 6 to control a DC motor 7.

The phase difference-to-voltage converter used in FIGS. 1 and 2 includes, for example, one using a sample-and-hold circuit. The circuit configuration is shown in FIG. In the figure, numeral 33 denotes a charging/discharging capacitor, which is charged by a constant current source 32 and discharged (reset) by a reset switch 31. The reset switch 31 is periodically turned on for very short periods by the reset panel obtained from the reference oscillator 1, discharging the charge/discharge capacitor 33. A buffer circuit 34a is provided to receive the voltage across the charging/discharging capacitor 33 at high impedance. A sampling switch 35 transfers the voltage reproduced across the charge/discharge capacitor 33 to the hold capacitor 36. The sampling switch 35 is made conductive for a very short time by a sampling pulse derived from the speed signal of the speed frequency generator 8, and is normally open. 34
b is a buffer circuit which receives the voltage of the hold capacitor 36 and outputs it to an output terminal 37; The sample-and-hold type phase difference-to-voltage converter shown in FIG. 3 can be realized with a relatively simple circuit configuration. Moreover, the sample-and-hold circuit is a type of low-pass filter with extremely excellent high-frequency cutoff characteristics, and its output has little ripple or phase lag, so if it is used, an extremely excellent phase difference-to-voltage converter can be realized. It has characteristics.

FIG. 4 is a waveform diagram showing the operation of the phase difference-to-voltage converter of FIG. 3. In FIG. 4, a is a reset pulse obtained from the reference signal oscillator 1, and b is a reset pulse obtained from the reference signal oscillator 1.
is a sampling pulse obtained by the speed signal of the speed frequency generator 8 coupled to the rotating shaft of the DC motor 7. c is charge/discharge capacitor 3 in Figure 3
3 shows the voltage waveform at both ends of the constant current source 3.
2 and the reset switch 31, a sawtooth wave having the same period as the reset pulse is obtained. d shows the voltage waveform across the hold capacitor 36,
Charging and discharging capacitor 33 at the time of sampling
The voltage at both ends is held until the next sampling point.

Therefore, the terminal 37 in FIG. 3 receives a signal corresponding to the phase difference (corresponding to θ shown in FIG. 4) between the reference signal obtained from the reference signal oscillator 1 and the speed signal of the speed frequency generator 8 coupled to the motor 7. A proportional voltage is obtained.

Figure 5 shows the sample-and-hold type phase difference in Figure 3.
It shows the phase difference-voltage characteristics of a voltage converter. As is clear from the figure, in this type of phase difference-voltage converter, the output voltage is
Since it has a periodicity of 2π, it is sufficient to detect only a phase difference from 0 to 2π, but it is impossible to detect a phase difference larger than that.

If such a phase difference-voltage converter is used in the motor phase control system shown in the block diagram of FIG. 2, not only will sufficient starting torque not be obtained at startup, but
The motor may be erroneously synchronized to a rotational speed that is an integral multiple of the reference rotational speed, and has the disadvantage that the motor cannot be controlled to a desired rotational speed. Furthermore, the second
In the speed phase control device shown in the figure, in order to obtain the speed voltage signal, the phase difference-voltage signal is added to a differentiating circuit and differentiated, so that the phase difference-voltage characteristic has a discontinuous point as shown in the phase difference-voltage characteristic of FIG. Using a phase difference-to-voltage converter would result in the speed voltage signal containing spike-like pulses at the discontinuity.
As a result, spike-like torque is generated in the motor, resulting in significant vibration and noise. Moreover, this spike-like torque reduces the possibility that the motor will be retracted stably and reliably synchronously.

In order to eliminate the above drawbacks, the present invention adds a synchronization detection circuit for determining whether or not the motor is synchronized with a reference signal to the speed phase control device shown in the block diagram of FIG. While taking advantage of the advantages of the phase difference-to-voltage converter using a hold circuit, it prevents erroneous synchronization with the reference frequency and facilitates synchronization, and is resistant to changes in ambient temperature and aging of electronic components. Therefore, it is possible to provide a speed phase control device for a DC motor that is extremely stable and that can stably and reliably perform phase synchronization pull-in even for a motor that only generates acceleration torque.

An embodiment of the present invention will be described below based on the drawings. FIG. 6 is a block diagram showing the motor speed phase control device of the present invention. In the figures, blocks that perform the same functions as those shown in FIGS. 1 and 2 are given the same numbers. In FIG. 6, 62 is a synchronization detection circuit, into which both the reference signal obtained by the reference signal oscillator 1 and the speed signal obtained by waveform shaping the output of the speed frequency generator 8 by the waveform shaping circuit 9 are input. There is. This synchronization detection circuit 6
2 compares the magnitude of the frequency of both inputs in the first half, and when the frequency of the speed signal is lower than the frequency of the reference signal, an acceleration command is output, and when the frequency of the speed signal is higher than the frequency of the reference signal, a deceleration command is output. Output. Note that in a synchronous state where the frequencies of the speed signal and the reference signal match, the acceleration command and deceleration command are not output.

Both outputs of the synchronization detection circuit 62 are supplied to a motor control circuit 61. When the rotational speed of the motor is slower than the reference speed or when the motor is in a stopped state, the synchronization detection circuit 62 outputs an acceleration command. The acceleration command causes the motor to generate maximum acceleration torque and increases the rotational speed of the motor. The motor is accelerated by the acceleration command,
The acceleration command is canceled when the rotational speed of the motor reaches the reference speed. However, when the rotational speed of the motor overshoots and exceeds the reference rotational speed, or exceeds it for some reason, the synchronization detection circuit 62 outputs a deceleration command. If the motor drive circuit is configured to generate acceleration torque and deceleration torque in both directions, the deceleration torque may be generated by the deceleration command, or if the motor drive circuit is configured to generate only acceleration torque. In this case, the motor current is cut off by the deceleration command, the acceleration torque is removed, and the rotational speed of the motor is reduced. Since the deceleration command is released in the synchronous state, the rotational speed of the motor is pulled into the synchronous state as a result.

As will be described later, by adding the synchronization detection circuit 62 to the motor control circuit 61 of FIG. 6, the phase difference of the phase difference-to-voltage converter included in the motor control circuit of FIG. - The voltage characteristics can have saturation characteristics. Therefore, the phase difference voltage signal can be differentiated, and as mentioned above, the speed voltage signal obtained by differentiating this signal does not contain spike-like pulses, and the motor can be stably and reliably synchronized. be drawn in. FIG. 7 is a circuit configuration diagram of an embodiment effective for use in the phase synchronization detection circuit 62 of FIG. 6. Letters A to E in the figure correspond to those in FIG. 8, respectively. In FIG. 7, 71a and 71b are trigger circuits to which a reference signal and a speed signal are input, respectively. 72a, 72
b and 72c are first, second and third RS flip-flop circuits, respectively. Trigger circuit 71a
The output terminal of is connected to one input terminal of the first AND circuit 74a, and is also connected to the set input terminal S of the first RS flip-flop circuit 72a. The input terminal of the trigger circuit 71b is connected to one input terminal of the second AND circuit 74b, and is also connected to the reset input terminal R of the first RS flip-flop circuit 72a. Reference numerals 73a, 73b, 73c, and 73d are first, second, third, and fourth delay circuits, respectively, which delay the rising edge of the input pulse by a predetermined period of time before outputting it. Of these, 73a and 73b output in response to their input without delaying the falling portion. As for 73c and 73d, the falling portion may also be output with a delay. The output terminal Q of the first RS flip-flop circuit 72a is connected to the other input terminal of the first AND circuit 74a via the first delay circuit 73a,
The output terminal is connected to the second delay circuit 73b via the second delay circuit 73b.
is connected to the other input terminal of the AND circuit 74b. The output terminal of the first AND circuit 74a is connected to one input terminal of the third AND circuit 74c, and is also connected to the set input terminal S of the second RS flip-flop circuit 72b. The output terminal of the second AND circuit 74b is connected to one input terminal of the fourth AND circuit 74d, and is also connected to the reset input terminal R of the second RS flip-flop circuit 72b. Similarly, the output terminal of the third AND circuit 74c is connected to the set input terminal S of the third RS flip-flop circuit 72c, and the output terminal of the third AND circuit 74c is connected to the set input terminal S of the third RS flip-flop circuit 72c.
The output terminal of 4d is connected to the reset input terminal R of the third RS flip-flop circuit 72c. The two input terminals of the fifth AND circuit 74e are connected to the output terminals Q of the second and third RS flip-flop circuits, respectively, and output an acceleration command. The two input terminals of the sixth AND circuit 74f are connected to the output terminals of the second and third RS flip-flop circuits, respectively, and output a deceleration command.

FIG. 8 is a waveform diagram showing the operation of the synchronization detection circuit of FIG. 7. In FIG. 8, A is a reference signal, and B is a speed signal after waveform shaping. C and D are trigger pulses obtained by the trigger circuits 71a and 71b, respectively, and in the figure, the trigger pulses are generated at the leading edges of the reference signal A and the speed signal B. E is the first RS flip-flop circuit 7
Indicates Q output of 2a, “H” with trigger pulse
, and is inverted to "L" by trigger pulse 2.

FIG. 8a shows a waveform diagram when the frequency of the speed signal is lower than the frequency of the reference signal, and FIG. 8b shows a waveform diagram when the frequencies of the speed signal and the reference signal match.

In FIG. 8a, since the frequency of the speed signal B is lower than the frequency of the reference signal A, two or more trigger pulses C exist between the trigger pulses D and D. Among the continuous trigger pulses, the first numbered trigger pulse inverts the Q output of the first RS flip-flop circuit 72a to the "H" state as shown in E. F shows a waveform in which only the leading edge portion of the waveform of the Q output E is delayed by the duration of the trigger pulse by the first delay circuit 73a. 7 shows the output of the first AND circuit 74a. The reference trigger pulse C and the output of the delay circuit 73a are supplied to two input terminals of the AND circuit 74a, and when the first trigger pulse is supplied to one input terminal of the AND circuit 74a, Since the waveform supplied to the other input terminal is still in the "L" state, the first trigger pulse is
is not output to the output terminal of the AND circuit 74a.
When the second and subsequent trigger pulses among the next consecutive trigger pulses are supplied to the input terminal of the first AND circuit 74A, the waveform supplied to the other input terminal becomes "H" state. Therefore, the second and subsequent trigger pulses are output as they are to the output terminal of the first AND circuit 74a.
Therefore, the second and subsequent trigger pulses output from the first AND circuit 74a are supplied to the set terminal S of the second RS flip-flop circuit 72b, thereby setting the Q output to the "H" state. Also, if the frequency of speed signal B is lower than the frequency of reference signal A, the second
A trigger pulse is not output from the output terminal of the AND circuit 74b, and the second RS flip-flop circuit 72b is not reset. Therefore, all trigger pulses input from the first AND circuit 74A to the third AND circuit 74c are output from the output terminal of the third AND circuit 74c, and are output from the third RS flip-flop circuit 72c.
The Q output power of is set to "H" state. As is clear from the above explanation, when the frequency of the speed signal B is lower than the frequency of the reference signal A, the Q outputs of the second RS flip-flop circuit 72b and the third RS flip-flop circuit 72c are "H". “It’s in a state. As a result, the fifth AND circuit 7
The output terminal 4c goes into the "H" state and outputs an acceleration command.

The above description can be applied in the same manner even when the frequency of the speed signal B becomes higher than the frequency of the reference signal A, so a description thereof will be omitted. In this case, the second RS flip-flop circuit 72b
and the output of the third RS flip-flop circuit 72c are in the "H" state (the Q output is in the "L" state).
Therefore, the output terminal of the sixth AND circuit 74f is in the "H" state, and the deceleration command is output.

FIG. 8b shows a waveform diagram when the frequency of the speed signal B and the frequency of the reference signal A match, that is, in a synchronous state. In the synchronized state, both trigger pulses C and D output from the trigger circuits 71a and 71b appear alternately at a fixed period corresponding to the phase difference between the reference signal A and the speed signal B, and when one of the trigger pulses The pulses do not appear consecutively. Therefore, the trigger pulses C and D bring the Q output of the first RS flip-flop circuit 72a into the "H" state for a period corresponding to the phase difference between the trigger pulses C and D, as shown in E. Further, both trigger pulses C and D are connected to the first and second AND circuits 74a and 74.
Since it is not output to the output terminal of b,
RS flip-flop circuit 72b and the third
The output state of the RS flip-flop circuit 72c is not changed, and the Q outputs of the second and third RS flip-flop circuits 72b and 72c are fixed at the "H", "L" or "L", "H" states, respectively. As it is, neither an acceleration command nor a deceleration command is output from the fifth AND circuit 74e and the sixth AND circuit 74f.

Incidentally, since the synchronization detection circuit shown in FIG. 7 is entirely composed of digital circuits, it has the characteristic that it does not require complicated adjustment.

FIG. 9 shows an embodiment showing a method for forcibly accelerating or decelerating the motor in response to acceleration commands and deceleration commands output by the synchronization detection circuit in an asynchronous state of the motor. The embodiment shown in FIG. 9 is based on the configuration of the sample-and-hold type phase difference-to-voltage converter shown in FIG. 3, and parts having the same functions in the figure are given the same numbers. 91 is a switch that is opened only when the synchronous detection circuit is outputting an acceleration command; 92 is a switch that is turned on only when the synchronous detection circuit is outputting a deceleration command, and resets the charging/discharging capacitor 33. . Therefore, when an acceleration command is present, the switch 91 is open, so the voltage across the charging/discharging capacitor 33 is not reset and reaches the saturation voltage. As a result, the saturation voltage across the charging/discharging capacitor 33 is outputted to the output terminal 37, and a maximum torque command is given to the motor drive circuit to increase the rotational speed of the motor. Next, when a deceleration command exists, switch 9
2 is conductive and both ends of the charging/discharging capacitor 33 are short-circuited, so the voltage across the charging/discharging capacitor 33 becomes zero, and the voltage at the output terminal 37 becomes zero. As a result, the rotational speed of the motor is reduced.

Note that when the motor is synchronously pulled in, the synchronous detection circuit does not output an acceleration command or a deceleration command, the switch 91 is conductive, and the switch 92 is turned on.
is open, so it has exactly the same function as the conventional sample-and-hold type phase difference-voltage converter shown in FIG. 3, and outputs a voltage proportional to the phase difference between the reference signal and the speed signal from the output terminal 37. Output.

FIG. 10 shows the phase difference-voltage characteristics of the phase difference-voltage converter shown in FIG. 9. As is clear from FIG. 10, the phase difference-voltage converter shown in FIG. 9 does not have periodicity in the phase difference-voltage characteristics as shown in FIG.
For phase differences up to 2π, it outputs a voltage proportional to the phase difference, but when the phase difference is 0 or less and 2π or more, it has a saturation characteristic of outputting a constant voltage. Therefore, the phase difference voltage signal obtained by the phase difference-voltage converter can be differentiated, and the speed voltage signal obtained by differentiation does not contain spike-like pulses, and the motor can be safely and reliably pulled into phase synchronization. Ru.

FIG. 11 shows another embodiment showing a method for forcibly accelerating or decelerating the motor in response to acceleration commands and deceleration commands output by the synchronization detection circuit in an asynchronous state of the motor. 1st
FIG. 1 is also based on the configuration of the sample-and-hold type phase difference-voltage converter shown in FIG. 3, and parts that perform the same functions in the figure are given the same numbers. Reference numeral 111 denotes a switch that is turned on only when the synchronization detection circuit outputs an acceleration command, and when an acceleration command is present, the input terminal of the buffer circuit 34b is connected to the power supply line 115 via a resistor 113. , the saturation voltage is output from the input terminal 37 of the buffer circuit 34b. 112 is a switch that is turned on only when the synchronization detection circuit is outputting a deceleration command; when a deceleration command is present, the input terminal of the buffer circuit 34b is grounded via the resistor 114, so that the voltage at the output terminal 37 is It becomes zero. As a result, the phase difference-voltage characteristics shown in FIG. 11 have saturation characteristics as shown in FIG. 10, similar to FIG. 9.

In addition, as a method of imparting saturation characteristics to the sample-and-hold type phase difference-voltage converter according to the acceleration command and deceleration command of the synchronization detection circuit, for example, the third method is used.
The switch 92 in FIG. 9 and the switch 111 in FIG.
It is obvious that various combinations such as one in which a resistor 113 and a resistor 113 are added are conceivable. Furthermore, it is clear that the same effect can be obtained by adding the acceleration command and deceleration command of the synchronization detection circuit to the next signal amplification stage instead of applying them to the phase difference-voltage converter.

As is clear from the above description, according to the present invention, a DC motor can be developed which can perform extremely stable and reliable phase synchronization pull-in even though it uses a conventional sample-and-hold type phase difference-voltage converter with excellent characteristics. Speed phase control becomes possible. In addition, since it is mainly composed of a phase control loop system, and the speed control loop system is obtained by differentiating the phase difference voltage signal, the circuit configuration is simple, and even with a motor that only generates acceleration torque, the phase can be stabilized. Since synchronous pull-in is possible, the motor drive circuit can be greatly simplified. Furthermore, since the maximum torque is forcibly generated at startup, there is an advantage that the startup time required from motor startup to phase synchronization can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining a conventional speed phase control method, FIG. 2 is a block diagram explaining another speed phase control method, and FIG. 3 is a circuit configuration diagram of a sample-and-hold type phase difference-voltage converter. FIG. 4 is a waveform diagram explaining the operation of the phase difference-voltage converter shown in FIG. 3, FIG. 5 is a phase difference-voltage characteristic diagram of the phase difference-voltage converter shown in FIG. 3, and FIG. FIG. 7 is a circuit diagram showing an embodiment of the synchronization detection circuit of the present invention. FIGS. 8a and 8b explain the operation of the synchronization detection circuit shown in FIG. 7. 9 is a circuit diagram showing an embodiment of the phase difference-voltage converter used in the present invention, and FIG. 10 is the phase difference-voltage characteristic of the phase difference-voltage converter shown in FIG. 9. Figure, 1st
FIG. 1 is a circuit diagram showing another embodiment of the phase difference-to-voltage converter used in the present invention. DESCRIPTION OF SYMBOLS 1... Reference signal oscillator, 2... Phase difference-voltage converter, 4... Adder, 6... Drive circuit, 7... Motor, 8... Speed frequency generator, 20... Differentiation circuit, 31... ...Reset switch, 33...Charge/discharge capacitor, 35...Sampling switch, 3
6...Hold capacitor, 61...Motor control circuit, 62...Synchronization detection circuit, 71a, 71b...
...Trigger circuit, 72a-72c...RS flip-flop circuit, 73a-73d...Delay circuit,
74a to 74f...AND circuit, 91, 92, 1
11,112...Switch.

Claims (1)

[Scope of Claims] 1. A reference signal oscillator that generates a reference signal pulse as a motor speed reference; a speed frequency generator that extracts and outputs a speed signal with a frequency proportional to the rotational speed of the motor from the motor; a waveform shaping circuit that converts the signal into a speed signal pulse; a sample-and-hold phase difference-voltage converter that compares the reference signal pulse with the speed signal pulse and generates a phase difference voltage signal proportional to the phase difference; a differentiating circuit that differentiates the phase difference voltage signal and outputs a differential signal; an adder that adds the phase difference voltage signal and the differential signal to output a sum signal; and a drive of the motor according to the sum signal. A drive circuit that controls the current compares the reference signal pulse with the speed signal pulse, and outputs an acceleration command when two or more consecutive reference signal pulses occur between the speed signal pulses, and vice versa. Synchronous detection that outputs a deceleration command when two or more speed signal pulses occur between reference signal pulses, and outputs neither the acceleration command nor deceleration command when reference signal pulses and speed signal pulses occur alternately. circuit and at least a charge/discharge capacitor or a hold capacitor constituting the sample-and-hold type phase difference-voltage converter, and controls the accumulated voltage of the charge/discharge capacitor or the hold capacitor according to the output of the synchronization detection circuit. A switch element for controlling the drive current of the motor; and a switch element for controlling the drive current of the motor by opening and closing the switch element according to the output of the synchronization detection circuit, so that the reference signal pulse and the speed signal pulse are alternately generated. The motor is configured such that when the reference signal pulse and the speed signal pulse are generated alternately, the drive current of the motor is controlled in accordance with the addition signal of the adder. speed phase control device. 2. The synchronization detection circuit includes two trigger circuits that generate a reference trigger pulse and a speed trigger pulse, respectively, based on a reference signal and a speed signal, and a first RS flip-flop circuit to which the reference trigger pulse and speed trigger pulse are input. , the first
first and second circuits connected to the two output terminals Q of the RS flip-flop circuit, respectively, for outputting at least the leading edge portions of the two output waveforms with a delay of the duration of the reference trigger pulse and the speed trigger pulse or more; a delay circuit, first and second AND circuits that output the AND of the reference trigger pulse and the output signal of the first delay circuit, and the respective output signals of the speed trigger pulse and the second delay circuit; A second RS flip-flop circuit receives the output pulses of the first and second AND circuits, and is connected to the two output terminals Q of the second RS flip-flop circuit.
third and fourth delay circuits that delay the output pulse of the second AND circuit by the duration or longer and output the output signals of the first AND circuit and the third delay circuit; third and fourth AND circuits that output the respective ANDs of the output signals of the circuit and the fourth delay circuit; and a third RS flip-flop circuit that receives the output pulses of the third and fourth AND circuits. and a fifth RS flip-flop circuit that outputs the AND of the respective output signals of the two output terminals Q of the second and third RS flip-flop circuits.
a sixth AND circuit, outputting an acceleration command from a fifth AND circuit output terminal when the frequency of the speed signal is lower than the frequency of the reference signal;
Conversely, when the frequency of the speed signal is higher than the frequency of the reference signal, a deceleration command is output from the sixth AND circuit output terminal, and when the frequency of the speed signal and the frequency of the reference signal match, both the acceleration and deceleration commands are output. 2. The motor speed phase control device according to claim 1, wherein