JPS6330901A - Protecting device for digital processing circuit - Google Patents

Abstract

PURPOSE:To prevent a device from entering into a runaway state, by providing a circuit for detecting whether a clock exists or not, on the way of a path of a start command signal of a device which is subjected to a digital control, such as a motor, etc., and sending a stop signal to the device to be controlled such as the motor, etc., irrespective of a state of the start command signal, when the clock does not exist. CONSTITUTION:When a fundamental clock generator 2 does not generate a clock signal (ck), if a start command signal ST is L, a motor is in a stop state. Subsequently, when the start command signal ST becomes H, the reset of a flip-flop 13 is released, but since the clock signal (ck), namely, a rise signal is not inputted to a T terminal, an output Q is not varied to H. Therefore, a motor starting switch 9 remains opened, and a motor 11 holds a stop state. In this way, when the clock signal (ck) does not exist, even if the start command signal ST is impressed, the motor 11 is not shifted to a start state, and does not become a runaway state.

Description

[Detailed Description of the Invention] (Field of Application of the Invention) The present invention relates to a protection device for a control device using a digital processing circuit. A suitable protection to prevent the motor from running out of control in case of 2! Regarding equipment.

(Backbone of the Invention) Digital Processing The motor control circuit requires a basic clock for digital processing. I4
11w shows the configuration of the digital motor control device and provides an overview of digital speed control.

In the figure, 1 is a frequency-voltage converter, 2 is a basic clock generator, 3 is a frequency generator, 4 is a pulse generator, and 5
is a preset circuit, 6 is a counting counter, 7 is a latch circuit, 8 is a D/A converter, 9 is a motor start switch, 1
0 is a drive amplifier, 11 is a motor, and 12 is a start command signal input terminal.

The operation will be explained using the main waveform diagram of FIG. 12.

As the motor 11 rotates, a signal FG (hereinafter this signal will be abbreviated as an FC signal) is generated from the frequency generator 3. This FC signal is amplified and then applied to a pulse generator 4Vr. The pulse generator 4 outputs a latch pulse L and a preset pulse P in response to the input of the FG flaw signal, and applies them to the latch circuit 7 and the counting counter 6, respectively. A clock signal c k (not shown) from the basic clock generator 2 is applied to the pulse generator 4, and the output timing and pulse width of the latch pulse L and preset pulse P are determined using the clock signal ck as a reference signal. ,
You can decide. The bit information N of the counting counter 6 is held in the latch circuit 7 by the generation of the latch pulse L. Immediately thereafter, the preset pulse P presets the counting counter 6 to a predetermined end level determined by the preset circuit 5. After the preset pulse P is released, the counting counter 6 starts counting the clock signal ck (not shown) from the basic clock generator 2. After that, the same action is repeated again due to the large FG input of fire.

The information Nl held in the latch circuit 7 is converted into a voltage V by the D/A converter 8 at the primary stage. The D/A converter 8 also receives a clock signal from the basic clock generator 2. k (not shown) is applied, and this is the basic unit of D/A.
Perform conversion processing. At this time, the output voltage V is 1! f
A1! The pressure is half of the pressure Vcc (Vcc/2). Further, when the motor is driven, the motor start switch 9 is closed, the output voltage V is applied to the drive 10Yc, and the motor 11 rotates nine times.

The start command signal S applied to the start command signal input terminal 12
When T is L, the motor start switch 9 is open, no voltage is applied to the drive amplifier 10, and the motor is in a stopped state regardless of the output voltage V of the D/A converter 8.

- To put the motor 11 into the driving state, apply an n-force command signal input 1 to 12. By setting the start command signal ST (not shown) to H, the motor start switch 9 is closed.

The operation of converter 1 is performed on the above-mentioned 1 system number-voltage.

The motor 11 rotates under control. In other words, the state of the motor (driving state or stopped state) can be determined by the starting command signal STK applied to the starting command signal input 1 12.

Now, as mentioned above, the same wave number-voltage converter l is operated by the clock signal ckK from the reference clock generator 2, but for some reason, the clock signal ckK
Suppose that the voltage is no longer supplied to the 5 frequency-to-voltage converter l. This means that the digital processing does not operate normally, and the output voltage V of the D/A converter 8 is
The exact value cannot be guaranteed.

Furthermore, the output voltage V ramps up at a certain voltage because the digital processing function stops.

If the motor start switch 9 is closed, its output voltage V
will be applied as is to the drive amplifier 10,
The motor rotates at a number of rotations depending on the electric potential. If the output voltage V latches up to the power supply voltage VCC or a value close to it, the motor must continue to rotate at an abnormally high speed. (This state is called a runaway state.) When the above motor control device is used for magnetic recording and playback such as a home VTR, such a runaway state may lead to damage to the tape. It was a problem. Particularly in devices such as portable VTRs, which are often used under adverse conditions (vibration, humidity, etc.), such accidents are likely to occur, and for some reason the clock is no longer being supplied to the motor control circuit. In case,
There was a desire for a device that would always switch to a safe mode, in which the motor stops.

Note that a document that describes the configuration of such an L motor control device is National Technical Report Vo 12 B.
-Nn 3-1982, Hashimoto et al.'s tC for VTR signal processing and control. For this.

An example of VTR motor control is described.

(Object of the Invention) An object of the present invention is to eliminate the drawbacks of the prior art described above, and to ensure that a digitally controlled device, such as a motor, does not go into runaway mode even if the reference clock supplied to the servo circuit is absent. The purpose is to provide a thread.

(Summary of the Invention) In order to achieve this objective Tc, the present invention provides a circuit for detecting the presence or absence of two clocks in the path of a start command signal for a digitally controlled device such as a motor. In this case, regardless of the state of the start command signal, by sending a stop signal to the controlled equipment such as a motor, the controlled equipment is forcibly stopped and a runaway state is prevented. There are characteristics.

(Example of the invention) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a motor control circuit protection device according to the present invention, in which 13 is a flip-flop and 14 is an inverter.

Components corresponding to those in FIG. 11 are given the same reference numerals and their explanation will be omitted.

2, 3, and 4 are waveform diagrams showing signals of each part in FIG. 1, and signals corresponding to those in FIG. 1 are given the same reference numerals.

FIG. 2 shows the operation when the clock signal ck is normally supplied. First, when the start command signal ST is L, the 7 lip 70 knob 13 is reset and its output Q, that is, the signal STI becomes L. Since the output Q is applied to the motor starting switch 9 as the motor starting switch control signal STI, the switch 9 is opened, and at this time, the motor 1
1 is in a stopped state.

Next, when the start command signal ST becomes HVc, the reset terminal R of the 7-rib-flop 13 becomes L, so that the value of D at that time, H, is outputted to the output Q in order to manually input the rising edge of the clock to T. Therefore, the motor start switch control signal S
Since TI changes to L-IH, the motor start switch 9 closes, and the motor 11 shifts from a stopped state to a controlled rotation state.

In FIG. 3, the basic clock generator 2 has a clock signal c
The operation when k is not generated is shown. If the start command signal ST is L, the 1'+51IjJVc motor is in a stopped state as in the above case. Next, when the start command signal ST becomes H, the reset of the flip 70 knob 13 is released, but since the clock signal ck, that is, the rising signal is not input to the T terminal.

Output Q does not change to H. Therefore, the motor start switch 9 remains open, and the motor 11 remains stopped. That is, when there is no clock signal ck, even if the start command signal ST is applied.

The motor 11 does not shift to the starting state.

This means that it will not go out of control.

As described above, according to this embodiment, when the clock signal ck is no longer supplied, the motor starting switch 9 is turned off, and the operation of the motor 11 can be stopped. Therefore, the drawbacks of conventional devices can be overcome.

However, in this embodiment, if the clock signal ck is no longer supplied while the motor 11 is rotating under normal control, the motor 11 cannot be brought to a stopped state. The operation is shown in FIG. That is, once the output Q (ST1 signal) of the 7-rip 70 knob 13 shifts to H, it remains at H unless the flip 70 knob 13 is reset. In other words, in order to shift to the stopped state, the start command signal STf must be set once.

One reason for this difficulty is that in this embodiment, the activation command signal ST is used as a reference signal for determining the presence or absence of the clock signal ek.

In other words, if the output signal Q of the flip 70 knob 13 changes from L to H after the start command signal ST changes from L to H, it is determined that the clock signal ck is present, and if it remains L, it is determined that the clock signal ck is not present. Ta.

Another embodiment that eliminates this drawback is shown in FIG.

In the figure, 15 is a motor starting switch control circuit, and parts corresponding to those in FIG. 11 are given the same reference numerals and their explanations will be omitted.

In this embodiment, motor start switch control circuit 1
FG flaw signal is input to 5.

This FC signal is used as a reference signal for determining the presence or absence of the clock signal ek.

To explain this in a different way, the motor start switch control circuit 15 is configured to shift to a stopped state when the FG flaw signal is input. Then, the transition to the stopped state is canceled by the clock signal ck. Then, if there is a clock signal ek, even if a transition to the stopped state is attempted, it will be canceled immediately, but if there is no clock signal Ck, the stopped state will be maintained as it is. As a result, it is possible to determine the presence or absence of the clock signal ck.

An example of a specific circuit of this motor starting switch control circuit 15 -Vl- is shown in FIG. In this figure, 16.1
7 is a flip 70 knob, 18 is an OR circuit, 19.20
21 is an inverter, and 21 is a delay circuit using an inverter, which is composed of an even number of inverters. Also 2
2 is an exclusive OR circuit. However, the 7-rip 70-tube 16 can be both set and reset, and if both the S and R terminals become H, reset takes priority and the D input of the clip flop 16 is always at L level VC. There is.

Now, the operation of this circuit will be explained with reference to FIGS. 6, 7, 8, 9, and 10.

Figure 7 shows the output ck2 of the exclusive OR circuit 22.
The operating waveforms are shown. By performing an exclusive OR on the clock signal ck and the delayed signal ckl, if there is a clock signal ek, its edge is output, and if there is no clock No. 1 ck, it becomes H.
Even if it is stopped at L level, even if it is stopped at L level, L
Maintain your level.

FIG. 8 shows the operation when the clock signal ck is normally supplied. When the start command signal ST is L, the flip 70 knobs 16 and 17 are reset, so the motor start switch control signal STI is at L level, and the motor 11 is in a stopped state. Here, the signal ck2 is also input to the flip 70 knob 160 set terminal.
As mentioned above, since reset is given priority over set, the output Q1 is at L level.

Next, when the activation command signal ST changes from the L level to the H level, the reset of the flip 70 knobs 16 and 170 is released and the set input and T input are received. In this case, the clock signal ck is being supplied normally, so when the edge of the clock signal ek is input, the output ck2 of the exclusion OR circuit becomes H level, and the 7rip 70rub 16 is immediately set. Its output Q1 becomes H level. Therefore, the motor start switch control signal STI becomes H level, and the motor 11 enters the start state. When the motor 11 starts rotating, an FG flaw signal is generated.

As shown in FIG. 8, when the rising edge of the FC signal is first detected, the flip 70 knob 16 samples the value of Dl, that is, the L level, so the output Q changes to the L level, and the motor starts. The switch control signal STI becomes L level and the motor 11 is returned to the stop mode. However, when the clock signal ek is input, the flip-flop 16 is set again, and the motor 11 returns to the starting state again.

Next, when the fall of the FG flaw signal is detected, the flip-flop 17 samples the output Q1 of the flip-flop 16, that is, the H level, and the output Q2 outputs the H level. After that, whenever the rising of the FG signal is detected, the output QL of the 7-lip 70-tube 16 becomes -LK for an instant due to the above-mentioned operation, but since the output Q8 of the flip-flop 17 becomes H, the motor start switch is controlled. Signal ST1 should be held at H level.

FIG. 9 shows the operation when the supply of the clock signal ck is stopped from the beginning. First, when the start command signal ST is at the L level, the motor 11 is in a stopped state in the same manner as described above. Next, when the start command signal ST goes to H level, the reset of the flip 70 flip 16.17 is released and it begins to accept the set input and the T input, but since the clock signal ck is not supplied, the exclusive - The output ek2 of the OR circuit is at L level due to the above operation. Therefore, flip-flop 1
6 is not set. Therefore, the motor 11 is held in a stopped state.

FIG. 1O shows a case where the supply of the clock signal ck is stopped while the motor is rotating under normal control. First, it is assumed that the normal operation described in FIG. 8 is performed and the position is in the fixed position state.

In this state, when the supply of the clock signal ck is stopped, the F'J block flop 16 samples the data L at the rise of the FG scratch signal, and its output Q1 becomes L level. However, since the clock signal ck is not supplied, the flip 70 knob 16 is not set again.
Output Q1 holds the L level value.

Further thereafter, at the fall of the signal FC'X, the flip-flop 17 samples the output Q of the flip-flop 16, so that the output section changes from the H level to the L level. Therefore, the output Q1 of two 7 lip 70 lip
and Q2 both go to L level, motor start switch control signal STI goes to L level, and motor 11
transitions to a stopped state.

As described above, according to this embodiment, even if the supply of the clock ck is stopped while the motor 11 is rotating under normal control, the motor 11 can be brought to a stopped state.

Although the above embodiment is an example in which the present invention is applied to the motor control device 1, it is contemplated that the present invention can be applied not only to motor control circuits but also to other circuits that perform digital processing using a basic clock. It's obvious.

In other words, by connecting the protection circuit of the present invention to the path of the command signal for transitioning from the initial state to the rhythmic state, the initial state can be maintained when there is no clock signal. Also, when the clock signal stops at some point, it should be possible to return it to the initial state.

(Effects of the Invention) According to the present invention, in a control device using a digital processing circuit, when the supply of the basic tarok stops and the function of the control circuit stops, the controlled @ device is always in a stopped state, It has the effect of improving safety because it can prevent runaway behavior.

Particularly, when the controlled device is a motor, it is possible to prevent the motor from running out of control, and this effect is remarkable when used in a VTR, mag camera, etc.

Furthermore, the present invention can be implemented within an IC.

There is no need for an increase in the number of external parts or an increase in costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the motor control device according to the present invention, FIGS. 2, 3, and 4 are waveform diagrams showing the operation of FIG. 1, respectively, and FIG. Block diagram showing another embodiment of the motor control aiIjl according to the invention, No. 6
5 is a circuit diagram showing an example of a specific circuit of the block in FIG. 5. FIGS. 7, 8, 9, and 10 are waveform diagrams showing the operation of FIG. The figure is a block diagram showing an example of a conventional motor control device.
This is a waveform diagram showing the signals of each part in FIG. 1... Frequency-voltage converter, 2... Basic clock generator, 3... Wave number generator, 8... D/A converter, 9... Motor start switch, 10...
・Drive amplifier, 11...Motor, 12...
Start command signal input 1, 15...Motor start switch control circuit

Claims (3)

[Claims] (1) In a circuit that performs digital processing using a basic clock signal, a detection means for the basic clock signal is provided in the path of a command signal for transitioning from an initial state to an operating state,
A protection device for a digital processing circuit, characterized in that when generation of the basic clock signal stops, transition from the initial state to the operating state is prevented, regardless of the contents of the command signal. (2) A circuit that performs digital processing using the basic clock signal includes means for detecting rotation of the motor, means for frequency-voltage conversion of the output by digital processing, and a clock signal for operating the frequency-voltage conversion means. The circuit includes a generating means, a driver for driving the motor, and a circuit for transmitting the output of the frequency-voltage converting means to the motor driver to provide negative feedback to the motor, and the clock signal detecting means is in the negative feedback circuit. A protection device for a digital signal processing circuit according to claim 1, further comprising: a protection device for a digital signal processing circuit according to claim 1. (3) The clock signal detection means receives a signal from the rotation detection means of the motor, and checks the presence or absence of a clock signal at an edge of the signal. A protection device for the described digital processing circuit.