JP2742371B2 - Motor start circuit in microcomputer servo system of VTR - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor starting circuit in a speed servo system in a VTR (video tape recorder).

[0002]

2. Description of the Related Art In a VTR, a microcomputer (hereinafter referred to as a "microcomputer") controls the speed of a motor for driving a head drum and a motor for driving a capstan.
What is done using is becoming mainstream. FIG. 3 shows such a conventional example with respect to a head servo system. In the figure, the speed control of the motor 36 is performed as follows. First, the output of the free-run counter 31 that counts the clock CLK is latched by the input capture register 32 every time an FG pulse from the motor enters.

The time between two subsequent latch data is obtained by the CPU 33 and compared with a reference value.
Calculate the difference. In the PWM generation circuit 34, this CP
A PWM (pulse width modulation) signal is output based on the data of the operation result of U33. This PWM signal is applied to a driver circuit 35 after being smoothed by a smoothing circuit including a resistor R and a capacitor C. 37 is a pulse amplifier for amplifying the FG pulse.

Before such a speed control operation is performed, the motor 36 must be started. This start is performed by the timer 38 → the overflow flag generation circuit 3
9 → CPU 33 → PWM generation circuit 34 → Driver circuit 3
5 → via the path of the motor 36.

When the power is turned on to the VTR, the free-run counter 31 operates, but the motor 36 is stopped, so that no FG pulse is generated, and the input capture register 32 does not perform a latch operation. Also, CP
Since U is interrupted by the FG pulse and performs an operation related to speed control, the above-described calculation is not performed in a state where no FG pulse is input. On the other hand, the timer 38 monitors that the free-run counter 31 exceeds a predetermined count value. When the count value of the free-run counter 31 exceeds the predetermined value, the timer 38 triggers the overflow flag generation circuit 39. As a result, an overflow flag is generated from the overflow flag generation circuit 39. This flag is processed by the CPU 33, and a start pulse is output from the PWM circuit 33 based on the flag. This start pulse is used for starting the motor 36 through the driver circuit 35.

As described above, when the motor 36 is started, the FG pulse is applied to the timer 38 to reset the timer 38. Accordingly, the output (overflow flag) of the overflow flag generation circuit 39 is also reset. On the other hand, input capture register 3
1 performs a latch operation by the input of the FG pulse, and C
The PU 33 is also interrupted by the FG pulse, and performs the operation related to the speed control described above.

[0007]

In the above conventional example, the CP
U33 requires a start-up program different from the speed control, and the start-up program requires an operation of constantly checking whether or not a start-up signal (overflow flag) is input even when the motor is stopped. ,
There is a disadvantage that the load on the CPU 33 and software is large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a motor starting circuit in a microcomputer servo system of a VTR so that the starting signal does not need to be checked by software. And

[0009]

In order to achieve the above object, a motor starting circuit according to the present invention comprises a free-run counter for counting clocks, and latches the output of the free-run counter every time an FG pulse from the motor is input. An input capture register, a CPU for calculating a time between two successive latch data of the input capture register, and a PWM based on a calculation output of the CPU.
A PWM circuit for outputting a signal, a driver circuit for driving a motor based on the output of the PWM circuit, and an overflow when the free-run counter exceeds a predetermined count value corresponding to a time sufficiently longer than the period of the FG pulse. An overflow flag generating circuit which outputs a flag and is reset by an FG pulse, and means for giving an output of the overflow flag generating circuit to the driver circuit as a motor start signal without passing through a CPU.

[0010]

When the power switch of the VTR is turned on to operate the free-run counter and the count value exceeds a predetermined value, an overflow flag is generated, and the overflow flag is directly supplied to the driver circuit without going through the CPU. The motor is started by the overflow flag. Therefore, the CPU does not need a start-up program, and does not need to go to the input of a start-up signal (overflow flag). When the motor starts, F
A G pulse is generated and the overflow flag is reset. On the other hand, the generation of the FG pulse causes the input capture register and the CPU to enter the speed control operation.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. In FIG. 1 embodying the present invention, reference numeral 1 denotes a free-run counter that counts a clock CLK, and its output is supplied to an input capture register 2 and a timer 8. The input capture register 2 latches the output of the free-run counter 1 every time the FG pulse is input. 3 is CP
If the following two latch data of the input capture register 2 are D ₁ and D ₂ , and the reference value is D, an operation of (D ₂ −D ₁ ) −D is performed, and the operation result is expressed by the PWM circuit 4. Give to.

The PWM circuit 4 outputs a PWM signal based on data provided from the CPU 3. This output is provided to the driver circuit 5 via the OR circuit 10 and drives the motor 6. Incidentally, smoothing circuit 1 consisting of resistor R ₁ and capacitor C ₁ before the PWM signal is input to the driver circuit 5
It is smoothed by 1.

When the motor 6 is not rotating (stopped), the input capture register 2 and the CPU
3. The PWM circuit 4 does not perform the above operation. When the motor 6 is started from a stopped state, the free-run counter 1 counts a predetermined count value (this value is FG when the motor is rotating).
The timer 8 triggers the overflow flag generation circuit 9 when it exceeds the threshold value of the pulse which is sufficiently longer than the threshold value. In this case, the overflow flag is provided to the output terminal 12 of the IC (microcomputer) 13 via the OR circuit 10. The overflow flag is supplied to the driver circuit 5 through the smoothing circuit 11 and is used for starting the motor 6.

When the motor 6 starts, an FG pulse is generated and the input capture register 2 and the CPU 3 start operating. On the other hand, since the FG pulse resets the timer 8, the overflow flag generation circuit 9 is also reset, and the overflow flag is reset. In Figure 2 (a) shows an overflow flag, rises to a high level at the free running counter 1 overflow flag generating circuit 9 by the timer 8 is triggered by exceeding a predetermined count value T _1, FG pulse It is reset falls to the low level at T ₂ by.
(B) in FIG. 2 shows the PWM signals generated later than T _1.

As described above, in this embodiment, the overflow flag is directly supplied to the driver circuit 5 without the intervention of the CPU to start the motor 6, so that a start program is not required for the CPU 3; 6 will not be involved.

[0016]

As described above, according to the present invention, C
The PU does not need a start-up program, and does not need to go to the input of a start-up signal (overflow flag). Therefore, the load on software is reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a motor starting circuit of a microcomputer servo system embodying the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation.

FIG. 3 is a diagram showing a conventional motor start circuit of a microcomputer servo system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Free run counter 2 Input capture register 3 CPU 4 PWM circuit 5 Driver circuit 6 Motor 8 Timer 9 Overflow flag generation circuit 12 Output terminal 13 IC (microcomputer)

Claims (2)

(57) [Claims] 1. A free-run counter for counting a clock, an input capture register for latching an output of the free-run counter each time an FG pulse from a motor is input, and a time between two successive latch data of the input capture register And a P that outputs a PWM signal based on a calculation output of the CPU.
A WM circuit; a driver circuit for driving a motor based on the output of the PWM circuit; and an overflow flag when the free-run counter exceeds a predetermined count value corresponding to a time sufficiently longer than the period of the FG pulse. And an overflow flag generation circuit reset by an FG pulse, and means for giving the output of the overflow flag generation circuit to the driver circuit as a motor start signal without the intervention of a CPU. . 2. A free-run counter for counting a clock; a latch circuit for latching an output of the free-run counter in response to an input of an external pulse; and a time between two successive latch data of the latch circuit. and a CPU for outputting the operation result, a PWM circuit for outputting a PWM signal to the output terminal based on an output of the CPU, than the period of the free running counter is the external pulse
An overflow flag generating means for outputting an overflow flag when a predetermined count value corresponding to a long time is reached and outputting the overflow flag to the output terminal without passing through the CPU.