JPS62297017A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To produce a desired pulse width, by a method wherein a first counter is turned ON and OFF at a stationary period by means of a clock signal from a clock circuit, an output from the first counter is triggered, and a second counter is driven to turn ON and OFF. CONSTITUTION:An address decoder 27 is connected to an CPU 23 through an address pass 25, and an LSI 31 is connected thereto through a data pass 29. An output out 1 from a first programmable counter C1 of the LSI 31 is a square wave of a stationary period. The CPU 23 instructs a single shot of a pulse width T2on to a second programmable counter C2 of the LSI 31. In which case, the counter C2 outputs a pulse of a pulse width T2on each time a gate G rises to a level 'H'. An output pulse from the counter C1 is triggered, and the counter C2 is driven to turn ON and OFF to provide an output with a desired pulse width.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) This invention relates to a pulse generation circuit, and is used, for example, to control switching elements of a power source for electric discharge machining in an electric discharge machine. The present invention relates to a pulse generation circuit that can generate pulses.

(Prior Art) Conventionally, as a pulse generation circuit for controlling a switching element of an electric discharge machining power supply of an electric discharge machine that uses a switching element to apply a voltage pulse to a machining gap, a circuit as shown in Fig. 3 has been used. be.

In this conventional pulse generation circuit, the CPU 1 has the latch 3,
On-Ton and off-Ton data are written into the data bus 5 and the address decoder 9, respectively. The counters 11 and 13 are configured to count clock signals using the output of the latch 3.5 as preset data.

Therefore, when the counter 13 counts up at a certain moment, the count up signal 15 of the counter 13 becomes the load signal q of the counter 11, and this counter 11 outputs the latch 3.
Load the output data of and continue counting. When the counter 11 counts the data in the latch 3, it outputs a count-up signal 17, which is sent to the counter 1.
3 becomes the load signal. Therefore, this counter 13 loads the data of the latch 5 and continues counting.

When the counter 13 counts the data in the latch 5, it outputs the count-up signal 15 again.

This interaction is repeated thereafter.

Therefore, the count-up signal @15 corresponds to the beginning of the Ton time, and the count-up signal 17 corresponds to the beginning of the Toff time. The count-up signal 15 becomes the S input signal of the flip-flop 19, and the count-up signal 17 becomes the R input signal of the flip-flop 19.
In the end, the output signal @21 of the flip-flop 19 becomes a pulse signal for the switching element fThl till.

By the way, in general, the output voltage pulse of a power source for electrical discharge machining using a switching element is between T onlR and Ton
Since it is necessary to accurately υJtiD over a wide range of time, presettable counters are used for each of Ton and Toff to generate switching control pulses under accurate time control.

However, if a presettable counter like the one above is used as a CP
If you try to put it under LI control, you will need a latch circuit for connecting to the CPU data bus, and other things in addition to a preset counter with the necessary number of bits to obtain the resolution and maximum time required for T0n1Toff. , there was a problem that the circuit became large scale.

(Problems to be Solved by the Invention) As described above, in the conventional pulse generation circuit for the electric discharge machining power source of the electric discharge machine, there is a problem that the scale of the circuit cannot be avoided.

The present invention has been made in view of such conventional problems, and provides a pulse generation circuit for an electric discharge machine that can generate pulses with a relatively simple configuration using at least two counters. The purpose is to provide

[Structure of the Invention] (Means for Solving Problems) The pulse generation circuit of the present invention includes a clock signal circuit, a first counter, and uses an on/off signal from the first counter as a trigger to generate a desired signal. and a second counter that generates a pulse having a pulse width.

(Function) In the pulse generation circuit of the present invention, the first counter is turned on at a fixed period by the clock signal of the clock signal circuit.
Using the output pulse of the first counter as a trigger, the second counter is turned on and off to obtain an output with a desired pulse width.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which an address decoder 27 is connected to the CPU 23 via an address bus 25. Further, an LSI 31 is connected to the CPU 23 via a data bus 29. This LSI 31 is equipped with two or more programmable counters.

A buffer 33 is connected to this 18131.

As shown in FIG.
7 and the first programmable counter C built into the LSI 31 via a control signal line not shown in the figure.
1 to command continuous oscillation with a fixed period Ton+Toff.

The output of this first programmable counter C1 is
1 is a square wave with a fixed period T on+T oH.

Next, the CPU 23 instructs the second programmable counter C2 built in the 18131 to output a single shot with a pulse width T20n. Therefore, the second programmable counter C2 outputs a pulse with a pulse width T20n every time the gate G rises to the °°H'' level.

Thus, the output o of the first programmable counter C1
ut 1 is a continuous oscillation with a fixed period T on + T off, and the output out of the second programmable counter C2
2 is triggered by out 1 and outputs a pulse with a pulse width T2on, so in the end, output out 2 is the setting layer 1
11 H with a period equal to 11 T on + T off
11, 11L This becomes a continuous pulse that repeats 11.

And the output out 2 of this second programmable counter C2 is a buffer? 33, it becomes a switching element control signal for the electrical discharge machining power supply of the electrical discharge machine.

Therefore, in the pulse generation circuit of this embodiment, the first counter is driven on and off at a fixed period by the clock signal of the clock signal circuit, and the output pulse of the first counter is used as a trigger to drive the second force counter. Drive on, off,
Obtain the desired pulse width output.

[Effects of the Invention] Since the present invention has the above configuration, it is possible to use the pulse output of the first counter as a trigger, and obtain a pulse output with a desired pulse width by the second counter. FIG. 2 is a timing chart showing the operation of the above embodiment, and FIG. 3 is a circuit block diagram of a conventional example.

23...CPU 27...Address decoder 31...LSI 33...Buffer C1...First programmable counter C2...Second programmable counter G...Gate agent Patent attorney Miyoshi Miyoshi Yasuo Figure 3

Claims (1)

[Claims] A first counter that is turned on and off at a fixed cycle by a clock signal from a clock signal circuit, and a second counter that outputs a pulse with a desired pulse width using the output pulse of the first counter as a trigger. A pulse generation circuit comprising: