JPS60120572A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an insulated gate field effect transistor of ultrafine size without punch-through by using 2-valency ions in case of implanting ions on the channel region of the treansistor. CONSTITUTION:A field oxide film 2 is formed on an N type Si substrate 1, then photoetched, P type impurity is diffused, and source 3 and drain 4 of a P-channel MOS transistor are formed. Then, before forming a gate oxide film, 2-valency ions 8 are implanted. When using a crystalline surface 100 N type Si substrate, ion channeling effect is directed in the direction of ion implanting in the crystalline surface direction (100) at the maximum. To prevent a punch-through, the dosage is necessarily set at approx. 10<11>/cm<3>, and 2-valence impurity region 9 is formed in depth of approx. 0.5micron from the surface of the Si substrate. Then, a gate oxide film 5 is formed, a contacting region 10 is formed on the source 3 and the drain 4, and wirings 11 are formed, thereby forming a P-channel MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to an improvement in a method for manufacturing a semiconductor device by implanting impurities in an ionized state.

When manufacturing semiconductor devices, particularly insulated gate field effect transistors, ion implantation is used to control the threshold voltage. Conventionally, an insulated gate field effect transistor (insulated gate field effect transistor) having a necessary threshold voltage has been formed by shallow ion implantation into a semiconductor substrate of a certain conductivity type.

For example, as shown in FIG. 1, in the case of a P-channel VMO8 type O8 transistor, a feed oxide film 2 is formed on an N-type silicon substrate 1, and P-type impurities are introduced into the source 5 and drain 4. was formed, a gate oxide film 5 was formed, and boron ions 6 were implanted into the channel region 7 near the interface between the gate oxide film 5 and the N-type silicon substrate 1.

However, with the increasing integration of semiconductor devices, the dimensions of individual insulated gate field effect transistors have also become smaller, and it has become difficult to form transistors with a single ion implantation process as in the past. , the source and drain are empty inside the silicon substrate channel region.
The problem of the so-called punch-through effect, which is a phenomenon in which layers are connected, has become clear.

To solve this problem, conventional methods have been to increase the concentration of the semiconductor substrate itself to prevent punch-through, or to implant impurity ions into the channel region, and then use thermal diffusion to penetrate the channel region and inside. I went with it by putting it in.

In this case, in the former case, the substrate concentration itself becomes high, and as a result, the junction capacitance of each source and drain increases, and the mobility of the transistor decreases. In the latter case, since thermal diffusion must be performed in addition to ion implantation, a decrease in productivity cannot be avoided.

The present invention was made in view of this situation, and its purpose is to eliminate punch-through.
The present invention provides an insulated gate field effect transistor with extremely small dimensions.

Hereinafter, the method for manufacturing an insulated gate field effect transistor according to the present invention will be explained in detail with reference to FIGS. 2 to 5.

As an example here, a P-channel/l/MO8 type transistor used as an example up to now will be described. As shown in FIG. 2, an N-type Si substrate 1 with a crystal plane (100) and a resistivity of 10 Ω·F or more is prepared.

Next, the field oxide film 2 is oxidized using a conventional method.
The source 3 and drain 4 of the P-channel/L/MO transistor are formed by diffusing P-type impurities using a photoetching method. In small-sized MOS transistors, this P-type impurity introduction step is often performed in a self-alignment manner after gate formation.

Next, as shown in FIG. 3, phosphorus ion implantation 8 is performed before forming the gate oxide film. One of the characteristics of the ion implantation performed here is that the exposed 3+ substrate surface is
Ion implantation is performed using divalent phosphorus ions with an ion acceleration energy of 150 KEY or more.

Another feature is that when using an N-type B+ substrate with a (100) crystal plane, the ion implantation is performed with the crystal plane orientation (110>, where the ion channeling effect is maximum, facing the direction of ion implantation. In this case, the angle is 45 degrees.Also,
At this time, as shown in Figure 3, in order to implant ions into the channel region and inside the micrometered transistor with good uniformity, the substrate is held at a 45 degree angle. Make the planetarium rotate. Also, to prevent bunch through, the dose is 10”/crr.
By doing this, a phosphorus impurity region 9 is formed at a depth of about 0.5 microns from the surface of the SI substrate, as shown in FIG. 4. Finally, as shown in FIG. 5, a gate oxide film 5 is formed, a contact region v1.10 is formed on the source 3 and drain 4, and a wiring part 11 is formed, thereby forming a P-channel MOS. A transistor is formed. To control the threshold voltage of the MOS transistor, the concentration of the initial N-type Si substrate is selected appropriately.

As described above, according to the present invention, it is possible to suppress punch-through even in a miniaturized insulated gate transistor with a single ion implantation. Therefore, there is no need to introduce an impurity layer, and it becomes possible to manufacture highly productive, highly integrated, pattern-thin devices.

For the above, P channel 5M using N type B+ substrate
08) Although the description has been made regarding the range nut, it goes without saying that it can be applied to N-channel/L/type MOS transistors using a P-type Bl substrate, as well as to CMOS transistors in which these are integrated.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a MOS transistor for explaining a conventional method of manufacturing a MOS transistor, and FIGS. 2 to 5 are process orders for explaining the steps of an embodiment of the present invention. This is a cross-sectional view. 1...N-type silicon substrate, 2...Field oxide film. 3...source, 4...drain, 5...gate oxide film. 6...Boron ion, 7...Channel region, 8...
・Rinne ion, 9... Rinne blunt area, 10... Contact area, 11... Wiring department and above Applicant Seiko Electronics Co., Ltd. Agent Patent Attorney Mogami Affairs Figure 1 jlN! l lI2 Figure 3 Figure 4 (Figure 115)

Claims (1)

[Claims] (1) In the case of ion implantation into the channel region of the transistor in an insulated gate field effect transistor.
A method for manufacturing a semiconductor device, characterized in that the method is performed using valence ions. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the ion implantation is performed at an angle where the maximum channeling effect occurs in the semiconductor substrate. (6) The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor substrate is exposed and ion implantation is performed before forming the gate oxide film. (4) The method for manufacturing a semiconductor device according to claim 6, characterized in that ion implantation is performed while rotating the substrate.