JPS60119744A - Forming process of element isolating region - Google Patents

Abstract

PURPOSE:To flatten buried layers while simplifying the production process by a method wherein grooves with width not exceeding specified value are formed on a semiconductor substrate to form oxide films inside these grooves filling their internal peripheral side with burying material. CONSTITUTION:N<+> type buried layers 2 are formed in a P type semiconductor substrate 1 and the N type epitaxial layers 4 are formed to form P<+> type regions 3 for leveling up the semiconductor 1. Firstly thick SiO2 films 5 are formed by means of selective oxidizing technology. Secondly Si3N4 films 11 and poly Si 12 deposited to form a pattern leveling resists 13 only on the parts to be formed into grooves. Thirdly the pattern is implanted with B utilizing the resists 13 as masks. Fourthly the resists 13 are removed to diffused B. Fifthly the concentration regions of Si 12 specified by the size not exceeding around 1mum are formed to open the Si 12 by the differential etching process forming deep grooves starting from the openings. Sixthly P<+> regions 16 are formed at the bottoms of the grooves. Seventhly the grooves are oxidized to form oxide films 17 filling in the space exceeding half of the groove width. Finally the grooves may be filled with poly Si 15.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to an improvement in element isolation technology for semiconductor integrated circuits, for example, when multiple semiconductor elements such as bipolar transistors, MISFETs, etc. This relates to the technology of integrating a plurality of integrated circuits.

[Background Art] For semiconductor integrated circuits, for example, bipolar integrated circuits (hereinafter referred to as bipolar ICs), the applicant of the present application has proposed an element structure as shown in FIG. No. 153910). In the figure, reference numeral 1 is a P-type silicon semiconductor substrate, and reference numeral 2 is an N+ type buried layer. On the buried layer 2, an N-type epitaxial layer 4 is formed.
is formed, and in this epitaxial layer 4, a collector region 8 and a base region 9 constituting a bipolar transistor element are formed.
and an emitter region 10 are respectively formed.

By the way, in order to isolate the bipolar transistor elements, a technique is known in which deep grooves are formed in the semiconductor substrate 1 and the grooves are filled with a filling material such as polycrystalline silicon or silicon dioxide (SiO2) to isolate the elements. ing. Reference numerals 6 and 7 indicate polycrystalline silicon buried in the trench and polycrystalline silicon oxide film after planarization, respectively. Further, reference numeral 5 is a silicon oxide film, and reference numeral 16 is a P+ channel stopper. Such an element isolation method can reduce parasitic capacitance and required area, and is advantageous for high integration.

However, according to the studies of the present inventors, there are the following secondary problems. The depth of the trench required for element/isolation in bipolar ICs is determined by the thickness of N+ buried WI2 and the film thickness of epitaxial WJ4, and is, for example, 2.5 mm.
~3.5μ+r− is required.

Therefore, in order to fill the groove, it is necessary to deposit the embedding material at least as deep as the groove, that is, 2.5 to 3.5 μm or more. This generally means that when considering deposition during the manufacturing process of integrated circuits, the film thickness is 0.
It is about 1 to 0.3 μm, but it is an “unique” process that is more than an order of magnitude larger. Furthermore, it is necessary to flatten the surface of the substrate after embedding, but the qt flattening process becomes complicated due to such thick deposition.

[Objective of the Invention] The object of the present invention, which was made in consideration of the large and unique process of buried planarization, is to simplify the process of forming an element isolation region of a trench buried structure and to improve the packaging density. .

Another object of the present invention is to form a groove by selective etching using impurity diffusion in polysilicon and a difference in impurity concentration in order to form a groove with a size smaller than this critical dimension using current microfabrication technology; The object of the present invention is to provide a method of utilizing the groove for element isolation.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, in order to fill the trench with a deposition of about 0.3 μm, I was poured into the sidewall of the trench.

This allows the groove width to be less than twice the film thickness to be deposited.
That is, if the thickness is 0.6 μm or less, the groove can be filled by deposition from the side wall. For this reason, by forming grooves by selective etching using impurity diffusion in polysilicon and the difference in impurity concentration, Q, 57
Since a trench of 1 m or less can be formed, the filling and planarization process can be simplified and the packaging density can be improved.

Thus, in the present invention, the groove width for element isolation is generally 1 μm.
An oxide film formed by oxidizing the semiconductor substrate itself is formed on the side wall of the trench to be at least about half the width of filW, and the narrow gap is filled with the embedding material.

[Example] Hereinafter, a second example in which the present invention is applied to a bipolar IC will be described.
This will be explained with reference to FIGS. Note that the same elements as those shown in FIG. 1 are indicated using the same reference numerals.

In FIG. 2, according to the conventional manufacturing process of bipolar IC, an N+ type buried layer 2 is formed on a P type semiconductor substrate, and then an N type Ebitex layer 4 is formed to form a 1]+ type region for pulling up the substrate; form 3. Next, a thick SiO
Dioxide film 5 is formed by selective oxidation technique using silicon nitride (Si3N4) as a mask. Thereafter, a silicon nitride film 1-1 and polysilicon 12, which are masks necessary for forming the groove, are deposited, and a pattern is formed so that the resist 13 is left only in the area where the groove is to be formed. The patterning of this resist 13 is performed using current microfabrication technology, for example, 1.5 to 2.5
The width is μIl+0. Boron is implanted using the resist 13 as a mask. The thickness of the silicon nitride film 11- is 1
Since it serves as a mask for forming silicon grooves in the next step of reactive ion etching, it is determined by the selection ratio between silicon and silicon nitride films.For example, if the etching ratio between silicon and silicon nitride films is 15, the thickness is 280 mm.
Approximately 0 angstrom is required. Further, although it is desirable that the polysilicon 12 be thin, a thickness of about 1000 angstroms is appropriate since the polysilicon 12 is oxidized in the first step and serves as a mask for etching the silicon nitride film 11. The dimensions of the patterned resist are 1.
The opening may be about 5 to 2.5 μm. The dose profile of boron is lXl01″”/cd. As a result, boron is implanted into the portion of the polysilicon 12 other than the portion below the resist 1 13.

In Figure 3, resist 1-3 is removed and heated to 950°C.
, IO minutes, boron is diffused in the lateral direction of the polysilicon, and hydrazine etching is performed on the entire surface. Hydrazine etching etches only the areas where boron is not diffused. After annealing at 950℃ for 10 minutes, boron diffuses by about 0.8μm on one side.
A 0.4 μIn hole 1111 is formed by a 2 μffl resist mask. In this way, the dimensions of the holes are determined by the dimensions of the resist mask and the annealing conditions. The remaining polysilicon 12t, . . . is entirely oxidized to form a polysilicon oxide film 14. Using this polysilicon oxide +aJ-4 as a mask, silicon nitride film J
Using the silicon nitride film +1 as a mask, the underlying oxide film 5 is etched to expose the silicon surface. In this case, the polysilicon oxide film 14 is removed by etching the underlying oxide film 5.

In FIG. 4, using the silicon nitride film 11 as a mask,
Deep trenches are formed by dry etching the silicon. The depth of the groove is determined by increasing the depth of the N+ layer 2.
Considering that the width of the N+ buried layer 2 is 1.2 μm and the thickness of the epitaxial layer is 1.4 μIn, it is necessary to dig 3 μm or more. The silicon nitride film 11 serving as a mask remains approximately 800 Å-1-Roam after silicon dry etching. Etching is a reactive method with less side etching.
Since etching is used, a groove with a groove width of 0.4 μIl+ and a depth of :':) μm is formed as described above. Thereafter, in order to remove the damaged layer caused by dry etching, silicone etching is performed using hydrofluoric nitric acid to a thickness of approximately 0.1 .mu.Il+ on the "1" side, resulting in a trench width of 0.6 .mu.In.

Also, a P+ region 16 is created under ilI by ion implantation.

In FIG. 5, using the remaining silicon nitride film 11 as a mask, the inside of the trench is oxidized by 0.4 μm to form an oxide film 17 inside the trench. As a result, the remaining width of the groove to be inserted in the next 1:00 minutes is 0.2 μm. Next, polysilicon 1-5 is deposited to embed the material. This deposition thickness is the remaining RI! ' is 2 (J00 Ongeström (0,
Since it is narrow (2 μm), it can be sufficiently filled with polysilicon of about 2,500 angstroms, and flattening can be made thinner, which facilitates simplification. Furthermore, i
fl'i can also be buried with an insulating material F having good step coverage, such as silicon nitride. Note that the 11ζ width was further reduced, and the groove width before selective oxidation within the groove was reduced to 0. /lμI1
If it is set to 1 or less, the grooves will be blocked by oxidation 1 prevention during selective oxidation, and the special problem of burying can be eliminated.

In FIG. 6, a polysilicon oxide film 18 is formed in 11 parts of the first polysilicon (the first polysilicon), and a collector region 8, a base region 9, and an emitter region 10 are formed using the bipolar IC technology from FIF. , i: '6 to form the required separated bipolar, (f T-.

FIG. 7 is a diagram showing the relative dimensions and positions of the mask patterns used in the above embodiments, in which numeral 19 is a boron implant mask, 20 is a field oxide film mask,
21 is an emitter mask, and 22 is a collector contact 1 to mask.

[Effects] As explained above, in the present invention, the width of the groove formed on the semiconductor substrate is about 1μI11 or less, and at least half of the groove width is formed on the inner circumference of the groove by oxidation of the substrate itself. Since an oxide film is formed to a certain extent and a buried material such as polysilicon is buried in the inner circumferential side of this oxide film, an element isolation region with a simplified buried flattening process can be obtained. .

Furthermore, when forming the grooves using boron diffusion in polysilicon and etching with a concentration difference,
It is possible to form the J method with good control, which is less than the limit usage determined by microfabrication technology using photolithography, and it is possible to effectively simplify the embedding planarization process.

Although it deviates slightly from the spirit of the present invention, by narrowing the R'S' width, the inside of the trench is simply oxidized to close it, and the embedding process itself is omitted, further simplifying the process. I can also recommend it.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Field of Application] The above description describes the case where the present invention is applied to bipolar devices. It is applicable not only to memory but also to complementary metal oxide semiconductor chips.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a bipolar IC formed by conventional deep groove isolation, FIGS. 2 to 6 are cross-sectional views of the steps of an embodiment of the present invention, and FIG. , the same process shown as an example J1]uN
FIG. ~ 1-... Semiconductor substrate, 11-... Silicon nitride film,
12.15...Polysilicon, 13...Ho1~Resist 11.7...In-groove oxide film. Figure 1 Figure 6

Claims (1)

[Claims] 1. - An element isolation region for isolating a plurality of semiconductor elements on a semiconductor substrate, the groove being formed on the semiconductor substrate and having a width of approximately 1 μm or less and a depth greater than the width. , an oxide film formed on the inner periphery of the groove by oxidation of the substrate itself and occupying at least half of the width of the groove, and a embedding material embedded in the inner periphery of the oxide film. Characteristic element isolation region. 2. Place the hole-drilling mask used to form grooves that separate multiple semiconductor elements on the same semiconductor substrate into holes 1-1.
After removing unnecessary photoresist using this hole-drilling mask, impurities are removed from the polysilicon film formed on the semiconductor board. selectively diffusing the polysilicon film, and then forming a concentration difference region of the polysilicon film defined by the method of "about 1 μIn or less" smaller than the hole size, and opening the polysilicon film by concentration difference etching, Forming a groove for element isolation in the semiconductor substrate based on this opening, and then forming an oxide film occupying at least half of the width i/, j1 on the inner periphery of this groove by selective oxidation. A method for forming an element isolation region, comprising embedding a embedding material from the outside of the substrate into the inner peripheral side of the oxide film. 3. The method for forming an element isolation region according to claim 2, wherein the groove for element isolation is formed by reactive ion etching.