JPS6011971A - Bit integration circuit - Google Patents

Abstract

PURPOSE:To set the mean voltage of output at zero with a prescribed level of output amplitude and at the same time to facilitate the easy integration for a bit integration circuit, by applying the electric charge stored to a capacitor to the input terminal of an arithmetic amplifier via a switch group. CONSTITUTION:The mean voltage of an output terminal 21 is set at 0V and a swtich 19 is kept off. Under such conditions, the output V21 of an integrated circuit is equal to the sum of the one-sample preceding output and the value obtained by multiplying the electric field of an input terminal 8 by C2/C1. Therefore it is understood that the signal of the terminal 21 is equal to the sum of input signals of the terminal 8. The output voltage is forcibly set at 0V every bit by discharging the electric charge of a capacitor 17 by means of the switch 19. In such a way, a bit integration circuit is obtained. Then the clock of the terminal 8 is set at ''0'' and set in a state as shown in the figure. In such a case, the electric charge stored to the capacitor C2 is totally shifted to the capacitor C1 since the input terminal of an operational amplifier 18 is virtually grounded. In other words, no electric charge remains at stray capacitances C5 and C6.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a bit integration circuit used in a modulator/demodulator.

Conventional configuration and its problems FIG. 1 shows a conventional bit integration circuit.

The configuration of this conventional example will be explained below with reference to FIG. 1 is an input node 11 of a signal to be bit-integrated, and this input terminal l is connected to a resistor 3. The other end of this resistor 3 is connected to the negative input terminal of an operational amplifier 5, one end of a capacitor 4, and a switch 6. On the other hand, the output of the operational amplifier 5 is connected to the other end of the capacitor 4, the switch 6, and the output end 7. Further, the discharge control signal input terminal 2 for each bit is connected to a switch 6. Further, the positive input terminal of the operational amplifier 5 is grounded.

Next, the operation of the above conventional example will be explained with reference to FIGS. 1 and 2. The bit-integrated signal shown in FIG. 2(1)) is applied to the input terminal 1 in FIG.

This input terminal], the voltage transfer function If(s) of the output terminal 7
is given by the following formula (however, the switch is in the state of (monthly pa1.゛)).

This shows that since k is negative, the output has the opposite polarity, but the integral (F signal) of input terminal 1 is generated at output terminal 7.On the other hand, the discharge control signal for each bit of 1 in Fig. 2 is An integral output signal (
-4) corresponding to the charge on the capacitor 4 is discharged bit by bit. By the above processing, a t'' bit integrator circuit is obtained at the output terminal 7 in FIG. An example of the output waveform in this case is shown in FIG. 2 (cl). When this output signal is observed while synchronizing with bits, the waveform shown in FIG. 2 ((1)) is obtained.

This signal has the following convergence (at each point where it is led to the regulator circuit and bit-integrated, the state σ shown in FIG. 2(d)) ~
■The position of the object is detected.

However, in the above conventional example, if the signal shown in FIG. 2(b) contains a DC component or there is an input offset to the operational amplifier 5 in FIG. 1, the output waveform will change as shown in FIG. 2(e).
), and the next comparator detects the state incorrectly. On the other hand, when attempting to integrate this circuit, it is difficult to realize the resistor 3 and capacitor 4 shown in FIG. 1 with high precision.

Unfortunately, for example, the output waveform becomes a waveform as shown in FIG. 2(f), and in this case as well, there is a drawback that the state detection by the next comparator is erroneous.

OBJECTS OF THE INVENTION The present invention eliminates the drawbacks of the conventional example described in (-), and provides a human integrator circuit which has an average output voltage of zero (■) and a constant output amplitude, and which is easy to integrate. The purpose is to achieve this goal.

SUMMARY OF THE INVENTION The present invention achieves the above object by detecting the average level of the integrated output of a KW amplifier with a capacitor connected between the input and output terminals, and calculating the difference between this average level and the input voltage. By applying voltage to the capacitor via a group of switches and applying the charge accumulated in this capacitor to the input voltage of the wave-cutting amplifier via the group of switches, it is not affected by stray capacitance, and only the ratio of the capacitor can be calculated. The integral gain is determined by
This has the effect of reducing the amplitude deviation of the bit integral output.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, 8C is an input terminal for a 14-bit integrated signal, and this input terminal 8 is connected to a switch 14.

The other terminals of switches 1 and 1 are connected to one end of capacitor +6 and one end of switch 15. The other end of switch 15 is grounded along with the positive input end of operational amplifier 18 . The 2o average value detection circuit is connected to one end of the switch 12, and the other end of the switch 12 is connected to the other end of the capacitor 16 and one end of the switch 13.

The other end of the switch] 3 is the negative power end of the operational amplifier 18;
It is connected to one end of the capacitor 17 and one end of the switch 19. The output end of the operational amplifier 18 is connected to the capacitor 17
The other end of the switch 19 is connected to one end of the average value detection circuit I8 and the output end 21.

Input terminals 9, into which clocks for controlling the front and rear groups are input, are connected to switches 12.14, respectively, and also to one side 1'1.1 of the input 11. The output of this inverter]1 (l, switch 1.3, ]5
are applied to each. In addition, the above switch]2,]
3.14 and I5.19, for example, an analog switch is used.

Next, the operation of the above embodiment will be explained. 6. Now, if the voltage at the output terminal 21 in FIG. Ru. In this case, the transfer function from the input end 8 to the output end 21 is expressed by the following equation.Next, when the above equation is inversely Z-transformed and transformed into a time function, it becomes the following equation.

C.

I/21 (nl = 7'21 (nl, ) 10-18
(lLI) -・---(:111 From this equation (3), J: Output V of the sea urchin bit integrator circuit
2□ is C! between the output of one sample before and the electric field of input terminal 8. 2
10. It is expressed as the sum of the products multiplied by . It can be seen that the signal at the output terminal 21 is represented by the sum of the input signals at the input terminal 8. This output voltage is forced to zero (V) bit by bit by discharging the charge in capacitor 17 by switch 19. By operating in this manner, a bit integration circuit is realized.

Next, it will be explained that the characteristics of this circuit are not affected by stray capacitance. Each of the switches 12 to 15 is turned ON or 0FI depending on the polarity of the clock applied to the input terminal 9 in FIG.
− is controlled. Now, the clock of input terminal 9 is 1”
Then switch 12, ]4 is ON and switch 13.15 is O.
FF state is shown in Fig. 4 (a), and conversely, when the clock of input terminal 9 is °'0'', switch 12.14 is OFF and switch 13.15 is ON, as shown in Fig. 4 (1)). show.

03 to C6 in FIG. 4 are stray capacitances that are thought to have the most influence on the characteristics of this circuit. It will be shown below that these capacitances do not affect the characteristics. First, Figure 4 (a
), charges are accumulated in the capacitor C2 and the stray capacitance C3, C, along the broken line in FIG. In this case, stray capacitance a5. Since C, is grounded through switch 12, no charge is accumulated. Next, let us assume that the clock at the input terminal 8 becomes 0" and reaches the -4~ state shown in FIG. 1 (1). In this case, the charge accumulated in the capacitor C2 is Since terminal 1 of JJ becomes a virtual ground, all of it is transferred to capacitor C1.
'? for C6? 11 There are no shipments left. , and stray capacitance C3,
The charge i'L/I accumulated on C, is all discharged to ground by switch 15. As a result, all charges corresponding to the voltage at the input terminal 8 are carried by the capacitor C2 and are not affected by the free capacitance C1~Co, which adversely affects the characteristics of the integrator circuit. do not have.

Next, it will be explained that the average voltage at the output terminal 21 in FIG. 3 becomes zero (X?). If the total average voltage of output ☆: 1, 121 is tilted positively, then the average value test 11 God 1 road 2
A positive potential is generated at the output of 0. However, when accumulating charge in the capacitor 6 (02), the output of the average value detection circuit 20 is configured to be the basic potential, so the input potential of the input terminal 8 is Unless the potential is higher than the potential of the average value detection circuit 20, no charge can be accumulated in the capacitor C2. Conversely, when the average potential of the output terminal 21 is negative, a similar feedback is applied, and the average potential of the output terminal 21 is always zero (V).

The waveforms of each part are the same as those in FIG. 2 used to explain the conventional example, except for the polarity in FIG. 2(C). In other words, FIG.
(1)) and (C) are respectively input terminal 10.8 in Figure 3.
．． 21 waveform.

Effects of the Invention The present invention has the above-mentioned configuration, and realizes a switchable carrier/recircuit circuit that is not affected by the stray capacitance of the switch, and uses this to configure the circuit. In the case where the integral gain is integrated with a sharp rise, there is an advantage that the deviation of the voltage range of the output signal of the bit integration can be reduced. However, since the average of the outputs of the bit integration circuit is fed to the other input terminal of the switch, it also has the advantage of making the average potential of the circuit output zero (V).

[Brief explanation of the drawing]

Figure 1 is an electric circuit diagram of a conventional bit integration circuit, and Figure 2 (
a) to (r) A diagram explaining the operation of the matching circuit, FIG. 3 is an electric circuit diagram of the bit integration circuit in an embodiment of the present invention, and FIGS. 4 (a) and (1)) are explanations of the operation of the same circuit. It is a diagram. 8.9, IO/input terminal, 11 Inno kuichita, 12.1
3,]4.15...Switch, 16 Capacitor, 1
7 - capacitor, 18 - operational amplifier, 19 switch, 20 average value detection circuit, 21 output Q''lii; Name of agent Patent attorney Satoshi Nakao and 1 other person No. 1
Figure 2 / Figure 2

Claims (1)

[Claims] An operational amplifier with one input terminal grounded, a first capacitor connected between the other input terminal and the output terminal of this operational amplifier, and a charge equivalent to l bits accumulated in the first capacitor. a switch means for discharging; an average value detection circuit for detecting the average level of the output of the operational amplifier; and a first switch group for applying a differential voltage between the output of the average value detection circuit and the input voltage to a second capacitor. and a second switch group that opens and opens in response to the opening and closing operations of the first switch group and supplies the charge accumulated in the second capacitor to the input terminal of the operational amplifier. circuit.