JPS6218095B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention involves sampling an analog signal during successive time intervals each having a time width corresponding to n pulses of a clock pulse generator, and for each time interval The present invention relates to a device for digitizing an analog signal having a constant average value, which includes a delta modulator that outputs m(n) pulses according to the difference between a signal value and a signal value at the end.

Devices of this type can be used, for example, to digitize ECG signals for further processing. ECG
The signal is a substantially periodic signal with an average value equal to zero or the (constant) contact potential occurring between the electrode and the patient's skin. It has been determined that the inaccuracy of the delta modulator adds an error signal to this signal, interfering with subsequent processing. The purpose of the present invention is to remove these interfering error signals while leaving useful information intact.

For this purpose, the device according to the invention is characterized in that the output terminal of the delta modulator is connected to a correction circuit configured as a digital high-pass filter.

The present invention provides that the error signal produced by the delta modulator has a continuous, slowly increasing or decreasing property, so that such an error signal can be very high from an ECG signal, which practically does not contain very low frequency components other than the insignificant contact potential. This was done based on the confirmation of the fact that separation can be achieved using a pass filter.

In a preferred embodiment of the device according to the invention, the correction circuit is configured to reduce the signal applied to it by a progressive average value of the signal.

The invention will be explained with reference to the drawings.

FIG. 1 shows an example of a device according to the invention, from whose input terminal 1 an ECG signal is supplied to a delta modulator 3. In FIG. The output terminal of the delta modulator is connected to a reversible counter 5 via an isolation transformer 4, and the output terminal of this counter is further connected to an adaptive high-pass filter 7.
The output of this filter is supplied to the output terminal 9 of the device. Delta modulator 3 and counter 5
is controlled by clock generator 11, and reversible counter 5 advances its count by one on each clock pulse in the direction determined by the logic state of the output from delta modulator 3. The digitized ECG signal occurring at the output terminal 9 can be supplied to an arithmetic unit, for example a microprocessor 13, for further processing.

FIG. 2 shows a detailed circuit diagram of one embodiment of a delta modulator. This modulator connects input terminal 1 to analog
It comprises a first input terminal 15 for receiving an ECG signal and a second input terminal 17 for receiving a reference voltage. 1st
The input terminal 15 is connected to a first amplifier 19 (for example, a gain of 10
) to the first input terminal 20 of the comparator 21
The second input terminal 17 is connected to one electrode of a capacitor 25 via a second amplifier 23 , and the other electrode of this capacitor is connected to a second input terminal 26 of the comparator 21 .

The output terminal of the comparator 21 is the D− of the bistable element 27.
Its C-input terminal is connected to clock generator 11 (FIG. 1). Bistable element 2
The electronic switch 31 is controlled by the output of the output terminal Q of the circuit 7, and this output terminal Q is also connected to the output terminal 33 of the delta modulator. The electronic switch 31 comprises two switching elements 35 and 37, the former capable of connecting the electrode of the capacitor 25 connected to the comparator 21 to a positive current source 39 or a negative current source 41, respectively, and the latter to a positive current source 39 or a negative current source 41, respectively. At the same time, the other electrode of the capacitor 25 can be connected to the negative current source 43 or the positive current source 45, respectively.
However, both switches 35 and 37 are in a neutral open circuit state during the interval between clock pulses.

The operation of this circuit is as follows. Comparator 21
When the instantaneous value of the amplified ECG signal at the first input terminal 20 of the comparator is greater than the voltage at its second input terminal 26, the output of the comparator will be a logical 1 and thus the D-input of the bistable element 27. The terminal also has a logic value of 1. As a result, when the next pulse from clock generator 11 appears at the C-output terminal of bistable element 27, its Q output will also be at a logical 1, thus setting switch 31 to the position shown. Therefore,
Capacitor 25 is connected to current source 39 for a short period of time t determined by clock generator 11, and current I _H is supplied from this to capacitor 25, so that capacitor 25 is charged with a charge amount of I _H t, and its Second input terminal 26 of result capacitor 21
approaches the first input terminal 20. At the same time, the other electrode of the capacitor 25 is connected to the negative current source 43, discharging the amount of charge I' _H t so that the reference voltage is not disturbed by the charge I _H t supplied by the current source 39.

When the voltage at the first input terminal 20 of the comparator 21 is lower than the voltage at the second input terminal 26, a logical 0 is generated at the D- input terminal of the bistable element 27, responsive to the next clock pulse of the clock pulse generator. Since the Q output of the bistable element 27 becomes logic 0 and the switch 31 is set to the other position, the capacitor 25 is connected to the negative current source 41 for a period of time t and carries a charge of I _L ·t. discharge amount. At this time, the positive current source 45 supplies a charge of I' _L ·t to the other electrode of the capacitor 25 for compensation.

As is clear from the above, the voltages at the two input terminals 20 and 26 of the comparator 21 are the same as those of the clock generator 1.
They become equal after multiple periods of 1. And if the ECG signal increases, multiple logical 1s will be output to the output terminal 3.
3, and multiple logical 0s if decreasing
is supplied. Therefore, the value of the ECG signal can be reproduced at any instant from the sequence of logical 1's and 0's occurring at the output terminal.

However, in reality, the above theory was confirmed to be only approximately correct. This is because the two current sources 39 and 41 are not exactly identical and because the input terminal 26 of the comparator 21 has a finite input impedance, a small current I _B leaks from the capacitor 25. Therefore, when capacitor 25 is charged over multiple periods of clock generator 11 and then discharged over the same number of periods, the voltage at second input terminal 26 of comparator 21 will not return to its original value. do not have. Conversely, an input signal that first increases to a predetermined value and then decreases back to its original value will produce a different number of logical 1's and 0's at the output terminal 33. This appears in the digitized signal as an ever increasing or decreasing voltage superimposed on the signal.

This point will be explained below using calculations. Assume that the leakage current to the comparator described above is I _B and that the current sources 39 and 41 are not exactly the same, but that I _H =I+δI (1) _IL =I-δI (2).

In the illustrated position of switch 31, capacitor 25
The current to is equal to I _u = I _H - I _B = I + δI - I _B = I - ΔI (3). Here, I _B −δI=ΔI (4) In the other position of the switch 31, the capacitor 25
The current is equal to I _d =I _L +I _B =I-δI+I _B =I+ΔI (5).

As is clear from (3) and (5), the charging and discharging processes are represented by unequal currents I _u and I _d (respectively smaller and larger than the ideal current source I by ΔI).

If I _u counts the number of periods n _u during switching on and the number n _d of periods I _d switches on during a predetermined number of clock periods (n _u is the number of logic 1s at the output terminal 33, n _d is logic 0). , n=n _u
+n _d ), and the voltage ΔV of the capacitor 25 is constant at ΔV=n _u −n _d・I _d = ( _nu − _nd )・I+(n _u +n _d )・ΔI (6) n _u +n _d =n Therefore, ΔV=(n _{u −nd} )・I+C (7) Here, C=n・ΔI (8) The signal at the first input terminal 20 of the comparator 21 has a time length of n clock periods. Assuming that ΔS increases during a predetermined time interval, the voltage increase ΔV across the capacitor 25 is equal to ΔS, so ΔS=(n _{u −nd} )・I+C (9), and from this, (n _u −n _d )=ΔS−C/I (10).

If the average value of the signal supplied to the input terminal 15 is constant, the average value of ΔS over a long period of time should be zero. However, from the above equation (10), it can be seen that the value n _u -n _d increases or decreases every moment. This means that the pulse train generated at the output terminal 33 represents a signal in which the signals at the input terminal 15 are combined with signals that increase or decrease from time to time. Therefore, the average value of the output value of the reversible counter 5 (FIG. 1) increases continuously. The high-pass filter 7 acts to reduce its average value to a constant value so that a digital signal is available at the output terminal 9 which accurately represents the analog signal applied to the input terminal 1.

FIG. 3 shows an embodiment of the high-pass filter 7. This filter receives the signal S from the reversible counter 5.
(t). This input terminal is connected to the positive input terminal of a first adder 49, the output terminal of this adder is connected to the output terminal 9 of the device, and an attenuator 5 is multiplied by a coefficient α<<1.
Connect to 1. The output terminal of this attenuator is connected to a first positive input terminal of a second adder 53, and the output terminal of this adder is connected to a delay element 55 producing a delay ΔT. The output terminal of this delay element is connected to the first adder 49.
and the second positive input terminal of the second adder 53.

The operation of this circuit is as follows. Instantaneous T+Δ
At T, a digital signal S(T+ΔT) appears at input terminal 47. This signal is subtracted in a first adder 49 by a signal (T) which is the gradual average value at instant T of the change signal S(t). At the same time, the signal S(T+ΔT)−
(T) is multiplied by the coefficient α, and the obtained signal α{S
(T+ΔT)−(T)} is added to (T) by the second adder 53. The signal (T)+α{S(T+ΔT)−(T)} thus obtained is delayed by ΔT in the delay element 55. Therefore, the signal that comes out of the delay element at instant T+ΔT is the signal that arrived at the delay element at instant T, and (T-ΔT)α{S(T)-(T+ΔT)} = (1-α)(T+ΔT)+αS (T) = (T).

This means that the gradual average value at the instant T is the instant T-
This is because it is a combination of the "old" gradual average value at ΔT and the instantaneous value of the signal S(t) at instant T (here, both components need to be multiplied by a weighting factor whose sum is 1).

The progressive mean value of a signal with a mean value of zero is approximately equal to zero, whereas the progressive mean value of a signal that increases linearly with time is equal to the instantaneous value of this signal minus a constant value. Therefore, if the signal S(t) at the input terminal 47 consists of a combination of a varying signal with an average value of zero and a linearly increasing signal, then the signal S(t)-S(t- ΔT) will be equal to a changing signal with a constant average value.

In the above example, the high-pass filter was configured with two adders, one attenuator, and one delay element, but these arithmetic operations to be performed on the signal are performed by an appropriately programmed arithmetic unit, It is clear that it can also be executed by the microprocessor 13, for example.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of an example of the device of the present invention.
2 is a circuit diagram of an embodiment of a delta modulator used in the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of an embodiment of an adaptive high-pass filter used in the circuit of FIG. DESCRIPTION OF SYMBOLS 1... Input terminal, 3... Delta modulator, 4... Isolation transformer, 5... Reversible counter, 7... High pass filter, 9... Output terminal, 11... Clock pulse generator, 13... Microprocessor, 19, 23... Amplifier, 21... Comparator, 25... Charge/discharge capacitor,
27... Bistable element, 31... Switch, 35, 37
...Switch element, 39, 41, 43, 45... Current source, 49... First adder, 51... Attenuator, 53... Second adder, 55... Delay element.

Claims (1)

Claims: 1. An analog signal is sampled during successive time intervals (ΔT) each having a time width corresponding to n clock pulses of a clock pulse generator, and for each time interval, at the beginning of the time interval ( A delta modulator that outputs m (mn) pulses according to the difference between the signal value at T) and the signal value at the end (T+ΔT) is provided, and an analog signal having a constant average value is digitized. In the apparatus, the output terminal of the delta modulator is connected to a correction circuit including a digital high-pass filter, the correction circuit configured to reduce the signal applied thereto by a progressive average value of the signal, and for this purpose. a reversible counter that receives clock pulses and counts the clock pulses in one direction or the other depending on whether an output pulse from the delta modulator is present during the occurrence of the clock pulse; is connected to the correction circuit via the digital filter for supplying the total count present in the counter at the end of each time interval (ΔT) to the digital high-pass filter as a digital input value S(T+ΔT); The high-pass filter gradually subtracts the average value (T) from the digital input value S(T+ΔT) to obtain the difference value {S(T+ΔT).
T)−(T)}, a multiplication means for multiplying the difference value by a constant weighting coefficient α (0<α≪1), and a first addition means forming the weighted difference value α{S(T+
ΔT)−(T)} to the gradual average value (T) and updated progressive average value (T+ΔT)=(1
−α)(T)+αS(T+ΔT), and an accumulation means for accumulating the updated progressive average value until the end of the next interval (ΔT), and the difference value { S(T+ΔT)−
(T)} is arranged to form a digital output value of the digital high-pass filter and represent the digital value of the sampled analog signal. 2. In the device according to claim 1,
An analog signal digitization device, characterized in that the device digitizes an ECG signal derived from a patient.