CA1182923A - Delta modulator with a high-pass digital output filter - Google Patents
Delta modulator with a high-pass digital output filterInfo
- Publication number
- CA1182923A CA1182923A CA000387123A CA387123A CA1182923A CA 1182923 A CA1182923 A CA 1182923A CA 000387123 A CA000387123 A CA 000387123A CA 387123 A CA387123 A CA 387123A CA 1182923 A CA1182923 A CA 1182923A
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- Prior art keywords
- delta
- signal
- value
- mean value
- delta modulator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/02—Delta modulation, i.e. one-bit differential modulation
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Networks Using Active Elements (AREA)
Abstract
ABSTRACT:
A device for digitizing an analog signal whose mean value is constant, comprising a delta modulator which is adapted to sample the signal during successive time intervals, each of which has a duration which corres-ponds to n pulses of a clock pulse generator, and to supply m (m < n) pulses per time interval, m being depen-dent on the difference between the values of the signal at the beginning g and at the and of the interval. The output of the delta modulator is connected to a correction air-cuit which is constructed as a digital high-pass filter in order to remove error signals which are added to the sig-nal due to inaccuracies of the delta modulator.
A device for digitizing an analog signal whose mean value is constant, comprising a delta modulator which is adapted to sample the signal during successive time intervals, each of which has a duration which corres-ponds to n pulses of a clock pulse generator, and to supply m (m < n) pulses per time interval, m being depen-dent on the difference between the values of the signal at the beginning g and at the and of the interval. The output of the delta modulator is connected to a correction air-cuit which is constructed as a digital high-pass filter in order to remove error signals which are added to the sig-nal due to inaccuracies of the delta modulator.
Description
The invention relates to a device for digitizing an analog signal whose mean value is constant, comprising a delta modulator which is adapted to sample the signal during successive time intervals, each of which has a dur-ation corresponding to n pulses of a clock pulse generator,and to supply m ~m ~ n) pulses per time interval, m being dependent on the difference between the values of the signal at the beginning and at the end of the interval.
A device of this kind can be used, for example, for digitizing an ECG signal for ~urther processing. An ECG signal is a more or less periodic signal whose mean value equals zero or a (constant) contact potential occur-ring between the electrodes and the skin of a patient. It has been found that inaccuracies in the delta modulator add error signals to this signal which, of course, disturb the ~urther processing. It is an object of the invention to eliminate these disturbing error signals while maintaining the useful information.
To this end, a device in accordance with the invention is characteri~ed in that -the output o -the delta modulator is connected to a correction circuit which is constructed as a digital high-pass fil-ter.
The invention is based on the recognition o~ the fact that the error signals caused by the delta modulator are of a continuous and slowly decreasing or increasing nature, so that a high-pass filter can be used to separate these error signals from an ECG signal which contains virtually no very low frequency components except for the unimportant contact potential.
A preferred embodiment o~ the device in accordance with the invention is characterized in that the correction circuit is adapted to reduce the signal applied thereto by PHN 9855 2 15.5.2981 the progressive rnean value of the signal.
The invention will be desc:ribed in detail h.ereirl-after ~ith reference to the accompanying daigrammatic dra-wing.
Figure 1 shows a block diagram of an emboclimen-t o-~
a device in aceordance with -the inventi.on.
:Figure 2 shows a eircuit diagrarn of an embodiment of a delta modulator -to be used in the circuit shown in ~igure 1, and Figure 3 shows a~ circui t diagram of an embodiment of an adaptive high-pass filter -to be used in the circuit shown in ~igure 1.
The deviee shown in Figure -I eompri.ses an input -l for supplying an ECG si~nal to a delta modulator 3, ~ria an 15 isolating transformer 4, -the outpu-t of the cZel-ta modulator is connected -to a bidirectional counter 5 ~.hi.ch in :its turn is eonnected to an adap-tive high-pass filter 7, the output signal of which i.s applied to the output 9 of the device.
The clelta modulator 3 and the counter 5 are eontrolled by 20 a eloek generator 11 and the bidiree-tional counter 5 is arranged to increment the eount for eaeh elock pulse in a direetion determined by the logic state of -the output f.rom the delta rnodulator 3. The digitizecl.~CG signal appearing on the QltpUt 9 can be applied to an arithmetic uni-t 13, 25 f`or example, a mic:roproeessor ~or further processing,.
Fi~ure 2 is a more detailecl vie~ of an e~ bodimerlt of the del-ta modula-tor 3. Tlle modulator comprises a firs-t input 15 f`or receivirlg the analog ECG signal from the inpu-t 1 and a second input 17 for receiving a reference voltage.
30 The first input l5 is eonnected to a first input 20 of a corllpa:rator 21 via a first amplifier 19 with a gain of, for example, 10. The second input 17 is connec-ted, via a second amplifier 23, to an electrode of a capacitor 25, the other electrode of which is connec~ed to the second input
A device of this kind can be used, for example, for digitizing an ECG signal for ~urther processing. An ECG signal is a more or less periodic signal whose mean value equals zero or a (constant) contact potential occur-ring between the electrodes and the skin of a patient. It has been found that inaccuracies in the delta modulator add error signals to this signal which, of course, disturb the ~urther processing. It is an object of the invention to eliminate these disturbing error signals while maintaining the useful information.
To this end, a device in accordance with the invention is characteri~ed in that -the output o -the delta modulator is connected to a correction circuit which is constructed as a digital high-pass fil-ter.
The invention is based on the recognition o~ the fact that the error signals caused by the delta modulator are of a continuous and slowly decreasing or increasing nature, so that a high-pass filter can be used to separate these error signals from an ECG signal which contains virtually no very low frequency components except for the unimportant contact potential.
A preferred embodiment o~ the device in accordance with the invention is characterized in that the correction circuit is adapted to reduce the signal applied thereto by PHN 9855 2 15.5.2981 the progressive rnean value of the signal.
The invention will be desc:ribed in detail h.ereirl-after ~ith reference to the accompanying daigrammatic dra-wing.
Figure 1 shows a block diagram of an emboclimen-t o-~
a device in aceordance with -the inventi.on.
:Figure 2 shows a eircuit diagrarn of an embodiment of a delta modulator -to be used in the circuit shown in ~igure 1, and Figure 3 shows a~ circui t diagram of an embodiment of an adaptive high-pass filter -to be used in the circuit shown in ~igure 1.
The deviee shown in Figure -I eompri.ses an input -l for supplying an ECG si~nal to a delta modulator 3, ~ria an 15 isolating transformer 4, -the outpu-t of the cZel-ta modulator is connected -to a bidirectional counter 5 ~.hi.ch in :its turn is eonnected to an adap-tive high-pass filter 7, the output signal of which i.s applied to the output 9 of the device.
The clelta modulator 3 and the counter 5 are eontrolled by 20 a eloek generator 11 and the bidiree-tional counter 5 is arranged to increment the eount for eaeh elock pulse in a direetion determined by the logic state of -the output f.rom the delta rnodulator 3. The digitizecl.~CG signal appearing on the QltpUt 9 can be applied to an arithmetic uni-t 13, 25 f`or example, a mic:roproeessor ~or further processing,.
Fi~ure 2 is a more detailecl vie~ of an e~ bodimerlt of the del-ta modula-tor 3. Tlle modulator comprises a firs-t input 15 f`or receivirlg the analog ECG signal from the inpu-t 1 and a second input 17 for receiving a reference voltage.
30 The first input l5 is eonnected to a first input 20 of a corllpa:rator 21 via a first amplifier 19 with a gain of, for example, 10. The second input 17 is connec-ted, via a second amplifier 23, to an electrode of a capacitor 25, the other electrode of which is connec~ed to the second input
2~ of the comparator 21.
The ou-tput of the comparator 21 is connected to the D-input of a bistable element 27~ the C-input 29 of ~hich is connected to the clock generator 1l shown in ~X~3~3 PHN 9855 3 15.5.1981 :Flgure 1. The outpu-t Q of the bistable elemen-t 27 controls an e:Lectronic switch 31 and is also connected to i;he output 33 of the delta modlllator. The elec-tronic switch 31 comprises two switching uni-ts 35 and 37 9 -the ~ormer being capable of connecting the electrode of -the capacitor 25 which is connected -to the compara-tor 21 to a positive current source 3g or to a negative current source 41 as desired, whilst the second switching -unit at the same time connec-ts the other electrode of the capacitor to a negative current source 43 or a positLve current source L~5~ respecti-vely. However, during the intervals between clock pulses both switches 35 and 37 are in a neutral 9 open circuit state (not shown).
The operation of this circuit is as follows 1~hen 15 the instantaneous value of the amplified ECG signal on the first input 20 of the comparator 21 is greater than the vo~tage on the second input 26 of the comparator, the OUtpllt of the comparator carries a logic 1 and hence also the D_input of the bistable element 27. ~s a result, when the 20 next pulse from the clock generator l1 appears on the C-input of the bistable element 27, the output Qthereof also carries a logic 1, so -that the switch 31 is se-t -to the position shown. Consequently, for a brie~ period of time t which is determined hy the clock geIlera-tor -ll -the capacitor 25 25 is connected -to -the current source 39 wllich s~lpplies a current IH to the capac:Ltor, so tha-t the la-tter .is cllarged by an amoun-t IHt, wi-th -the resul-t tha-t the vo:l.-tage on -the second inpllt 26 of the comparator 21 approaches -that on the firs-t input 20. ~t the same time the other electrode 30 of the capacitor 25 is connected to the negative current source 43, ~hich discharges a charge amoun-t I'IIt in order to preven-t the charge IHt supplied b~ the current source 39 from disturbing the reference voltage.
When the voltage on the input 20 of the compara-tor 35 21 is lower than that on the second input 26, a logic O
appears on the D-input of the bistable element 27, said logic 0 setting the switch 31 to the other position ia the Pl-IN 9855 4 15.5.'1981 outpu-t Q, in reac-tion to the ne~t pulse of` -the clock generatox, so that the capaci-to-r 25 t9 co~lnectecl to the negative currerlt source 41 fo:r a periocl of -time t and i.s discharged by an amount IL.t~ ~or compensa.-tion, the posi-ti-ve cur:rent source 45 applies a charge I'L.-t to t'he other electrode of the capacitor.
It will be clear from the foregoing that -the voltages on the two inputs 20 and 26 of the comparator 21 will be equal after a number of periods of the clock lO generator 11. Any subsequent rise of -the ECG signal means that a number of logic ones are applied to the output 33, and any decrease that a number of` logic zeroes are applie~.
Therefore, the value of the ~CG signal can be reconsl;ructecl at any instant from the series of :Logic ones and ~eroes 5 appearing on the output.
It has been found in practice, ho-rever, that -the above reasoning is onl~ appro~imately correct, because on the one hancl the -two curren-t sources 39 and 4l are no-t exac-tly iden-ti.cal and because on the other hand the input 20 26 of the comparator 21 has a finite input resistance, so that a small curren-t IB leaks from the capacitor 25. Conse-quently, when the capacitor 25 has been charged for a nllmber o:f periods of` the cloclc generat;o:r ll and is sub-sequently d:ischarged again f`or the same nllmbe:r of periods, 25 the vol-tage on the second input 26 o:t' the comp~rator 2l will not have retuxrled to the origi.l-lal val-le Conversely, a s:ignal on the f`lrst lnput 20 whlch t`irst rises from a given value and subsequently decreases -to its orig:Lnal value again, ~rill thus produce mequa.l numbers of zeroes and ones 30 on the OlltpUt 33. ~n the d:igi-t:i~ed signal this becomes mani:~est as a steadily lncreasing ox decreasing voltage superposed on -the signal.
This will be illustrated hereinafter ~rith reference to a calculation. .Assume that the leakage current to the comparato.r as described above equals IB and that the current sources 39 and 41 are not e~actly iden-tical, so that Pl-IN 9(~55 l5.5.l981 ~ ~[ (1) In the position of` the swi-tch 31 sho~rn~ the curren-t to the capacitor 25 equals:
I = IH ~ IB = I ~ ~ I - IB
Therein:
In the other position of the switch 31, the current of the capacitor 25 equals:
I~ = IL * IB = I ~ IB
It appears from (3) and (5) that the charging and dischar-ging process can be described with the unequal current sources Iu and Id which are an amount ~ I smal].er and lar-ger, respectively, than an ideal current source I.
If the num'ber of periods n~l during whic~l Iu is switched on and -the num'ber of periods nl during w}lich Id is ~switched on (nu being the number of ones and nd being ~he number of zeroes on the output 33, and n = nu + nd) is counted each time during a fixed number (n) o~ clock periods, the voltage increase ~ V on the capacitor 25 follows therefrom:
~ ~/ = nu Iu ~ lld Icl = (n~-rld) I ~ (r~ ~rll) . ~ I (~) Because n~ nd = n :is consta tl t:
~ V - (nu - nd) . I + c (7) in which C = n . ~ I (8) If the signal on the first inpllt ~0 of the comparator 21 increases b~ an amo~mt ~ S during a given time interval having a length o:~ n clock periods, the voltage increase ~ ~ on the capaci-tor 25 will be equal to S, so that.' ~ S = (nu ~ nd) . I ~ C (9) It follo~rs there~rom that:
, ~ ~ S - C
~nu ~ nd~ = --I ' ( 10) If the mean value of -the signal appearing on the i.nput 15 is constant, the mean value of ~ S o~er a prolonged period PIIN 9~55 6 !5,5.19~1 of time mus-~ he equal -to 0. ~Iowever, it :t'ollows f`rom (-10) tha-t the ~a1.ue nu ~ nd steadil.y increa.ses or clecreases i.n -time. This means that the pulse series appearing on -the output ~3 represents a signal which is composed of -the signal on the input 15 ancl a ste~dily increasing or decreasing signal~ Therefore, the value on the output of the bidirectional counter 5 (Figure 1) will continuously increase on average. The high-pass filter 7 serves -to reduce this mean value to a constant amount, so that on the l0 output 9 a digital signal appears which is an e~act repre-sentation of the anal.og signal applied to the input 1.
Figure 3 shows an embodiment Or the high-pass filter 7. The filter comprises an inpu-t 47 which recei.ves the signal S(t) from thebidirectional coull-ter 5. This input 15 is connected -to a positive i:nput of a firs-t adder ~9 whoxe OUtp~lt is connected on -the one side to the o~ltpu-t 9 ot` the device and on the other side to an attenua-tor 51 which multiplies by a factor ~1. The output of the attenuator is connected to a ~i.rst posi-tive input of a second adder 20 53, the output of which is conn.ected to a delay element 55 having a delay ~ T. The output of the delay elernent is connected on the one side to a negative inpu-t of the first adder 49 and on the other sicle to a second pos:itive :inpllt of the second adder 53.
The opera-tion of this circu:i-t i.sas ~'ollows. ltt an instarl-t T ~ ~ T, a cligi.tal s:ignal S(T + ~ T) appears on the lnput ll7, This signal is redIlced in tlle first adcler by a signal S(T) ~hich is the progressive mean value at the instant T of the varying signal S(t). In the attenuator 51, 30 the signal S(T ~ ~ T) - S(T) is multipli.ed by ~ and the resultant signal ~ ~S(T ~ ~ T) - S (t) ~ is increased iIl the second adder 53 by S(T). The signal S (T) +
cG f S~T + ~ T) - S(T) } thus formed is delayed by an amo~mt ~ T in tha delay element 55. The signal which leaves the delay element at the instan-t T ~ T7 therefore, is the signal which arrived in the delay el.ement at the instant T and equals:
P:HN 9855 7 l5.5.1981 S(~ VG ~ S(T) - S(T- ~ ~r) } =(1- ~ )S(T- ~ ~r) ~
~ S(T) = S(T) This is because -the progressive mean value at ~he ins-tan-t T
is a combination of the "old" progressive mean value at the i.nstant T ~ ~ T and the ins-tan-taneous value of` the signal S(t) at the lnstant T9 lt being necessary to mul-tiply both components by a weighting factor, -the sum of the weighting factors being equal -to 1.
The progressive mean value of a signal having a lO mean value zero is substantially equal to zero, whilst the progressive mean value of a signal which linearly increases in time is equal to the instan-taneous value of -this signal, minus a cons-tant amount. Therefore, if the signal S(t) on the input 47 is composed of a combina-tion of` a variable 15 signal having the mean value zero and a linearly increasing sigr1al, the signal S(-t) - S(t - ~ T) on -the~utput 9 ~rill be equal -to -the variable signal having a constant mean val~le.
In the described embodiment, the high-pass t'ilter 20 is constructed as a combina-tion of t~o adders, an at-tenua~
tor and a delay element. It 1~ill be clear tha-t the arithme-tical operations to be e~ecuted thereby on the signal can alternatively be e~ecu-ted by a suitably progr.llllmed arithmetic uni.-t, t`or example, thc microp:roces~or 13.
The ou-tput of the comparator 21 is connected to the D-input of a bistable element 27~ the C-input 29 of ~hich is connected to the clock generator 1l shown in ~X~3~3 PHN 9855 3 15.5.1981 :Flgure 1. The outpu-t Q of the bistable elemen-t 27 controls an e:Lectronic switch 31 and is also connected to i;he output 33 of the delta modlllator. The elec-tronic switch 31 comprises two switching uni-ts 35 and 37 9 -the ~ormer being capable of connecting the electrode of -the capacitor 25 which is connected -to the compara-tor 21 to a positive current source 3g or to a negative current source 41 as desired, whilst the second switching -unit at the same time connec-ts the other electrode of the capacitor to a negative current source 43 or a positLve current source L~5~ respecti-vely. However, during the intervals between clock pulses both switches 35 and 37 are in a neutral 9 open circuit state (not shown).
The operation of this circuit is as follows 1~hen 15 the instantaneous value of the amplified ECG signal on the first input 20 of the comparator 21 is greater than the vo~tage on the second input 26 of the comparator, the OUtpllt of the comparator carries a logic 1 and hence also the D_input of the bistable element 27. ~s a result, when the 20 next pulse from the clock generator l1 appears on the C-input of the bistable element 27, the output Qthereof also carries a logic 1, so -that the switch 31 is se-t -to the position shown. Consequently, for a brie~ period of time t which is determined hy the clock geIlera-tor -ll -the capacitor 25 25 is connected -to -the current source 39 wllich s~lpplies a current IH to the capac:Ltor, so tha-t the la-tter .is cllarged by an amoun-t IHt, wi-th -the resul-t tha-t the vo:l.-tage on -the second inpllt 26 of the comparator 21 approaches -that on the firs-t input 20. ~t the same time the other electrode 30 of the capacitor 25 is connected to the negative current source 43, ~hich discharges a charge amoun-t I'IIt in order to preven-t the charge IHt supplied b~ the current source 39 from disturbing the reference voltage.
When the voltage on the input 20 of the compara-tor 35 21 is lower than that on the second input 26, a logic O
appears on the D-input of the bistable element 27, said logic 0 setting the switch 31 to the other position ia the Pl-IN 9855 4 15.5.'1981 outpu-t Q, in reac-tion to the ne~t pulse of` -the clock generatox, so that the capaci-to-r 25 t9 co~lnectecl to the negative currerlt source 41 fo:r a periocl of -time t and i.s discharged by an amount IL.t~ ~or compensa.-tion, the posi-ti-ve cur:rent source 45 applies a charge I'L.-t to t'he other electrode of the capacitor.
It will be clear from the foregoing that -the voltages on the two inputs 20 and 26 of the comparator 21 will be equal after a number of periods of the clock lO generator 11. Any subsequent rise of -the ECG signal means that a number of logic ones are applied to the output 33, and any decrease that a number of` logic zeroes are applie~.
Therefore, the value of the ~CG signal can be reconsl;ructecl at any instant from the series of :Logic ones and ~eroes 5 appearing on the output.
It has been found in practice, ho-rever, that -the above reasoning is onl~ appro~imately correct, because on the one hancl the -two curren-t sources 39 and 4l are no-t exac-tly iden-ti.cal and because on the other hand the input 20 26 of the comparator 21 has a finite input resistance, so that a small curren-t IB leaks from the capacitor 25. Conse-quently, when the capacitor 25 has been charged for a nllmber o:f periods of` the cloclc generat;o:r ll and is sub-sequently d:ischarged again f`or the same nllmbe:r of periods, 25 the vol-tage on the second input 26 o:t' the comp~rator 2l will not have retuxrled to the origi.l-lal val-le Conversely, a s:ignal on the f`lrst lnput 20 whlch t`irst rises from a given value and subsequently decreases -to its orig:Lnal value again, ~rill thus produce mequa.l numbers of zeroes and ones 30 on the OlltpUt 33. ~n the d:igi-t:i~ed signal this becomes mani:~est as a steadily lncreasing ox decreasing voltage superposed on -the signal.
This will be illustrated hereinafter ~rith reference to a calculation. .Assume that the leakage current to the comparato.r as described above equals IB and that the current sources 39 and 41 are not e~actly iden-tical, so that Pl-IN 9(~55 l5.5.l981 ~ ~[ (1) In the position of` the swi-tch 31 sho~rn~ the curren-t to the capacitor 25 equals:
I = IH ~ IB = I ~ ~ I - IB
Therein:
In the other position of the switch 31, the current of the capacitor 25 equals:
I~ = IL * IB = I ~ IB
It appears from (3) and (5) that the charging and dischar-ging process can be described with the unequal current sources Iu and Id which are an amount ~ I smal].er and lar-ger, respectively, than an ideal current source I.
If the num'ber of periods n~l during whic~l Iu is switched on and -the num'ber of periods nl during w}lich Id is ~switched on (nu being the number of ones and nd being ~he number of zeroes on the output 33, and n = nu + nd) is counted each time during a fixed number (n) o~ clock periods, the voltage increase ~ V on the capacitor 25 follows therefrom:
~ ~/ = nu Iu ~ lld Icl = (n~-rld) I ~ (r~ ~rll) . ~ I (~) Because n~ nd = n :is consta tl t:
~ V - (nu - nd) . I + c (7) in which C = n . ~ I (8) If the signal on the first inpllt ~0 of the comparator 21 increases b~ an amo~mt ~ S during a given time interval having a length o:~ n clock periods, the voltage increase ~ ~ on the capaci-tor 25 will be equal to S, so that.' ~ S = (nu ~ nd) . I ~ C (9) It follo~rs there~rom that:
, ~ ~ S - C
~nu ~ nd~ = --I ' ( 10) If the mean value of -the signal appearing on the i.nput 15 is constant, the mean value of ~ S o~er a prolonged period PIIN 9~55 6 !5,5.19~1 of time mus-~ he equal -to 0. ~Iowever, it :t'ollows f`rom (-10) tha-t the ~a1.ue nu ~ nd steadil.y increa.ses or clecreases i.n -time. This means that the pulse series appearing on -the output ~3 represents a signal which is composed of -the signal on the input 15 ancl a ste~dily increasing or decreasing signal~ Therefore, the value on the output of the bidirectional counter 5 (Figure 1) will continuously increase on average. The high-pass filter 7 serves -to reduce this mean value to a constant amount, so that on the l0 output 9 a digital signal appears which is an e~act repre-sentation of the anal.og signal applied to the input 1.
Figure 3 shows an embodiment Or the high-pass filter 7. The filter comprises an inpu-t 47 which recei.ves the signal S(t) from thebidirectional coull-ter 5. This input 15 is connected -to a positive i:nput of a firs-t adder ~9 whoxe OUtp~lt is connected on -the one side to the o~ltpu-t 9 ot` the device and on the other side to an attenua-tor 51 which multiplies by a factor ~1. The output of the attenuator is connected to a ~i.rst posi-tive input of a second adder 20 53, the output of which is conn.ected to a delay element 55 having a delay ~ T. The output of the delay elernent is connected on the one side to a negative inpu-t of the first adder 49 and on the other sicle to a second pos:itive :inpllt of the second adder 53.
The opera-tion of this circu:i-t i.sas ~'ollows. ltt an instarl-t T ~ ~ T, a cligi.tal s:ignal S(T + ~ T) appears on the lnput ll7, This signal is redIlced in tlle first adcler by a signal S(T) ~hich is the progressive mean value at the instant T of the varying signal S(t). In the attenuator 51, 30 the signal S(T ~ ~ T) - S(T) is multipli.ed by ~ and the resultant signal ~ ~S(T ~ ~ T) - S (t) ~ is increased iIl the second adder 53 by S(T). The signal S (T) +
cG f S~T + ~ T) - S(T) } thus formed is delayed by an amo~mt ~ T in tha delay element 55. The signal which leaves the delay element at the instan-t T ~ T7 therefore, is the signal which arrived in the delay el.ement at the instant T and equals:
P:HN 9855 7 l5.5.1981 S(~ VG ~ S(T) - S(T- ~ ~r) } =(1- ~ )S(T- ~ ~r) ~
~ S(T) = S(T) This is because -the progressive mean value at ~he ins-tan-t T
is a combination of the "old" progressive mean value at the i.nstant T ~ ~ T and the ins-tan-taneous value of` the signal S(t) at the lnstant T9 lt being necessary to mul-tiply both components by a weighting factor, -the sum of the weighting factors being equal -to 1.
The progressive mean value of a signal having a lO mean value zero is substantially equal to zero, whilst the progressive mean value of a signal which linearly increases in time is equal to the instan-taneous value of -this signal, minus a cons-tant amount. Therefore, if the signal S(t) on the input 47 is composed of a combina-tion of` a variable 15 signal having the mean value zero and a linearly increasing sigr1al, the signal S(-t) - S(t - ~ T) on -the~utput 9 ~rill be equal -to -the variable signal having a constant mean val~le.
In the described embodiment, the high-pass t'ilter 20 is constructed as a combina-tion of t~o adders, an at-tenua~
tor and a delay element. It 1~ill be clear tha-t the arithme-tical operations to be e~ecuted thereby on the signal can alternatively be e~ecu-ted by a suitably progr.llllmed arithmetic uni.-t, t`or example, thc microp:roces~or 13.
Claims (3)
1. A device for digitizing an analog signal whose mean value is constant, including a delta modulator which is arranged to sample the signal during successive time intervals (.DELTA. T), each of which has a duration correspond-ing to n clock pulses of a clock pulse generator, and to supply m (m ? n) pulses in each said time interval (.DELTA. T), m being dependent on the difference between the values of the signal at the beginning (T) and at the end (T + .DELTA. T) of the interval, characterized in that the output of the delta modulator is connected to a correction circuit which includes a digital high-pass filter, the output of the delta modulator being connected to said correction circuit via a bidirectional counter arranged also to receive the clock pulses and to count said pulses respectively in one direction or the other depend-ing on whether a said output pulse from the delta modulator is or is not correspondingly present during the occurrence of a said clock pulse, the running total count present in the counter being applied as a digital input value S(T + .DELTA. T) to the digital high-pass filter at the end of each said time interval (.DELTA. T).
2. A device as claimed in Claim 1, characterized in that said digital high-pass filter comprises storage means for storing a progressive mean value, first summation means in which said digital input value S (T + .DELTA. T) has subtracted therefrom a progressive mean value S(T) from said storage means so as to form a difference value {S(T + .DELTA. T) - S(T)}, multiplying means arranged to multiply said differences value by a constant weighting factor ? , where 0 < ?? 1, second summation means in which the weighted difference value ? {S(T + .DELTA. T) S(T)} is added to said progressive mean value S(T) to form an updated progressive mean value S(T + .DELTA. T) = (1 - ?) S(T) + ? S(T + .DELTA. T), to be stored in said storage means until the end of the next said interval ( .DELTA. T), said difference value {S(T + .DELTA. T) - S(T)} forming the digital output value of said digital high-pass filter and representing in digital form the sampled analog signal.
3. Electrocardiography apparatus, characterized in that said apparatus includes a device as claimed in Claim 1 arranged to digitize the ECG signal derived from a patient.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL8005549 | 1980-10-08 | ||
| NL8005549A NL8005549A (en) | 1980-10-08 | 1980-10-08 | DEVICE FOR DIGITALIZING AN ANALOGUE SIGNAL. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1182923A true CA1182923A (en) | 1985-02-19 |
Family
ID=19835989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000387123A Expired CA1182923A (en) | 1980-10-08 | 1981-10-01 | Delta modulator with a high-pass digital output filter |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS5795722A (en) |
| CA (1) | CA1182923A (en) |
| DE (1) | DE3139800C2 (en) |
| FR (1) | FR2491700A1 (en) |
| GB (1) | GB2085683B (en) |
| IT (1) | IT1194099B (en) |
| NL (1) | NL8005549A (en) |
| SE (1) | SE451523B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63196696U (en) * | 1987-06-04 | 1988-12-19 | ||
| DE3825884A1 (en) * | 1988-07-29 | 1990-02-01 | Texas Instruments Deutschland | Method for increasing the resolution of an A/D converter |
| US7312785B2 (en) | 2001-10-22 | 2007-12-25 | Apple Inc. | Method and apparatus for accelerated scrolling |
| US7333092B2 (en) | 2002-02-25 | 2008-02-19 | Apple Computer, Inc. | Touch pad for handheld device |
| US8022935B2 (en) | 2006-07-06 | 2011-09-20 | Apple Inc. | Capacitance sensing electrode with integrated I/O mechanism |
| US8274479B2 (en) | 2006-10-11 | 2012-09-25 | Apple Inc. | Gimballed scroll wheel |
| US9654104B2 (en) | 2007-07-17 | 2017-05-16 | Apple Inc. | Resistive force sensor with capacitive discrimination |
| US8683378B2 (en) | 2007-09-04 | 2014-03-25 | Apple Inc. | Scrolling techniques for user interfaces |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52114346A (en) * | 1976-03-23 | 1977-09-26 | Nippon Chemical Ind | Indicating device for ad converter |
-
1980
- 1980-10-08 NL NL8005549A patent/NL8005549A/en not_active Application Discontinuation
-
1981
- 1981-10-01 CA CA000387123A patent/CA1182923A/en not_active Expired
- 1981-10-02 FR FR8118605A patent/FR2491700A1/en active Granted
- 1981-10-05 IT IT24334/81A patent/IT1194099B/en active
- 1981-10-05 SE SE8105853A patent/SE451523B/en not_active IP Right Cessation
- 1981-10-05 GB GB8130002A patent/GB2085683B/en not_active Expired
- 1981-10-07 DE DE3139800A patent/DE3139800C2/en not_active Expired
- 1981-10-08 JP JP56159574A patent/JPS5795722A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2491700B1 (en) | 1985-03-08 |
| DE3139800A1 (en) | 1982-06-24 |
| NL8005549A (en) | 1982-05-03 |
| JPS5795722A (en) | 1982-06-14 |
| SE8105853L (en) | 1982-04-09 |
| JPS6218095B2 (en) | 1987-04-21 |
| IT1194099B (en) | 1988-09-14 |
| IT8124334A0 (en) | 1981-10-05 |
| FR2491700A1 (en) | 1982-04-09 |
| SE451523B (en) | 1987-10-12 |
| DE3139800C2 (en) | 1985-09-12 |
| GB2085683B (en) | 1984-08-08 |
| GB2085683A (en) | 1982-04-28 |
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