RU2106062C1 - Digital automatic signal corrector - Google Patents

Abstract

FIELD: communications. SUBSTANCE: device has non-recursive filter which comprises N+1 multipliers, which outputs are connected to inputs of adder, which output serves as filter output. In addition device has error signal detector, N-stage shift register for error signal which has N+1 terminals, N+1 gain control units, each of which has first AND gate and reverse counter. Terminals of N-stage shift register of error signal are connected to corresponding input of error signal of corresponding gain control unit, which has clock input. In addition device has linear delta-modulator for input signal, which input serves as input of digital automatic signal corrector. In addition device has serial circuit of double integrator and solving unit which output serves as output of digital automatic signal corrector. In addition device has serial circuit of low-pass filter, linear delta-modulator of error signal and delta multiplier by constant factor. In addition device has serial circuit of switch of test signal circuit and delay gate. Non-recursive filter has N-stage shift register which has N+1 terminals, which input serves as input of filter. Each of N+1 multipliers is based on XOR gate, which one input is connected to corresponding terminal of N-stage shift register and another terminal is connected to output of corresponding introduced flip-flop. Output of XOR gate serves as output of multiplier. In addition each gain control unit has second and third AND gates and delta-complete adder, which output is connected to control input of reverse counter, which counting input is connected to output of third AND gate. Outputs of first and second AND gates are connected to first and second inputs of delta-complete adder. Outputs of reverse counter serve as overflow and reset outputs of gain control unit and are connected to inputs of corresponding flip- flop which output is connected to first input of second AND gate of corresponding gain control unit. Second inputs of first, second and third AND gates serve as test signal inputs. First input of first AND gate serves as input for error signal, first input of third AND gate serves as input of clock signal in each gain control unit. Output of linear delta-modulator of input signal is connected to input of non- recursive filter which output is connected to input of double integrator. Input and output of solving unit are connected to first and second inputs of error signal detector, which output is connected to input of low-pass filter. Output of solving unit is connected to input of switch of test signal circuit. Output of delay gate is connected to inputs of test signal of N+1 gain control units which error signal inputs are connected to corresponding terminals of N- stage error signal shift register, which clock signal input is connected to inputs of clock signal of N+1 gain control units, clock inputs of linear delta-modulator of input signal, of linear delta- modulator of error signal, non-recursive filter. It also serves as first clock input of digital automatic signal corrector, which second clock input is clock input of solving unit. EFFECT: tuning by test signal before delta-modulated input signal data transmission, simplified design. 2 dwg

Description

 The invention relates to telecommunications and can be used in digital data transmission systems.

 Known automatic signal correction (ACS) with pre-setting for the test signal transmitted over the communication channel before the start of data transfer. Such ACS are capable of tuning in conditions of large initial intersymbol distortions and with a significant level of noise in the channel.

 Currently, ACS is almost exclusively implemented on the basis of digital signal processing, in particular, using digital non-recursive filters (NRF), which provide better performance compared to analog ACS. Known examples of digital ACS in the form of LSI. However, the use in the ACS of the highest-speed digital NRFs with parallel processing is difficult and expensive due to the need to use a large number of complex multi-bit multipliers in the NRF taps. Simplification of the digital implementation of the ACS is possible by eliminating complex multi-bit multipliers using the technique of delta-modulated signals, using the well-known programmable NRF with a binary signal at its input and with "delta-modulated" tap-off coefficients of the NRF, in particular, with binary coefficients (A book: R. Steele Principles of Delta Modulation, 1979).

 The automatic signal corrector described in the article by Becker, Holtzmann, and Lucky, “Automatic Correction Device for Communication Systems,” Proceedings of the Institute of Electrical and Electronics Engineers, 1965, v. 53, No. 1, p. 110 112, with presetting according to a special test signal representing a sequence of rarely repeated short pulses containing NRF, made on N + 1 multipliers, the outputs of which are connected to the inputs of the adder, the output of which is the output of the NRF, error signal isolator, N cascade shift register ( CWG) of the error signal, made with N + 1 taps, N + 1 gain control units (BECS), each containing the first element And and a counter counter (PC), while the taps of the N-cascade CWG signal osh bki each connected to an input error signal corresponding Buqu having a clock input.

 The problem to which the invention is directed is the implementation of ACS with pre-tuning according to a test signal made on the basis of the NRF, which practically removes the restrictions on its creation in the form of a specialized LSI, due to the use of the delta-modulated signal technique.

 The problem is solved in that in a digital ACS containing NRF made on N + 1 multipliers, the outputs of which are connected to the inputs of the adder, the output of which is the output of the NRF, an error signal isolator, an N-frame RGS error signal made with N + 1 taps , N + 1 BUKU, each containing the first element And And RS, while the taps N of the cascaded CWG error signal are connected each to the input of the error signal of the corresponding BUKU, having a clock signal input, a linear delta modulator (LDM) of the input signal, the input of which is is the digital ACS input, a double integrator and a decision block (RB) connected in series, the output of which is a digital ACS output, a low-pass filter (LPF), an error signal LDM and a constant coefficient delta multiplier connected in series, a test signal circuit breaker connected in series, and a delay register, and in the NRF introduced N-cascade RGS made with N + 1 taps, the input of which is the input of the NRF, each N + 1 multiplier is made on the element EXCLUSIVE OR, one input of which is connected to the corresponding tap of the N-cascade CWG, and the other input with the output of the corresponding trigger input, and the output is the output of the multiplier, while the second and third elements And and the delta-total adder, the output of which is connected to the control input of the PC, are input to the counting input which the output of the third AND element is connected, the outputs of the first and second AND elements are connected to the first and second inputs of the delta of the total adder, the PC outputs are the outputs of the overflow and zeroing signals of the BUKU and are connected to the inputs respectively trigger, the output of which is connected to the first input of the second element AND of the corresponding BUKU, the second inputs of the first, second and third elements AND are the input of the test signal, the first input of the first element AND the input of the error signal, the first input of the third element AND the input of the clock signal in each BUKU, wherein the LDM output of the input signal is connected to the NRF input, the output of which is connected to the input of the double integrator, the RB input and output are connected to the first and second inputs of the error signal isolator, the output of which is connected to the input LF, the RB output is connected to the input of the test signal circuit breaker, the delay register output is connected to the T + 1 BUKU test signal inputs, the error signal inputs of which are connected to the corresponding taps of the N-cascade RGS error signal, the clock signal of which is connected to the N signal inputs + 1 BUKU, the clock inputs of the LDM of the input signal, the LDM of the error signal, NRF is the first clock input of the digital ACS, the second clock input of which is the RB input.

 In FIG. 1 shows a block diagram of a digital ACS; in FIG. 2 is a structural diagram of a BUKU.

The digital ACS of FIG. 1 contains NRF 1, made on an N-cascade RGS2 with N + 1 taps and delay elements 2 ₁ 2 _N , N + 1 multipliers on the elements EXCLUSIVE OR 3 ₁ 3 _{N + 1} and triggers 4 ₁ 4 _{N + 1} , as well as the adder 5, RB6, error signal isolator 7, N cascaded RGS8 error signal with N + 1 taps and delay elements 8 ₁ 8 _N , N + 1 BUKU 9 ₁ 9 _{N + 1} , LDM 10 of the input signal, double integrator 11, low-pass filter 12 , LDM 13 of the error signal, delta multiplier 14 by a constant coefficient, delay register 15, switch 16 of the test signal circuit.

 BUKU 9 in FIG. 2 contains the first, second and third elements And 17, 18 and 19, the delta-complete adder 20 and the PC 21.

 Digital AKC works as follows.

It is characterized by two modes of operation: the setup mode of the ACS by the test signal and the data transfer mode. In the ACS tuning mode, a test signal is transmitted over the communication channel, which represents a sequence of rare short single pulses. The test signal, the sequence of clock pulses with a frequency of F ₁ and F ₂ are respectively received at the information input of the LDM 10 of the input signal, at the input of the clock frequency F ₁ and at the input of the clock frequency F _{2 of the} device.

From the output of the LDM 10 of the input signal, the delta-modulated input signal is fed to the first input of the PC 2 from the taps 2 _{1-N + 1 of} which the signals are fed to the first inputs of the exclusive OR 3 _{1-N + 1} elements, to the second inputs of which the signals from triggers 4 _{1-N + 1} , the binary signals multiplied by the XOR elements are summed by the adder 5 and integrated by the double integrator 11. The corrected signal from the output of the double integrator 11 is fed to RB 6, the output of which is the output of the device, and the error signal isolator 7.

 RB 6 is a simple threshold device that converts incoming signals from a dual integrator 11 with a changing level into pulses at its output fixed in level and duration.

At the same time, a threshold is set in RB 6 equal to 1/2 of the nominal value of the received signal at its output. In the isolator of the error signal 7 at the moments determined by the strobe signals of frequency F ₂ , the signals arriving at its first and second inputs, respectively, from the output of the double integrator 11 and the output of the RB 6, are subtracted. The discrete error sequence formed at the output of the isolator of the error signal 7 is smoothed by the low-pass filter 12, the output of which the smoothed error signal is supplied to the LDM 13 error signal, the output of which the delta-modulated error signal is fed to the input of the delta multiplier 14, in which multiplication by constant th coefficient Δ
The delta modulated binary error signal from the output of the delta multiplier 14 is supplied from the taps of the CSG 8 _{1-N + 1} to the inputs “b” of the BUKU 9 _{1-N + 1} , which update the NRF coefficients by changing the state of the triggers 4 _{1-N + 1} .

( t - период следования посылок двоичного дельта-модулированного сигнала), который также подается на ЛДМ 10 входного сигнала, на ЛДМ 13 сигнала ошибки и на второй вход РГС 8. Между частотами F₁, F₂ и F₃, как правило, должно выдерживаться следующее соотношение:
F₁≥(7^oC8)•F₂≥F₃.The inputs "in" Buqu January _{9-N + 1} receives a test signal at a frequency F _{March 1} / T _p (T _p repetition period of the test signal). The inputs "a" BUKU 9 _{1-N + 1} receives a clock signal with a frequency

(t is the repetition period of the binary delta-modulated signal packages), which is also fed to the LDM 10 of the input signal, to the LDM 13 of the error signal and to the second input of the CWG 8. Between frequencies F ₁ , F ₂ and F ₃ , as a rule, must be maintained the following ratio:
F ₁ ≥ (7 ^o C8) • F ₂ ≥F ₃ .

 BUKU 9 works as follows.

With the arrival of the test signal pulse delayed by the delay register 16 to fill the CWG 8 to the input "b" of the BUKU 9 _i connected to the first inputs of the first, second and third elements And 17, 18 and 19, at the outputs of the first and second elements And 17 and 18, connected respectively to the first and second inputs of the delta-total adder 20, one of the binary states occurs depending on the binary signals currently received at the second inputs of the first and second elements And 17 and 18, respectively, from the delta multiplier 14 by a constant coefficient and ment of the updated memory of the coefficient of tap-trigger 4 _i . The result of summing these signals from the output of the delta-total adder 220 is fed to the control input of the PC 21, the counting input of which receives the test signal sampled by the clock signal of the frequency F ₁ from the output of the third element And 19. Depending on the control signal ("1" or "0 ") the contents of the PC 21 increases or decreases by one. At the outputs of the PC 21 with a reset circuit to the average value of its scale according to the signals of its overflow and zeroing when it overflows or when zeroing, a signal appears that goes to the corresponding input of trigger 4 _i and changes its state. The changed state of trigger 4 _i is supplied to the second input of AND 18 and to the second input of the binary multiplier exclusive OR 3.

To adjust the corrector requires repeated repetition of the above procedure. To enter the data transfer mode after setting it, the test signal circuit is broken by switch 16. In the data transfer mode, only the path is functioning, including the LDM 10 of the input signal NRF 1, the double integrator 11 and RB 6. At the same time, triggers 4 _{1-N + 1} remain unchanged values.

где
C $\genfrac{}{}{0ex}{}{\text{нов}}{\text{i}}$ и C $\genfrac{}{}{0ex}{}{\text{стар}}{\text{i}}$ новое и старое значение коэффициента i-го отвода НРФ 1, определяемое состояние i-го триггера 4,

усредненное значение умноженной на постоянный коэффициент Δ ≪ 1 дельта-модулированной ошибки ε_дм.
При этом

двоичные значения ∈ {1,0}.
Используемые в цифровом АКС дельта-полные сумматоры 20 и дельта-перемножитель 14 на постоянный коэффициент представляют относительно простые элементы двоичное логики. В частности, схема дельта-полного сумматора 20 состоит из полного двоичного сумматора и D-триггера. Функциональные и электрические схемы и сведения об основных особенностях этих элементов содержатся, в частности, в статье Коувераса "Операции с дельта-модулированными сигналами" в журнале The Radio and Electronic Engineer 48, N 9, 1978.The proposed digital ACS implements an interactive algorithm

Where
C $\genfrac{}{}{0ex}{}{\text{new}}{\text{i}}$ and C $\genfrac{}{}{0ex}{}{\text{is old}}{\text{i}}$ new and old value of the coefficient of the i-th retraction of the NRF 1, the determined state of the i-th trigger 4,

the averaged value multiplied by a constant coefficient Δ ≪ 1 delta-modulated error ε _dm .
Wherein

binary values ∈ {1,0}.
The delta-complete adders 20 and delta-multiplier 14 used by the constant factor, used in the digital ACS, represent relatively simple binary logic elements. In particular, the delta-total adder circuitry 20 consists of a full binary adder and a D-flip-flop. Functional and electrical circuits and information about the main features of these elements are contained, in particular, in Coweras's article, "Operations with Delta-Modulated Signals," in The Radio and Electronic Engineer 48, No. 9, 1978.

 Thus, the elimination of the analog delay line from the ACN structure and its replacement with the conventional binary shift register, as well as the replacement of multi-resistive attenuator circuits in a non-recursive filter (and when digitally replacing a large number of complex multi-bit multipliers) with the simplest multipliers, the elements EXCLUSIVE OR the task and practically remove the restrictions on the implementation of ACS using modern technology in the form of a specialized LSI.

Claims (1)

 Digital automatic signal corrector containing a non-recursive filter made on N + 1 multipliers, the outputs of which are connected to the inputs of the adder, the output of which is the output of a non-recursive filter, an error signal isolator, an N-cascade error signal shift register made with N + 1 taps, N + 1 gain control blocks, each containing the first AND element and a reverse counter, while the taps of the N-cascade error signal shift register are each connected to the error signal input of the corresponding block gain control having a clock signal input, characterized in that a linear input signal delta modulator is introduced into it, the input of which is an input of a digital automatic signal corrector, a double integrator is connected in series and a decision block whose output is an output of a digital automatic signal corrector connected by a low-pass filter, a linear delta modulator of the error signal and a delta multiplier by a constant coefficient, connected in series a test signal circuit switch and a delay register, and an N-cascade shift register made with N + 1 taps, the input of which is an input of a non-recursive filter, each N + 1 multiplier is made on the EXCLUSIVE OR element, one input of which is connected to a non-recursive filter the corresponding tap of the N-cascade shift register, and the other input with the output of the corresponding trigger entered, and the output is the output of the multiplier, while the second and third elements are introduced into each gain control unit nts And and the delta are the total adder, the output of which is connected to the control input of the reversing counter, the output of the third element And is connected to the counting input, the outputs of the first and second elements And are connected to the first and second inputs of the delta-total adder, the outputs of the reversing counter are signal outputs overflow and zeroing the gain control unit and are connected to the inputs of the corresponding trigger, the output of which is connected to the first input of the second element AND of the corresponding control unit of the coefficient gain factor, the second inputs of the first, second and third elements AND are the input of the test signal, the first input of the first element AND the input of the error signal, the first input of the third element AND the input of the clock signal in each gain control unit, while the output of the linear delta modulator of the input signal connected to the input of a non-recursive filter, the output of which is connected to the input of the double integrator, the input and output of the decision block are connected to the first and second inputs of the error signal isolator, the output of which is connected low-pass filter input, the output of the deciding unit is connected to the input of the test signal circuit breaker, the output of the delay register is connected to the inputs of the test signal N + 1 gain control units, the input of the error signals of which are connected to the corresponding taps of the N-cascade error signal shift register, the clock input the signal of which is connected to the inputs of the clock signal N + 1 of the gain control units, the clock inputs of the linear delta modulator of the input signal and the delta modulator of the error signal and a non-recursive filter, and is the first clock input of the digital automatic signal corrector, the second clock input of which is the clock input of the decision block.

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