JP3463316B2 - Auto offset cancel circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an auto offset cancel circuit having an offset cancel mode and an operational amplifier operation mode, and in particular, in the offset cancel mode, charges are stored in the capacitor in consideration of the effect of a parasitic capacitor in the operational amplifier operation mode. The present invention relates to an automatic offset cancel circuit.

[0002]

2. Description of the Related Art As a conventional auto offset cancel circuit, there is, for example, a circuit configuration as shown in FIG. The configuration and operation of the conventional auto offset cancel circuit will be described below with reference to FIGS.

First, the circuit configuration will be described with reference to FIG. This auto offset cancel circuit is composed of MOS switches 401 to 405, an operational amplifier 406, and a capacitor 409. In the operational amplifier 406, an input offset voltage (usually about several tens of mV) is generated due to the process. Here, the operational amplifier 406 is an actual operational amplifier, and the operational amplifier 4
06 is an ideal operational amplifier 407 and an offset voltage source 40
8 and the parasitic capacitor 410 is connected to the MOS switch 405.

Next, the operation will be described. However, in the following description, the MOS switches 402, 403,
405 is collectively referred to as φ1, and the MOS switch 401,
404 may be collectively referred to as φ2. The effect of the parasitic capacitor 410 will be ignored. The MOS switches 401 to 405 shown in FIG. 1 are turned ON / OFF at the timing shown in FIG. The operation of the conventional auto offset cancel circuit is roughly divided into (1) offset cancel mode (φ1: ON, φ
2: OFF), and (2) Operational amplifier operation mode (φ1: OFF, φ2: O
N). The details will be described below.

(1) Offset Cancel Mode First, the offset cancel mode (φ1: ON, φ
2: OFF) will be described with reference to FIG. When the MOS switches 401 to 405 are φ1: ON and φ2: OFF, the equivalent circuit shown in FIG. 6 is established. In this circuit, the imaginary short-circuit operation of the operational amplifier 406 operates so that the potentials of the + (plus) input terminal and the- (minus) input terminal of the ideal operational amplifier 407 become equal. As a result, the voltage of the offset voltage source 408 is applied to the capacitor 409, and the capacitor 409 holds the offset voltage V _OS .

The imaginary short-circuiting operation (virtual grounding) means a characteristic that the potential of the input terminal becomes 0 volt, which is equal to the ground potential of the circuit, in the amplifying operation of the operational amplifier. Further, describing in detail, in fact, not be completely equal to the ground potential (0 volt), a very small voltage (V _i) has occurred. The value of this voltage (V _i ) is represented by V _i = V _out / A ₀ , where V _{out is the} output voltage A _{0 and is} the amplification factor of the operational amplifier. Where A ₀ = 10,000 to 10
Since V _out is about 1 to 10 volts and V _{i is} 1 millivolt or less. Therefore, when analyzing the circuit operation, it can be considered that V _i ≈0.

(2) Operational Amplifier Operation Mode Next, operational amplifier operation mode (φ1: OFF, φ2: O
N) will be described with reference to FIG. MOS switch 4
When 01 to 405 are φ1: OFF and φ2: ON, the equivalent circuit shown in FIG. 7 is established. In this circuit, the offset voltage V _OS held in the capacitor 409 is connected so as to cancel the voltage of the offset voltage source 408. As a result, the operational amplifier 406 is
While the capacitor 409 holds the offset voltage V _OS , it operates as if there is no input offset voltage.

At the operation timing shown in FIG. 5, there is a section in which both φ1 and φ2 are in the OFF state, but this is to ensure the transfer of the charge accumulated in the capacitor 409. That is, by repeating these two operation modes, the input offset voltage of the operational amplifier 406 can be reduced in the operational amplifier operation mode.

[0009]

However, in the conventional auto offset cancel circuit as described above, in the operational amplifier operation mode, the charge accumulated in the capacitor is the parasitic capacitor of the MOS switch (the substrate-drain of the MOS switch). Intercapacitance, the charge is not accumulated when the MOS switch is turned on), so the capacitance value of the capacitor must be increased to reduce this effect.
For example, when the above circuit is formed on an integrated circuit (IC), there is a problem that the chip area is increased by the capacitor or the capacitor has to be attached externally, resulting in an increase in the cost of the circuit.

Further, when the above-mentioned conventional auto offset cancel circuit is used for an integrator, for example, even if the input is 0, the output continues to change (increase or decrease) due to the voltage difference due to the error. There was also a problem.

The present invention has been made in view of the above, and has a circuit configuration for accumulating electric charge in the capacitor in anticipation of the effect of the parasitic capacitor in the operational amplifier operation mode in the offset cancel mode, and externally attaching the capacitor. It aims to reduce the cost of the circuit by eliminating it and reducing the chip area.

[0012]

[0013]

SUMMARY OF THE INVENTION The present invention has the above objects.
In order to achieve this, in an auto offset cancel circuit composed of a MOS switch and a capacitor connected to an operational amplifier or a comparator, in the (-) input terminal of the operational amplifier or the comparator, the first, second, and third MOS switches are connected. A first electrode is connected, a first resistor is connected between the second electrode of the third MOS switch and the output terminal of the operational amplifier or comparator , and the second electrode of the second MOS switch and the reference potential are connected. And a second resistor connected between the input terminal and the + (plus) input terminal of the operational amplifier and the reference potential.
Connect the OS switch to the + (plus) of the operational amplifier.
A fourth MO is connected between the input terminal and the first electrode of the capacitor and between the second electrode of the capacitor and the reference potential.
S switch is connected, the second electrode of the capacitor is connected to the output terminal of the operational amplifier or comparator,
The second electrode of the first MOS switch is input, the output terminal of the operational amplifier or the comparator is used as output, and the first and fourth MOS switches are turned ON / OFF at the same time.
The 3rd, 5th and 6th MOS switches are simultaneously turned on / of
The present invention provides an auto offset cancel circuit that performs F.

The capacitance value of the parasitic capacitor between the first electrode and the second electrode when the fifth MOS switch is open is ΔC, the capacitance value of the capacitor is C, and the first resistance is the resistance value as R _1, if the resistance value of the second resistor and the _{R 2, R 1 / R 2} = the first such that the [Delta] C / C, setting the resistance value of the second resistor It is a thing.

[0015]

The automatic offset cancel circuit according to the present invention accumulates charges in the capacitor in anticipation of the effect of the parasitic capacitor in the operational amplifier operation mode in the offset cancel mode.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An automatic offset cancel circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of the automatic offset cancel circuit according to this embodiment. In the figure, MOS switches 101-
106, an operational amplifier 107 (which is composed of an ideal operational amplifier 108 and an offset voltage source 109 as in the conventional example), a resistor (R ₁ ) 110, and a resistor (R ₂ ) 111.
And a capacitor 112. Also, M
A parasitic capacitor 113 is connected to the OS switch 105.

Next, the operation will be described. It is assumed that the MOS switches 101 to 106 shown in FIG. 1 are turned on and off at the timing shown in FIG. Further, the MOS switches 102, 103, 105 and 106 may be collectively referred to as φ1, and the MOS switches 101 and 104 may be collectively referred to as φ2. The operation of this embodiment is similar to the above-mentioned conventional example: (1) Offset cancel mode (φ1: ON, φ
2: OFF), and (2) Operational amplifier operation mode (φ1: OFF, φ2: O
N).

(1) Offset Cancel Mode First, the offset cancel mode (φ1: ON, φ
2: OFF) will be described with reference to FIG. When the MOS switches 101 to 106 are φ1: ON and φ2: OFF, the equivalent circuit shown in FIG. 2 is established. In this circuit, the imaginary short-circuiting operation of the operational amplifier 107 causes the + (plus) input terminal of the ideal operational amplifier and the −
It operates so that the potentials of the (minus) input terminals become equal, and the potential at point A in the figure is the offset voltage source 109.
Becomes the same as the voltage V _OS .

Therefore, the current I flowing through the resistor (R ₂ ) 111 is expressed as I = V _OS / R ₂ ... (1).

Since the input impedance of the operational amplifier 107 is very large, the current flowing through the resistor (R ₁ ) 110 is also I (= V _OS / R ₂ ), and the voltage V _R1 across the resistor (R ₂ ) is V _R1 = I × expressed as _{R 1 = V OS R 1 /} R 2 ···· (2).

That is, the output voltage V of the operational amplifier 107
_OUT becomes V _OUT = V _OS + V _OS R ₁ / R ₂ ... (3), and when the capacitance value of the capacitor 112 is _C , QC = V _OUT × C ...・ The charge of (4) is accumulated.

(2) Operational amplifier operation mode Next, operational amplifier operation mode (φ1: OFF, φ2: O
N) will be described with reference to FIG. MOS switch 1
When 01 to 105 are φ1: OFF and φ2: ON, the equivalent circuit shown in FIG. 7 is established. In this circuit, the capacitor 112 is connected so as to cancel the offset voltage source 109, but the MOS switch 105 is turned on.
By performing FF, the parasitic capacitor 113 is charged. In this case, the charge Q _X accumulated in the capacitor 112 and the parasitic capacitor 113 is Q _X = V _X (C + ΔC) ... (where C is the capacitance value of the capacitor 112 and ΔC is the capacitance value of the parasitic capacitor 113). 5) can be expressed as

According to the law of constant amount of charge, the amount of charge | Q _C | stored in the capacitor 112 in the offset cancel mode, the amount of charge | Q _X | stored in the capacitor 112 in the operational amplifier operation mode and the parasitic capacitor 113. Are equal. Also, the ideal operational amplifier 10
8 - (minus) because the potential of the input terminal is _{0, -V X = V OS ···· (} 6) That is, it may if the _{Q C = -Q X ···· (7} ) Therefore, the above formula (3), formula (4), formula (5)
Therefore, the relationship of the following expression 1 [expression (8)] and expression 2 [expression (9)] is established.

[0024]

[Equation 1]

[0025]

[Equation 2]

Therefore, if the relationship of R ₁ / R ₂ = ΔC / C ... (10) is established, then −V _X = V _OS ... (11) To satisfy the relationship,
By setting the values of the resistor (R ₁ ) 110 and the resistor (R ₂ ) 111, it is possible to eliminate the influence of the parasitic capacitor 113.

Therefore, it is possible to operate the operational amplifier 107 with the input offset voltage reduced in the operational amplifier operation mode without increasing the capacitance value of the capacitor 112.

Further, when the auto offset cancel circuit according to the above embodiment is used for the integrator, the offset voltage is reliably cancelled, so that an error does not occur in the integrated value and accurate calculation processing is possible. Become.

[0029]

As described above, according to the auto offset cancel circuit according to the present invention, in the offset cancel mode, the transfer of charges to the parasitic capacitor generated in the operational amplifier operation mode is expected, and the offset cancel capacitor is used. Since the configuration is such that charges are accumulated, it is not necessary to increase the offset canceling capacitor in order to reduce the input offset voltage of the operational amplifier or the comparator, and therefore the capacitor can be built in the integrated circuit and the chip area can be reduced. Therefore, the cost of the circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an auto offset cancel circuit according to the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of the automatic offset cancel circuit shown in FIG. 1 in an offset cancel mode.

3 is a circuit diagram showing an equivalent circuit of the auto offset cancel circuit shown in FIG. 1 in an operational amplifier operation mode.

FIG. 4 is a circuit diagram showing a configuration of a conventional auto offset cancel circuit.

5 is a timing chart showing the operation timing of the MOS switch shown in FIG.

6 is a circuit diagram showing an equivalent circuit of the automatic offset cancel circuit shown in FIG. 4 in an offset cancel mode.

FIG. 7 is a circuit diagram showing an equivalent circuit of the auto offset cancel circuit shown in FIG. 4 in an operational amplifier operation mode.

[Explanation of symbols]

101-106 MOS switch 107 operational amplifier 108 ideal operational amplifier 109 offset voltage source 110 resistance (R ₁ ) 111 resistance (R ₂ ) 112 capacitor 113 parasitic capacitor

Claims (2)

(57) [Claims] 1. An auto offset cancel circuit composed of a MOS switch and a capacitor connected to an operational amplifier or a comparator, wherein an- (minus) input terminal of the operational amplifier or the comparator has a first (1st), a second (2nd) and a third (3) th MOS switch. Connect the first electrode,
The second electrode of the third MOS switch and the operational amplifier
Alternatively, a first resistor is connected between the output terminal of the comparator and a second resistor between the second electrode of the second MOS switch and the reference potential, and the operational amplifier or
Connects a fifth MOS switch between the + (plus) input terminal of the comparator and the reference potential, connects the + (plus) input terminal of the operational amplifier or the comparator and the first electrode of the capacitor, A fourth MOS switch is connected between the second electrode of the capacitor and the reference potential, and the second electrode of the capacitor and the sixth MOS switch are connected.
Of the sixth MOS switch is connected to the first electrode of
The two electrodes are connected to the output terminal of the operational amplifier or the comparator, and the second electrode of the first MOS switch is input,
The output terminal of the operational amplifier or the comparator is used as an output, and the first and fourth MOS switches are simultaneously turned on / off.
F, and an automatic offset cancel circuit characterized in that the second, third, fifth and sixth MOS switches are turned ON / OFF at the same time. 2. The capacitance value of the parasitic capacitor between the first electrode and the second electrode when the fifth MOS switch is open is ΔC, the capacitance value of the capacitor is C, and the first resistance is When the resistance value of R1 is R1 and the resistance value of the second resistor is R2, the resistance values of the first and second resistors are set so that R1 / R2 = ΔC / C. The automatic offset cancel circuit according to claim 1 .