JP5861909B2 - Switched capacitor integrator - Google Patents

Description

  The present invention relates to a switched capacitor integrator used for negative feedback control and the like.

  Conventionally, a method of performing negative feedback control using an integrator is known for circuit stabilization and the like. Particularly in recent years, an integrator using a switched capacitor circuit as described in Patent Document 1 has been widely adopted. An integrator using this switched capacitor circuit has an optimum circuit configuration for an integrated circuit, that is, an IC because it does not require a high-precision resistor.

  A circuit diagram of a general switched capacitor integrator described in Patent Document 1 is shown in FIG. Here, by alternately turning on and off the first and second switches 12 and 14, the charge is transferred from the input terminal 16 to the second capacitor 22 via the first capacitor 18. This charge movement, that is, current is expressed by [Equation 1]. Here, fsw is a clock frequency for driving the first and second switches 12 and 14, C1 is a capacitance value of the first capacitor 18, Vin is an input voltage applied to the input terminal 16, and Vy is a differential amplifier 24. The voltage of the inverting input terminal 26 is shown.

  During normal operation, Vy is equal to the constant voltage Vref set at the non-inverting input terminal of the differential amplifier 24, so the current is given by [Equation 2].

  The current expressed by [Expression 2] is equal to the current flowing into the second capacitor 22 expressed by [Expression 3].

  By solving [Equation 2] and [Equation 3] simultaneously, Equation [Equation 4] representing the characteristics of the integrator shown in FIG. 5 is obtained. Here, C2 represents the capacitance value of the second capacitor 22, and Vout represents the output voltage appearing at the output terminal 20 of the differential amplifier 24. As can be seen from this equation, the output voltage Vout is obtained by multiplying a value obtained by integrating the input voltage Vin with respect to the reference voltage Vref with a certain coefficient. Here, an accurate integral value cannot be obtained unless the coefficient portion composed of C1, C2, and fsw is a constant. That is, in the operating state of the integrator, this coefficient portion is required to be a constant value.

  In the operating state of the integrator, the voltage applied to the first capacitor 18 is Vin when the first switch 12 is on and the second switch 14 is off, and the first switch 12 is off and the second second switch 14 is off. When turned on, it becomes Vref. On the other hand, the voltage applied to the second capacitor 22 is represented by (Vout−Vref). Thus, since the voltages applied to the first and second capacitors 18 and 22 are different and change with time, in order for the coefficient part of [Equation 4] to be a constant value, The second capacitors 18 and 22 are required to have no voltage dependency. So far, it has been proposed to use a PIP capacity (Poly-Insulator-Poly capacity) or an MIM capacity (Metal-Insulator-Metal capacity) in which an insulating film is sandwiched between polysilicon and metal electrodes.

  However, since the capacitance value per unit area is not sufficient in the PIP capacitor and the MIM capacitor, the area occupied by the first and second capacitors 18 and 22 is increased, which is an obstacle to downsizing of the integration circuit. For this reason, it is conceivable to employ a MOS capacitor having a gate oxide film, which is a very thin film, as an insulating film, assuming that the capacitance value per unit area is larger than that of the PIP capacitor or MIM capacitor. The MOS capacitor is a capacitor element having a MOS structure formed by using a manufacturing process of a MOS (Metal Oxide Semiconductor) transistor which is a kind of field effect transistor (FET). However, the MOS capacitor has a large voltage dependency as shown in FIG. 6 because the charge state of the semiconductor layer, which is an electrode on one side, varies depending on the applied voltage, and as shown in FIG. There was a problem in using the first and second capacitors 18 and 22 of the integrating circuit. In FIG. 6, the horizontal axis represents the gate-source voltage (Vgs: equivalent to the applied voltage with respect to the capacitance) in the MOS transistor, and the vertical axis represents the normalized capacitance value of the MOS capacitance.

  Note that Patent Document 2 and Patent Document 3 disclose means for greatly reducing the voltage dependency of the MOS capacitor. However, in any of the patent documents, voltage dependency is canceled by using two MOS capacitors and connecting them in parallel in the opposite direction. To realize this, two P-well layers having different potentials are used. It is necessary to make more than one in the semiconductor substrate. Since the P-well layer requires a large area in the semiconductor, the necessity of two or more P-layers is problematic in terms of cost, so that the practicality is poor.

JP-A-61-264812 Japanese Patent Laid-Open No. 5-82741 JP 7-221599 A

  The present invention has been made in the background as described above, and the solution is to reduce the area occupied by the capacitor while reducing the voltage dependency of the capacitor in the switched capacitor integration circuit. An object of the present invention is to provide a switched capacitor integrating circuit having a novel structure.

That is, according to the first aspect of the present invention, the first capacitor, the first switch for turning on / off between one end of the first capacitor and the input terminal, and the other end of the first capacitor are output. And a second switch for turning on and off between the one end of the first capacitor and the inverting input terminal of the differential amplifier. And a second capacitor having one end connected to the inverting input terminal of the differential amplifier and having the other end connected to the output end of the differential amplifier. A switched capacitor integrator is provided in which the other end of the second capacitor and the other end of the second capacitor are always conductively connected.

  In the switched capacitor integrator configured according to this aspect, the other end of the first capacitor is connected to the output end in the same manner as the second capacitor. As a result, the voltage applied to the first capacitor and the voltage applied to the second capacitor can be made very close to each other, so that a voltage-dependent capacitor can be used, and the degree of freedom in design can be expanded. .

  Similarly to the second capacitor, the first capacitor is also connected to the output terminal, so that two capacitors, the first capacitor and the second capacitor, that receive the current expressed by [Equation 3] in the conventional example are provided. Became. As a result, the capacitance value of the second capacitor can be reduced as compared with the conventional case, and the size can be reduced. Incidentally, even if the capacitance of the second capacitor is reduced by the amount of the first capacitor, the integrated value Vout having the same value can be obtained.

  As described above, according to this aspect, since the connection of one end of the second capacitor can be simply changed, the circuit size can be reduced very easily without increasing the number of elements or drastically changing the circuit configuration. It is possible to reduce the influence on the characteristics of the switched capacitor integrator due to the voltage dependence of the capacitor.

  According to a second aspect of the present invention, in the switched capacitor integrator according to claim 1, the control target output terminal of the control target circuit is connected to the input terminal, while the control input terminal of the control target circuit is connected to the control input terminal. The output terminal is connected.

  According to this aspect, the voltage applied to the first and second capacitors can be made the same by using the switched capacitor integrator for the negative feedback control. As a result, there is no problem in using a voltage-dependent capacitor, and the degree of freedom in design can be expanded.

  According to a third aspect of the present invention, in the switched capacitor integrator according to the first or second aspect, the first and second capacitors are constituted by MOS capacitors.

  According to this aspect, since the problem of the voltage dependency of the capacitor is reduced or eliminated, a MOS capacitor having voltage dependency can be employed for the first and second capacitors. Since the capacitance value per unit area of the MOS capacitor is larger than that of other capacitive elements, it can be said that it is extremely effective for miniaturization of the switched capacitor integrator. Further, since the capacitance element can be easily changed, it can be easily realized.

  According to the switched capacitor integrator of the present invention, the influence of the voltage dependency of each capacitor on the characteristics of the switched capacitor integrator is reduced by changing the connection destination of one end of the first capacitor to the output terminal. In addition, the capacitance of the second capacitor can be reduced, and the switched capacitor integrator can be reduced in size by a simple change.

The circuit diagram of the switched capacitor integrator as a first embodiment of the present invention. The circuit diagram of the switched capacitor integrator as 2nd embodiment of this invention. The circuit diagram of the switched capacitor integrator as a third embodiment of the present invention. The operation | movement timing diagram of the switch element shown in FIG. The circuit diagram of the conventional switched capacitor integrator. The voltage characteristic figure of MOS capacity.

  Hereinafter, in order to clarify the present invention more specifically, embodiments of the present invention will be described in detail with reference to the drawings.

  First, FIG. 1 shows a circuit diagram of a switched capacitor integrator 10 as an embodiment of the present invention. First, by turning on the first switch 12 with the second switch 14 turned off, the input terminal 16 and one end of the first capacitor 18 are brought into conduction, and the input voltage Vin is applied to the first capacitor 12. 18 is charged. The other end of the first capacitor 18 is connected to the output end 20. Next, by turning on the second switch 14 after turning off the first switch 12, one end of the first capacitor 18 and one end of the second capacitor 22 are brought into conduction, and are stored in the first capacitor 18. A part of the charged charge is transferred to the second capacitor 22. By repeating this series of operations, charges are accumulated in the first capacitor 18 and the second capacitor 22 and appear as an integrated value in the output voltage Vout of the output terminal 20. One end of the second capacitor 22 is connected to the inverting input terminal 26 of the differential amplifier 24, and the other end of the second capacitor 22 is also connected to the output terminal 20 of the differential amplifier 24. A negative feedback circuit for the differential amplifier 24 is configured. The constant voltage Vref applied to the non-inverting input terminal 28 of the differential amplifier 24 sets a target voltage when the switched capacitor integrator 10 is used for negative feedback control described later. The constant voltage Vref can be arbitrarily set depending on the application to which it is applied.

  In the switched capacitor integrator 10 of the present embodiment, the voltage applied to the first capacitor 18 is such that when the first switch 12 is on and the second switch 14 is off (Vout−Vin), the first switch 12 is off. When the second switch 14 is on, the voltage is (Vout−Vref), while the voltage applied to the second capacitor 22 is represented by (Vout−Vref). Here, if Vin and Vref are set to close values, the voltage applied to the first and second capacitors 18 and 22 can be made much closer than in the prior art. MOS capacitors and PN (P-type semiconductor N-type semiconductor) junction capacitors can also be used, and the degree of design freedom can be expanded.

  The expression representing the characteristics of the switched capacitor integrator 10 of the present invention can also be obtained in the same manner as in the conventional example shown in FIG. First, by alternately turning on and off the first and second switches 12 and 14, the current resulting from the transfer of charge from the input terminal 16 to the second capacitor 22 through the first capacitor 18 is the conventional one. It is expressed by [Formula 2] as in the example. On the other hand, the current flowing into the second capacitor 22 expressed by [Equation 3] in the conventional example is that the capacitors that receive this are the first and second capacitors 18, 22. ] Is shown.

  Here, by solving [Formula 2] and [Formula 5] simultaneously, Formula [Formula 6] representing the characteristics of the integrator shown in FIG. 1 is obtained.

  Comparing [Equation 6] and [Equation 4], it can be seen that the denominator of the coefficient portion is changed from C2 in the conventional example to (C1 + C2). That is, even if the capacitance C2 of the second capacitor 22 is decreased by the capacitance C1 of the first capacitor 18, the same integrated value Vout can be obtained, and the size can be reduced.

  Next, a switched capacitor integrator 30 as a second embodiment of the present invention will be described with reference to FIG. The second embodiment performs negative feedback control of the control target circuit 32 using the switched capacitor integrator 10 of the first embodiment. Specifically, the control target output terminal (terminal that outputs a signal to be controlled) 34 of the control target circuit 32 is connected to the input terminal 16 of the switched capacitor integrator 10 of the first embodiment, and the same. The control input terminal 36 of the control target circuit 32 is connected to the output terminal 20. In the following description, components substantially similar to those of the above-described embodiment are denoted by the same reference numerals as those of the above-described embodiment, and detailed description thereof is omitted.

  When the integrator is used for negative feedback control in this way, the voltage of the control target output terminal 34 of the control target circuit 32, that is, the target value of the input voltage Vin of the switched capacitor integrator 10 is set to Vref. Since Vin≈Vref in the steady state, the voltage applied to the first capacitor 18 is normally (when the gain of the differential amplifier is sufficiently high and a virtual short circuit between the two inputs is established), It is equal to or nearly equal to (Vout−Vref). Since the voltage applied to the second capacitor 22 is also (Vout−Vref), the voltage applied to both capacitors 18 and 22 can be made equal or substantially equal.

  Therefore, by forming both capacitors 18 and 22 using the same capacitive element, the voltage-dependent component of the capacitance value of the coefficient portion of [Formula 6] is reduced and eliminated. This makes it possible to use a MOS capacitor that has been difficult to use because of its voltage dependency, although it has a large capacitance value per unit area, and a significant reduction in size can be realized.

Next, a switched capacitor integrator 38 according to a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, the switched capacitor integrator 10 of the first embodiment is formed using integrated circuit technology. Specifically, the first and second switches 12 and 14 are nMOS (n-channel Metal Oxide).
The first and second capacitors 18 and 22 are formed using p-channel metal oxide semiconductor (pMOS) transistors.

  Here, although nMOS transistors are used for the first first and second switches 12 and 14, depending on the value of Vref and the voltage used to drive the switches, pMOS transistors or nMOSs connected in parallel are used. Transistors and pMOS transistors may be used. A pulse voltage as shown in FIG. 4 is applied to the gate terminals 40 and 42 of the first and second switches 12 and 14 using nMOS transistors, which are alternately turned on (when Von is applied) and off (when Voff is applied). Is repeated. On the other hand, pMOS capacitors are used for the first and second capacitors 18 and 22. There are two types of MOS capacitors: an nMOS capacitor formed using an nMOS transistor fabrication process and a pMOS capacitor formed using a pMOS transistor fabrication process. As shown in FIG. Dependencies are different. In the case of an nMOS capacitor, a larger capacitance value is shown when a positive voltage is applied. On the other hand, in a pMOS capacitor, a larger capacitance value is shown when a negative voltage is applied. In an actual circuit, the MOS capacitor semiconductor layer side is connected to the output terminal 20 of the differential amplifier 24 and used in a region having as large a capacitance value as possible in order to reduce the influence of leakage current generated in the semiconductor layer and the switch. It is desirable to do. Therefore, since the voltage applied to the first and second capacitors 18 and 22 is expressed by (Vout−Vref), it is desirable to use the nMOS capacitor under the condition of Vref> Vout and the pMOS capacitor under the condition of Vref <Vout. .

  As mentioned above, although several embodiment of this invention has been explained in full detail, this is an illustration to the last, Comprising: This invention is not limited at all by the specific description in this embodiment. For example, in the above embodiment, a specific example in which a voltage-dependent MOS capacitor is used for the first and second capacitors 18 and 22 has been described. However, a PIP capacitor or a MIM capacitor having no voltage dependency may be used. Is possible. Even in this case, the capacity of the second capacitor 22 can be reduced, and the size can be reduced.

10, 30, 38: switched capacitor integrator, 12: first switch, 14: second switch, 16: input terminal, 18: first capacitor, 20: output terminal, 22: second capacitor, 24 : Differential amplifier, 26: inverting input terminal, 28: non-inverting input terminal, 32: control target circuit, 34: control target output terminal, 36: control input terminal

Claims (3)

A first capacitor;
A first switch for turning on and off between one end of the first capacitor and an input terminal;
A differential amplifier having an output terminal connected to the other end of the first capacitor and a non-inverting input terminal connected to a constant potential source;
A second switch for turning on and off between the one end of the first capacitor and an inverting input terminal of the differential amplifier;
A second capacitor having one end connected to the inverting input terminal of the differential amplifier and the other end connected to the output end of the differential amplifier;
A switched capacitor integrator in which the other end of the first capacitor and the other end of the second capacitor are constantly connected. While the control target output terminal of the control target circuit is connected to the input terminal,
The switched capacitor integrator according to claim 1, wherein the output terminal is connected to a control input terminal of the control target circuit.   The switched capacitor integrator according to claim 1 or 2, wherein the first and second capacitors are configured by MOS capacitors.

Images