JPS6011970A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the processing time for input of data by using a data collecting circuit to collect previously only effective data from all interface circuits. CONSTITUTION:The register circuits 5a-5g fetch the effective data input flags, end flags and input data out of corresponding interface circuits 2a-2g by the data input signal delivered from a control circuit 6. Then the contents of circuits 5b-5g and the circuit 5a are shifted successively to register circuits 5a-5f and the circuit 6 respectively by the data shift signal. The circuit 6 memories the input data if the effective data input flags are set. While the data shift signal is delivered to the circuits 5a-5g if the end flags are set in reset states 2a-2f, respectively. The above-mentioned processing is carried out until the input of the end flag in a set state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device equipped with a data collection circuit that collects data individually input by a plurality of interface circuits into one place.

Generally, in a data processing device with a built-in program, various data are input from an external device, etc., and data processing is often performed based on the input data.

Therefore, a data processing device with a built-in program may include a large number of interface circuits.

Conventionally, a data processing device with a built-in program has a configuration as shown in FIG. 1 when it has a large number of interface circuits. However, FIG. 1 shows, as an example, a case where there are seven interface circuits for inputting data. In the figure, 1 is a central control circuit, 2a to 2g are interface circuits that input data from external devices, etc., and 3
is a data bus that connects the central control circuit l and the interface circuits 2a to 2g, and includes data lines, address lines,
Consists of lines and control lines. 4a to 4g are data buses for connecting the interface circuits 2a to 2g and external devices, respectively, and are composed of data lines and control lines necessary for interfacing the external devices and each interface circuit 2a to 2g. be done.

Next, the operation will be explained. Each interface circuit 2
Data buses a to 2g input data from external devices or the like using data buses 4a to 4g, respectively. The interface circuits 2a to 2g that have input the data store it and at the same time set a valid data input flag.

The central control circuit 1 operates according to a program, and by specifying the addresses that each of the interface circuits 2a to 2g has, it is possible to input a valid data input flag and data from any interface circuit. In many cases, the valid data input flag and data are manually assigned to the central control circuit 1 by specifying separate addresses.

Therefore, when valid data is input from the interface circuits 2a to 2g, the program of the central control circuit 1 becomes a flowchart as shown in FIG.

In the figure, TF(2a) to IF(2g) mean valid data input flags of the interface circuits 2a to 2g, and when the value is "1", it is valid, and when the value is "0", it is invalid. That is, when reading only valid data, the central control circuit 1 inputs valid data flags from all interface circuits 2a to 2g, and if set, reads data from the interface circuits.

Since the conventional data processing device with a built-in program is configured as described above, it is necessary for the central control circuit to access each of the interface circuits in order to confirm the presence or absence of self-effective data. This has the disadvantage that the central control circuit consumes a large amount of time in the process of reading only valid data from the plurality of interface circuits.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by providing one data collection cycle and collecting only valid data from all interface circuits in advance, central control is possible. It is an object of the present invention to provide a data processing device that can read only valid data from all interface circuits without the circuit checking whether valid data exists in each interface circuit.

An embodiment of the present invention will be described below with reference to the drawings. Third
The figure shows the configuration of an embodiment of the present invention, and shows, as an example, a case where there are seven interface circuits for inputting data. In FIG. 3, l is a central control circuit, 2a to 2g are interface circuits for inputting data from external devices, etc., and 3 is a data bus that connects the central control circuit l and a control circuit 6, which will be described later. address·
Consists of lines and control lines. 4a to 4g are data buses for connecting the interface circuits 2a to 2g and external devices, respectively, and are composed of data lines and control lines necessary for interfacing the external devices and each interface circuit 2a to 2g. be done. 5a~5g
6 is a register circuit that inputs and stores data from the interface circuits 2a to 2g, and 6 is each register circuit 5a to 5.
This is a control circuit (data collection circuit) that outputs a control signal to g and at the same time inputs only valid data. Furthermore, the central control circuit 1 can read valid data input by the control circuit 6.

Next, the operation will be explained. Each interface circuit 2
Data buses 3 to 2g input data from external devices and the like using data buses 4a to 4g, respectively. The interface circuits 23 to 2g that have input the data store it and at the same time set a valid data input flag. Further, the interface circuit 2g keeps the end flag in the full set state, and the other interface circuits 2a to 2f are always kept in the reset state.

The control circuit 6 first sends the data input signal to each register circuit 5a.
Output to ~5g. As a result, register circuits 5a to 5g
are the corresponding interface circuits 2a to 2g, respectively.
More valid data input flag.

Capture and store end flag and input data. Next, the control circuit 6 transfers the data movement Shinno to the register circuit 5.
Output to a~5g. As a result, the flags and data stored in the register circuit 5g are transferred to the register circuit 5f, and the flags and data stored in the register circuit 5f are transferred to the register circuit 5e. In this way, the flags and data are sequentially transferred. It will be done. Furthermore, register circuit 5
The flag and data stored in a are transferred to the control circuit 6. The control circuit 6 stores the input data if the valid data input flag is in the set state, and discards the input data without storing it if it is in the reset state. Further, if the end flag is in a reset state, a data movement signal is output to register circuits 5a to 5g. The above processing is repeated until the end flag of the cent state is input. The control circuit 6, which has received the end flag in the set state, performs data capture or rejection processing according to the state of the valid data input flag, and then outputs data input signals to the register circuits 5a to 5g. By repeating the above processing, the control circuit 6 includes the interface circuit 2a.
Only valid data can be imported from ~2g.

The control circuit 6 sequentially stores the input valid data and sets a flag indicating that it holds valid data. The central control circuit 1 ink-faces the control circuit 6 and reads valid data until its flag is in the reset state. In this case, the program of the central control circuit 1 becomes a flowchart as shown in No. 4-1. ■F in the diagram
is a flag indicating that the control circuit 6 holds valid data, and is valid when the value is 1" and invalid when the value is "0". In this embodiment, the interface circuits 2a to 2g
The register circuits 5a to 5g input data from an external device, etc., and the register circuits 5a to 5g input data from an external device etc.
The timing of inputting flags and data from the input terminals is done asynchronously. Further, the timing at which the central control circuit 1 interfaces with the control circuit 6 and the timing at which the control circuit 6 inputs the flag and data from the register circuit 5a are performed asynchronously.

In the above embodiment, the timing at which the interface circuits 2a to 2g input data from external devices etc. is asynchronous to the timing at which data is output to the register circuits lf358 to 5g. It may be synchronized with Similarly, the timing at which the central control circuit 1 interfaces with the control circuit 6 and the timing at which the control circuit 6 interfaces with the register circuit 5a are asynchronous, but these may also be synchronized using an interrupt or the like.

Further, in the above embodiment, a case has been described in which a programmable control circuit is used as the central control circuit, but a control circuit configured only by hardware may be used, and the same effects as in the above embodiment can be obtained.

As described above, according to the present invention, the data processing device is configured to collect only valid data from a plurality of interface circuits in one place, thereby reducing the processing time related to data input of the data processing device with a built-in program. This has the effect of increasing the data processing capacity of the data processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional data processing device with a built-in program, FIG. 2 is a flowchart for explaining the operation of a conventional data processing device with a built-in program, and FIG. 3 is a diagram according to an embodiment of the present invention. FIG. 4 is a block diagram of a data processing device with a built-in program; FIG. 1... Central control circuit, 23-2g... Interface circuit, 5a-5g... Register circuit, 6... Control circuit (data acquisition circuit). In the drawings, the same reference numerals indicate the same or equivalent parts. Agent: Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] (1) In a data processing device comprising a central control circuit and a plurality of interface circuits for inputting data to the central control circuit, a plurality of register circuits to which data from each of the interface circuits is input;
Data and data that connect the plurality of register circuits in series
A data processing device comprising: a data collection circuit that collects only valid data in all of the register circuits via a bus and a control line, and sends the collected data to the central control circuit.