JP2555171B2 - Bit judgment method - Google Patents

Description

The present invention relates to a bit determination method for determining each bit of data captured by a processor, and an object of the present invention is to perform bit determination at high speed and efficiency by using hardware. In a method for determining each bit of input data composed of a plurality of bits by a device equipped with a microprocessor, a first register in which the input data composed of the plurality of bits is set, and designated by an address signal in the first register A bit decomposing unit for taking out one bit of the bit position to be taken, and taking the taken out one bit to a specific bit position,
The remaining bit positions use a second register that outputs judgment data consisting of a plurality of bits filled with a fixed value of bits, and the judgment data output from the second register is 1,0 bits by software. It is configured to make a judgment.

TECHNICAL FIELD The present invention relates to a bit determination method for determining each bit of data taken in by a processor.

In a system with a microprocessor,
The data received from the outside of the device or the data created inside the device is taken into the microprocessor and data analysis / processing is performed.

[Conventional technology]

As shown in FIG. 5 (a), a microprocessor MPU,
In a computer system having a common bus CBUS and an I / O port, a plurality of, for example, 8-bit data input to the I / O port is taken into an internal register (accumulator) by the MPU in 8-bit parallel and data analysis is performed. In the alarm information and the like, each bit of the multi-bit data sent by the hardware has its own meaning. For example, as shown in FIG. 6 (b), D0 bit is REC (reception unit normal / abnormal), D1 bit is SND (transmission unit normal / abnormal),
...... indicates that the MPU reads 1 or 0 of each bit (although there are unused bits) to know the status of the transmitting / receiving terminal, and stores / stores it.
Display etc.

There are various methods of bit determination, but one of them is shifting by one bit. For example, in FIG. 6 (b), the data bits D0 to D7 are shifted to the right one bit by a shift instruction and the carry bits C are sequentially set to D0, D1, ... And the MPU sets the carry bits C 1,0. Decipher. Another way is to take the AND. For example, D0 in Fig. 6 (b)
For, the AND of 00 …… 001 is taken, and if the result is 1, the first D0 is 1, and if 0, it is 0. The next bit D1 is ANDed with 00 ... 010, and if the result is 0, the first D
If 1 is 0, the first D1 is 1. The same shall apply hereinafter. FIG. 5 shows this flow.

In Figure 4, the input data is In other words, it is assumed that it is 01111101, and is set in the spill accumulator ACC (1). This ACC (1) data and 1 AND with and set the result in ACC (1).
Next, it is checked whether or not ACC (1) = 0, and if it is not 0, a flag FLG1 indicating that the D0 bit of the input data is 1 (is set) is set (in this example, it is set). And). If 0, do not set this flag . In this example, ACC (1) = 0111111101, and AND with 00000001 is 00000001, so ACC (1) = 0? Is NO, And

Next input data again Set to ACC (1), and this time And take. Then, check whether ACC (1) = 0, and if 0, If not 0 And The same applies hereinafter.

The processing flow of FIG. 4 is an example, and the bit determination unit returns in a loop or receives data. There are various methods, such as holding in another accumulator ACC (2) and moving to ACC (1) at the time of determination. In any case, bit determination is performed by software processing.

[Problems to be Solved by the Invention]

In the bit judgment by such software or firmware, for each data that is significant (meaningful) with respect to the data that is continuously collected, and each time the bit configuration changes (for each data A task to perform bit judgment processing is required every time the bit allocation changes), and it takes time to perform bit judgment processing (this has a large effect when processing time is a problem), program amount (hence memory capacity) Grows. There is a problem such as.

When bit determination is performed by software processing, the problem is that bit decomposition of received data must be performed for each bit for which determination is to be performed (the above-mentioned shift by 1 bit, And that's it). If the significant bits are simply (unified) determined, for example, if the 1st to 4th bits of the bits contain the necessary information, and the meaning of each bit is always the same, simply loop the process. If so, it does not pose a big problem in terms of program amount, but it is the same in terms of processing time, and this does not solve the problem.

An object of the present invention is to make a bit decision quickly and efficiently by using hardware as well.

[Means for solving the problem]

As shown in FIG. 1, in the present invention, bit determination is performed by software 10 and hardware 20, and software 10 has a function of taking received data into accumulator ACCA.
12 and a bit judgment function 14 are provided. Further, the hardware 20 is provided with an IO register (PSCONV-I) 22, a bit disassembly unit 24, and an IO register (PSCONV-O) 26.

When the software 10 fetches the received data ($ 7D in this example) into the accumulator ACCA, the I / O of the hardware 20
Send to O register 22. The bit disassembling unit 24 receives an address signal (not shown) and sets each bit of the I / O register 22 to I
Output to / O register 26. The content of the I / O register is variable only for one bit received from the bit disassembling unit 24, and the rest is constant. In this example, only the MSB is variable, so the I / O register
Contents of 26 Is. Software 10 uses this I / O register 26 Is received by the accumulator ACC (1), and it is checked whether ACC (1) is 0 or not. If it is 0, the bit is 0, and if it is 1, 1
Flag FLGi in the above example To ACCA and ACC (1) are the same accumulator.

[Action]

As described above, in the present invention, the bit decomposition of the bit judgment processing is performed by hardware, and the portion for writing the data to be judged to the register and the portion for reading the bit decomposition result from the register are I / O, and the interface between the hardware and the software is set. The bit determination processing can be performed at high speed by adjusting the.

In FIG. 1, hardware 20 receives data from software 10. Capture it and write it to I / O register 22, then when software 10 reads I / O register 26, bit decomposition result , Which can be loaded into the accumulator ACC (1) and a bit decision can be made in the next step.

Figure 2 shows the contents of the I / O register 26. In this example, the input data is Therefore, the D0, D1, D2, ... D8 bits are 1,0,1, ... 0
The contents of register 26, which is the MSB, PSCONV01,
2, same 3, ... same 8 This is the software accumulator ACC
It is sequentially set to (1).

Although each bit of the received data has a vacant (unused, and therefore meaningless) bit, if this address is not given to the bit disassembling unit 24, only the valid bit excluding the vacant bit is bit. It is possible to make a decision, and an effective high-speed bit decision can be made.

In general, the arithmetic processing of the processor is slow, and by using this method, the number of arithmetic operations can be reduced, the number of program steps can be reduced, and the speed can be increased. For example, the following instruction group is sufficient for the program that performs the above processing.

LDAA DATA STAA PSCONV-I LDAA PSCONV-0 BEQ LVL1 STAA FLG1 LVL1 LDAA PSCONV-0 + 1 BEQ LVL2 where LDAA is Load Acmltr A and STAA is Store Acmltr
A, BEQ, Branch If = Zero, LVL are labels. Load the data to accumulator A (Acmltr A), store it in PSCONV-I from accumulator A (Acmltr A), and latch it to PSCONV, then PSCONV and PSCONV
By reading one after another as +1, PSCONV + 2, ..., the result of bit decomposition can be obtained. Bit determination processing can be performed.

〔Example〕

Since the bit disassembling unit 24 only needs to convert the received multi-bit parallel data into serial data, it can be realized with simple hardware. FIG. 3 shows an example thereof. The bit disassembling unit 24 in this example is an 8-channel multiplexer (8 →
1 selector) 24A. D0 to D7 are data input terminals, A, B, C
Is the input end of addresses A0, A1, A2, Y is the 1-bit output end, EN
Is an enable terminal.

I / O register 22 has data input terminals 1D to 8D and output terminal 1
Equipped with Q to 8Q, clock terminal CLK, and enable terminal EN, when write command W.PSCONV is input to the CLK terminal, each bit D0 to D7 of input (reception) data RD is taken in and output from 1Q to 8Q . The I / O register 26 includes data input terminals 8A to 1A, output terminals 8B to 1B, and enable terminal EN. Only one of the data input terminals, 1A (this is the MSB), is connected to the output terminal Y of the multiplexer 24A, and the remaining 2A to 8A.
Is a constant potential, and is connected to the ground in this example, and all 0s are data. Therefore, the output data D0 to D7 of this I / O register 26 is become.

One of the input data bits of the multiplexer 24A is output from the terminal Y by the addresses A0 to A2, and the read command R.
Input PSCONV to the enable pin EN of the I / O register. A
When this process is repeated 8 times by changing 0 to A2, the output data with each bit of the input data RD as the MSB can be output from the I / O register 26.

Instead of inputting the output bit of the multiplexer 24A to the MSB terminal 1A of the register 26, it may be input to the LSB terminal 8A or the like.

〔The invention's effect〕

As described above, in the present invention, a part of the software processing (a portion that the hardware is good at) is caused to be executed by the hardware in the data processing conventionally performed by the software.
By executing the processing as firmware, the program can be simplified and the processing speed can be increased. In particular, when the data is input one after another and the bit determination of the data is performed one after another, the advantage that the speed can be increased is very large.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is an explanatory view showing an example of read contents of an I / O register, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. Explanatory drawing, FIG. 5 is explanatory drawing of bit determination. In FIG. 1, 22 and 26 are I / O registers, 24 is a bit disassembly unit, and 14 is a judgment function.

Claims (1)

(57) [Claims] 1. A device comprising a microprocessor,
In a method of determining each bit of input data composed of a plurality of bits, a first register (22) in which the input data composed of a plurality of bits is set, and a bit designated by an address signal in the first register (22) A bit disassembling unit (24) for taking out one bit at a position, and taking out the taken out one bit at a specific bit position, and outputting the judgment data consisting of a plurality of bits in which the remaining bit positions are filled with bits of a constant value. A bit determination method characterized by using a second register (26) and determining 1,0 bits by software with respect to the determination data of the output of the second register.